JPH05298837A - Error correcting method - Google Patents

Abstract

PURPOSE:To prevent making an erroneous correction to erroneous data in the case smaller number of inspection codes are used to constitute a digital audio signal recording and reproducing device and to prevent the occurrence of a malfunction for which other original data are mistaken and judged that no error is present thereon. CONSTITUTION:In a signal arranging diagram in which signals are arrayed in row and column directions, recording regions 1, 2, 3 and 4 are provided on SYNC, ID, audio and auxiliary signals, respectively. After the correction processing of signal errors in the column direction by C1 codes, a generating function is formed using matrix product codes is formed in order to prevent the occurrence of the erroneous recognition of signal errors in the row direction by C2 codes. Then, the positions of erasing flags are compared which are obtained from the roots of the generating function. When the positions of signal errors in respective row and column directions are coincided, error corrections are performed and when the error positions are different, no error correction processing takes place.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction system for digital audio signals.

[0002]

2. Description of the Related Art Recently, as represented by compact discs (CD) and digital audio tapes (DAT),
Audio equipment using digital signal processing has been put into practical use. The conventional signal error correction method used for DAT will be described below (for details, see "Illustrated DAT Reader" by Ohtasha, 1988, published by Heitaro Nakajima and Kentaro Otaka.
It is described in). FIG. 8 is a signal arrangement diagram in which digital audio signals used in a conventional DAT are combined and arranged in the vertical and horizontal directions by a dual Reed-Solomon code. In the figure, the audio data and the C1 code (inner code) are arranged in the row direction.
Check codes called are arranged vertically. In the column direction,
The voice data is arranged on the left and right, and a check code called a C2 code (outer code) is arranged in the middle. In the Reed-Solomon code, the minimum unit of data forming a code is not one bit but a plurality of bits (8 bits) as a unit, which is called one symbol.

FIG. 9 is a signal configuration diagram showing an example of signal arrangement in the column direction of FIG. As shown in the figure, the Reed-Solomon code is made by collecting a plurality of symbols. Here, an information code such as a digital audio signal is recorded in the first 13 symbols of the 32 symbol signals in the column direction, a check code is recorded in the subsequent 6 symbols, and the remaining information is recorded in the last 13 symbols. The code is recorded. Such a code structure is called a (32.26) Reed-Solomon code, and a large number of signals in the column direction are arranged in each row of the signal arrangement diagram shown in FIG. The C2 code is a check code of 32-26 = 6 symbols, and the minimum distance between codes that determines the correction capability of the code is the number of parity + 1 = 7. Since the code error distance is compared in symbol units, one symbol is 8
If there are 8 bits, all signal errors within 8 bits are regarded as the same.

For example, the total number of data in the column direction is n symbols,
If the check code is k symbols, the audio data is (n-
k) Become a symbol. If the transmitted 2 ^nk kinds of data each have at least d errors,
The data is said to be separated from the original data by a distance d. Therefore, although there are 2 ⁿ patterns to be received, a pattern separated from the original pattern by the number d in which an error has occurred is obtained in the set of all received data indicating the inter-code distance.

In the aggregate of all received data, if each transmit data is separated by a correctable distance t and the sets of patterns do not overlap, it is necessary to select the pattern with the shortest distance up to t errors. It becomes the original data. Even if there are t or more errors beyond this limit, it is not possible to specify which was the original data unless it is still within the set of patterns of distance t from other original data. However, in this case, it can be determined that there was an error. However, if there is a larger error, it will fall within the set of the distances t of other patterns, and therefore it will no longer be possible to correct it correctly, and it will be erroneously corrected to erroneous data. Further, in the worst case, the original data may be garbled, which may give the illusion that there is no error. As described above, the error correction code can completely correct an error within a certain range, but when it exceeds the limit, it causes various malfunctions.

Generation of parity and error correction and detection using the result are all performed by calculation in symbol units on the Galois field. For example, let us consider a Reed-Solomon code composed of four information codes and four check codes. The error correction and detection are performed by multiplying each code word V by the parity check matrix H shown in the following equation (1) and obtaining the solution of the simultaneous equations so that the value H · V becomes 0.

[Equation 1] Note that α is the root of the modal polynomial, and α ⁰ , α ¹ , α ² , α ³
... is each code word V (D ₀ , D ₁ , D ₂ , D ₃ , ...
・) Is a coefficient indicating the weighting.

[0007]

In such a conventional configuration, when the C1 code has 4 symbols and the C2 code has 6 symbols as in DAT, an erroneous operation of further erroneously correcting erroneous data, The probability of a malfunction that would be garbled into other original data and that there was no error was quite low. However, in such an error correction method,
If the number of check codes is reduced, there is a problem that erroneous correction or the like is performed with high probability.

The present invention has been made in view of the above conventional problems, and corrects a signal error by using a small number of check codes, and when the error correction is determined, the correction process is stopped. It provides an error correction method that can be performed.

[0009]

SUMMARY OF THE INVENTION The present invention uses a symbol unit code composed of a number of binary bits, and M number of signal codes in the row direction and N number of signal codes in the column direction are respectively m.
(M> m) outer codes for checking in the row direction and n (N>)
n) When transmitting and receiving a product code to which inner codes for checking in the column direction are added, and when a code error is detected, the occurrence position and magnitude thereof are calculated using the root of the generator polynomial to correct each error. This is an error correction method to be performed, and after the completion of the correction processing by the inner code, j errors on the code string of the product code in the outer code direction are i
In consideration of the possibility of erroneous detection of individual errors (j> i), error correction processing is performed by a polynomial using the position of the error obtained by calculation using the outer code and the inner code of the product code. In this case, the position of the erasure flag set for an error exceeding the limit of the error correction capability is compared, and error correction is performed only when the respective error positions match, and when the respective error positions differ. Is characterized in that the error correction process is not performed and the correction flag is added to the information before the error correction and the information is output.

[0010]

According to the present invention having such characteristics, the product code is generated by adding the check code to the signal code in the row direction and the signal code in the column direction containing the voice information. The audio data recording area is scanned to read the signal, and error correction processing is performed using a polynomial using the inner code of the product code. At this time, the position of the error obtained by calculation using the outer code is compared with the position of the erasure flag set for the error exceeding the limit of the error correction capability, and if the respective error positions match. Error correction is performed only on. If the respective error positions are different, error correction processing is not performed, and a correction flag is added to the information before error correction and output. By performing the processing in this way, noise parasitic on the demodulated information can be minimized.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An error correction system according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a signal arrangement diagram of audio data used in the error correction system of this embodiment. In the figure, each interleaved data is arranged two-dimensionally, and areas for recording data of different attributes are provided in each row and column direction. That is, the synchronization signal (S
(YNC) recording area 1, ID code recording area 2, audio data recording area 3, auxiliary data recording area 4, vertical parity recording area 5, horizontal parity recording area 6. The code of the horizontal parity recording area 6 is called an inner code or C1 code and is a code for error detection and correction of audio data in the column direction.
The code of the vertical parity recording area 5 is called an outer code or C2 code and is a code for error detection and correction of audio data in the row direction.

Focusing on the code string in the row direction indicated by the arrow V in the figure, the code array as shown in FIG. 2 is obtained. That is, the portion of the vertical parity recording region 5 in FIG. 1, check codes P _0,
P ₁ and P ₂ are recorded as outer codes with 3 symbols (generally m symbols), and information code D ₀ ,
6 symbols of D ₁ ... D ₅ are recorded, and a total of 9 symbols (generally M symbols) are obtained. Thus, the number of symbols of vertical parity is one symbol less than that of the C1 code of the conventional error correction system. The horizontal parity C1 code of this embodiment is 8 symbols (generally n symbols).
I am trying. The number of symbols N in the column direction is 13 in this embodiment.
2 symbols.

FIG. 3 is a block diagram showing a configuration of an audio signal processing device 10 for performing such signal arrangement. In the figure, the data rearranging unit 11 is used for the terminal 1 at the time of recording.
This is a circuit that rearranges the arrangement order of the audio data and the auxiliary data input from 1a at the time of recording in two dimensions. The data converted here is given to the outer code processing unit 12. or,
The data rearrangement unit 11 converts the two-dimensional error-correction-processed data output from the outer code processing unit 12 during reproduction into one-dimensional data, demodulates audio data and auxiliary data during recording, and outputs the demodulated data to the terminal 11a. It is a circuit to do. Outer code processing unit 1
As shown in the signal arrangement diagram of FIG. 1, reference numeral 2 is a vertical parity code (C2) added in the vertical direction of the signal portion of the audio data and auxiliary data at the time of recording, and the signal is added to the inner code processing portion 13
And a signal in the row direction is extracted for each column from the two-dimensional signal given from the inner code processing unit 13 at the time of reproduction, and the error correction process for each column shown in FIG. 2 is performed.

Next, the inner code processing unit 13 adds the C1 code to the audio data and the auxiliary data in the horizontal direction at the time of recording and gives the signal to the ID / SYNC processing unit 14, and from the ID / SYNC processing unit 14 at the time of reproduction. This is a circuit that extracts a horizontal (column direction) signal for each row from a given two-dimensional signal and performs error detection processing for each row. Inner code processing unit 13
If error correction is not possible for each row, the error detection is performed and then the erasure flag is added to the signal end of the row. The ID / SYNC processing unit 14 adds an ID code and SYNC data in the column direction of audio data and auxiliary data at the time of recording, and at the time of reproduction, the signal recording / reproducing unit 1
5 is a circuit for removing the ID code and the SYNC data from the signal reproduced from FIG.

The signal recording / reproducing unit 15 divides the two-dimensional data shown in FIG. 1 into 9 rows at the time of recording and outputs the signal to the magnetic head 16 for each row, and at the time of reproducing, the magnetic head 1 is reproduced.
6 is a circuit that detects SYNC data from the signal read from 6, and separates the data into row units and arranges them in the column direction to output two-dimensional data to the ID / SYNC processing unit 14. The magnetic head 16 is a head that is attached to the outer circumference of a rotating drum and rotates to record or read a signal on a helical scan track of a magnetic tape.

FIG. 4 is an explanatory diagram of a track pattern of a magnetic tape when a signal is recorded by using the magnetic recording / reproducing apparatus including the audio processing apparatus 10. As shown in FIG. 4A, tracks T1, T2, T3, ... Tn are formed on the magnetic tape 20 by scanning with the magnetic head 16. Each track T is provided with a region V for digitally recording a video signal and a region A for digitally recording an audio signal. When the area A is scanned in the X direction, the signals of the nine blocks B1 to B9 are reproduced as shown in the signal arrangement diagram of FIG. For example, in the case of NTSC video and audio signals, one frame consists of 10 tracks,
The signals of 2 channels of L and R in one frame are recorded on 5 tracks respectively. For example, each block B has 12
Eight symbols (generally N−n symbols) of audio data and, for example, eight symbols (generally n symbols) of C1 code are recorded, and the C1 code and the C2 code are completed in the area A of one track. Therefore, as shown in FIG. 4B, when the region A is scanned in the X direction, the signals of one block are arranged in one column, and the column signals are arranged in nine blocks in the row direction.
Two-dimensional data shown in is obtained.

The operation of the error correction system of the present embodiment thus constructed will be described with reference to the flowchart of FIG. FIG. 5 is a flowchart showing the operation of the error correction processing of the audio signal processing device 10 of FIG. Also, FIG.
An example in which a signal error occurs in the recording area 3 of the audio data shown in FIG. In this figure, it is assumed that a signal error occurs in each of the areas Bx to Bz in the column direction. Also R1, R7
There is no signal error in any row in the range of
There is one signal error in the R3 range, two signal errors in the R3 and R5 range, and three signal errors in the R4 range.

In the flowchart shown in FIG. 5, when the audio signal processing device 10 starts its operation, the magnetic head 16 scans, for example, the track T1 of the magnetic tape 20, and the area A
Read the signal. The signal recording / reproducing unit 15 is the magnetic head 1.
The signal of No. 6 is amplified and waveform-shaped, and the digital data of the blocks B1 to B9 is arranged in the state shown in FIG. 1 by using the SYNC data. In step 21, the inner code processing unit 1
3 uses C1 code to check the presence / absence of a signal error in the data sequence in each column direction. If there is a signal error, the error position is corrected, and if the error cannot be corrected, the erasure flag is added to the column. That is, as shown in FIG. 6, if there are errors in the three areas Bx to Bz, three erasure flags are added. Next, the outer code processing unit 12 reads the data string in the row direction as shown in FIG. 2 and checks the presence or absence of a signal error in each row direction using the C2 code.

Here, a method of decoding the error correction code will be described. When the number of errors in the row direction in FIG. 6 is calculated, only two or more errors can be determined within the range of R3, R4, and R5. Also, in an extreme case, it may be judged as one error. Here, consider a case where it is erroneously determined that only three errors actually exist.

The syndromes S ₀ , S ₁ , S ₂ of the signal in the row direction including the C2 code as shown in FIG. 2 are shown below (2).
It is defined as in (4). S ₀ = D ₅ + D ₄ + D ₃ + D ₂ + D ₁ + P ₂ + P ₁ + P ₀ (2) S ₁ = α ⁸ D ₅ + α ⁷ D ₄ + α ⁶ D ₃ + α ⁵ D ₂ + α ⁴ D ₁ + α ³ D ₀ + α ² P ₂ + αP ₁ + P ₀ (3) S ₂ = α ¹⁶ D ₅ + α ¹⁴ D ₄ + α ¹² D ₃ + α ¹⁰ D ₂ + α ⁸ D ₁ + α ⁶ D ₀ + α ⁴ P ₂ + α ² P ₁ + P ₀ (4)

When the relationship between the syndromes S ₀ , S ₁ and S ₂ satisfies the following equation (5), it is judged that there is no signal error. S ₀ = S ₁ = S ₂ = 0 (5) When the relationship between the syndromes S ₀ , S ₁ , and S ₂ satisfies the following expression (6), it is judged as a single error. S ₁ ² + S ₀ · S ₂ = 0 (6) Then, if the relationship between the syndromes S ₀ , S ₁ and S ₂ satisfies the relationship of the following equation (7), it is judged that the double error or more. Then, the erasure correction is performed. S ₁ ² + S ₀ · S ₂ ≠ 0 (7)

Here, as shown in FIG. 2, among the data D _{5 to} D ₀ and P _{2 to} P ₀ of 9 symbols, D ₃ , D ₁ and P are included.
_It is assumed that errors (e ₆ , e ₄ , e ₁ ) actually occur at 3 locations of ₁ and that the syndrome happens to satisfy the equation (6) and a single error (i-th symbol out of 9 symbols has an error e _i Assuming that there is an erroneous judgment), the following relationships (8) to (10) are established. S ₀ = e ₆ + e ₄ + e ₁ = e _i (8) S ₁ = α ⁶ e ₆ + α ⁴ e ₄ + α e ₁ = α ⁱ e _i (9) S ₂ = α ¹² e ₆ + α ⁸ e ₄ + α ² e ₁ = α ²ⁱ e _i (10)

In the equations (8) to (10), + represents an exclusive OR, so that if an arbitrary value is A, the following equation (11) is established. A + A = 0 (11) Next, by substituting the equation (8) into the equation (9), the following equation (12) is obtained. α ⁶ e ₆ + α ⁴ e ₄ + αe ₁ = α ⁱ (e ₆ + e ₄ + e ₁ ) (12)

By rearranging the equation (12) using the equation (11), the following equation (13) is obtained. (Α ⁶ + α ⁱ ) e ₆ + (α ⁴ + α ⁱ ) e ₄ + (α + α ⁱ ) e ₁ = 0 (13) Similarly, when the formula (8) is substituted into the formula (10), the following ( 1
Equation 4) is obtained. α ¹² e ₆ + α ⁸ e ₄ + α ² e ₁ = α ²ⁱ (e ₆ + e ₄ + e ₁ ) ... (14) When formula (14) is rearranged using formula (11), the following (1
Equation 5) is obtained. (Α ⁶ + α ⁱ ) ² e ₆ + (α ⁴ + α ⁱ ) ² e ₄ + (α + α ⁱ ) ² e ₁ = 0 (15)

Next, using equations (13) and (15), e ₁ ,
By solving for e ₄ , the following equations (16) and (17) are obtained.

[Equation 2]

Therefore, when i = 1, 4 or 6, that is, when the erroneously detected position matches the error position, (16), (1
The right side of the expression (7) becomes 0 or infinity, and this expression does not hold. However, in the case of i = 0, 2, 3, 5, 7, and 8, if e ₁ and e ₄ satisfying the equations (16) and (17) occur for any e ₆ , the actual occurrence 3 A double error is judged to be a single error and false detection is performed.

The probability of false detection in such a case is 6/2.
55 ² = 9.227 × 10 ^-5 , which is a frequency that cannot be ignored considering the number of audio signal data. When erroneous detection is performed, the position where the error exists is the position (i = 0, 2, 3, 5, 7, 8) other than the position where the error actually exists. Therefore, the data at a position different from the position where the error is actually made, that is, the data which is not actually wrong is corrected. Therefore, when the erroneously corrected digital audio signal is converted into an analog audio signal, it becomes noise.

Now, in step 22 of the flow chart shown in FIG. 5, when no error is detected from the signal in the row direction of FIG. 1 or two or more signal errors are detected,
The process proceeds to the subroutine 23, and another error correction process S1 is performed. If the number of errors is 0, no correction process is performed. Also (7)
When the expression is satisfied, it is determined that the error is double or more, and the processing such as erasure correction is performed in the subroutine 23. Next, in step 22, if the equation (6) is satisfied and the number of errors is 1, the process proceeds to step 24, and the position of the erasure flag added to the data in the column direction is referred to.

In the next step 25, the number of disappearance flags is checked. If this number is not 3, the process proceeds to the subroutine 26, and another error correction process S2 is performed. If the number of disappearance flags is 3, it is determined that the signal in the area indicated by R4 in FIG. 6 has been read. Therefore, the process proceeds to step 27, and the position of the disappearance flag is checked. Then, in step 28, it is checked whether or not the error position viewed from the row direction and the position of the erasure flag added in the column direction match. If they do not match, the process proceeds to step 29, where it is determined that the detection is erroneous and the correction process is stopped. In this case, information indicating that the correction processing is not performed is sent to the data rearrangement unit 11, signal processing such as interpolation processing is performed in the next step 30, a correction flag is added, and audio data is output.

As shown in FIG. 6, information obtained by error correction in the horizontal direction (horizontal parity direction) indicates that there are errors in three of the nine symbols in the vertical direction (vertical parity direction). Regardless, if the number of errors derived by calculation is 1, and the position is different from the position information obtained from the error correction process in the horizontal parity direction, there is a high possibility of false correction detection. It will be.

If it is determined in step 28 that there is one error point due to the error correction calculation using the syndrome and that one point matches the error position information obtained in the horizontal parity direction, the process proceeds to step 31. Ordinary error correction processing is performed to reproduce the original voice data. In this way, the error correction process is completed. By the above-described processing, it is possible to erroneously correct an error in a signal and minimize noise parasitic on a signal-processed audio signal.

Here, the case where the information code is 6 symbols and the check signal is 3 symbols and the triple error is erroneously corrected as the single error has been described as an example of the operation. The same operation is performed when the combination is different from the above example. Further, the error correction processes S1 and S2 in FIG. 5 are the same as the error correction method that has been conventionally performed and are not the subject of the present invention, and therefore the description thereof will be omitted.

FIG. 7 is a table showing combinations of actual signal errors and signal errors detected by the voice signal processing device 10. As shown in the figure, the single error can be completely corrected, but when the single error is detected, the probability that the actual signal error is erroneously detected as the triple error is extremely high. Therefore, the above-mentioned processing is performed. However, the probability of erroneous detection such as an actual quintet error being a triplet error or a singlet error is extremely low, and it has been confirmed that this probability does not hinder the reproduction of voice. Therefore, as shown in the lower part of the table of FIG. 7, it can be said that the erroneous detection for the quintuple error or more does not need to perform the correction process.

Although the product code has a structure in which the inner code and the outer code are orthogonal to each other as shown in FIG. 1, the both codes may be obliquely crossed. Further, in the present embodiment, the erasure flag set when the error correction capability limit is exceeded has been described. However, if the erasure flag set when the capability limit is reached, for example, if there are 8 symbols in the inner code, It is also possible to use a flag added when the quadruple correction process is performed.

[0035]

As described in detail above, according to the present invention, in consideration of the possibility of erroneous detection on the code string in the column direction of the product code, an error exceeding the limit of the error correction capability is considered. The correction flag is added to the information before the error correction and the information is output. Therefore, the number of check codes is reduced, and when an erroneous correction occurs, the effect of minimizing noise parasitic is produced. Further, it becomes possible to correct a signal error by using a small number of check codes, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a signal arrangement diagram used in an error correction system according to an embodiment of the present invention.

FIG. 2 is a layout diagram in the row direction of signals including audio data according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of an audio signal processing device in this embodiment.

FIG. 4 is a format of a signal including audio data recorded on a magnetic tape in this embodiment.

FIG. 5 is a flowchart showing the operation of the audio signal processing device in this embodiment.

FIG. 6 is an explanatory diagram showing an example of a signal error distribution according to the present embodiment.

FIG. 7 is an explanatory diagram showing a combination of signal errors in the present embodiment.

FIG. 8 is an example of a signal arrangement diagram used in a conventional signal error correction method.

FIG. 9 is a signal arrangement diagram in the column direction in the conventional signal error correction method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 sync signal recording area 2 ID code recording area 3 audio data recording area 4 auxiliary data recording area 5 vertical parity recording area 6 horizontal parity recording area 10 audio signal processing device 11 data rearranging section 12 outer code processing section 13 inner code processing section 14 ID code / SYNC processing unit 15 Signal recording / reproducing unit 16 Magnetic head 20 Magnetic tape

Claims (1)

[Claims] 1. A code in a symbol unit composed of a number of binary bits is used, and m (M> m) number of signal codes in M row directions and N column direction signal codes are used. A product polynomial in which an outer code for checking in the row direction and an n (N> n) inner code for checking in the column direction are added and received, and when a code error is detected, a generation position and a magnitude thereof are generated. Is an error correction method in which each of the error corrections is performed by calculating using the root of, and j errors on the code string of the product code in the outer code direction are converted into i errors ( In consideration of the possibility of erroneous detection that j> i), the error position obtained by the calculation using the outer code and the error correction processing by the polynomial using the inner code of the product code are performed. Compare the position of the erasure flag set for an error that exceeds the limit of error correction capability, Characteristic is that error correction is performed only when each error position matches, error correction processing is not performed when each error position is different, and a correction flag is added to the information before error correction and output. Error correction method.