JPH05298246A - Time division transfer device for data - Google Patents

Abstract

PURPOSE:To improve data transfer efficiency when the data are transferred in time division among plural modules via a common data bus. CONSTITUTION:A system control part 5 receives a data transfer request from an external data processor 2 and gives a bus slot time setting command to a bus controller 4 in response to the access time of the processor 2 as well as a bus slot setting command. The controller 4 transmits the slot enable signal proper to a designated bus slot at the designated bus slot time. An interface circuit 3 sequentially compares the slot numbers set at the part 5 with the slot enable signal and transfers the data to a bus line 1 when the coincidence is secured between the slot number and the slot enable signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention connects modules constituting a data processing system with a common data bus,
The present invention relates to a time-division transfer device for data that transfers data between modules by using the data bus in a time-division manner by each module.

[0002]

2. Description of the Related Art Heretofore, the following devices have been known as devices for transferring data between respective modules constituting a system by utilizing a common data bus in a time division manner. This device relates to a plurality of modules connected to a common bus line, and a bus controller that controls time-division transfer of data between the modules and a module that performs data transfer in response to a request from the module. , And a system control unit that determines a bus slot used for data transfer. Here, the bus slot is a minimum time unit preset for data transfer between modules.
When data transfer is performed in a time-division manner between a plurality of modules, a bus slot corresponding to each data transfer is set, and a group of these bus slots appears repeatedly. The repetition time of a group of bus slots is referred to herein as a bus cycle.

A detailed description will be given below. For example, the data transfer X from the module A to the module B, the data transfer Y from the module B to the module C, and the data transfer Z from the module C to the module D are used in a time division manner on a common bus line. I try to go. Each module that intends to transfer data requests the system controller to transfer data. In response to this, the system control unit determines the bus slot # used for data transfer X, Y, Z.
Set X, #Y, and #Z. Bus slots #X, #Y,
#Z is composed of a plurality of bits of data. The system controller uses the set bus slots #X, #Y, #Z.
To the corresponding module to notify the slot numbers used for each data transfer and to issue a command to the bus controller to generate the bus slots #X, #Y and #Z. Based on this command, the bus controller controls signals corresponding to the bus slots #X, #Y, and #Z (hereinafter referred to as slot enable signals).
Is repeatedly output to the control bus in the bus line at regular time intervals. Therefore, each bus slot #X, #Y,
If the time assigned to #Z, that is, the time during which each slot enable signal is output to the control bus is, for example, 200 nsec, the bus cycle in this case is 600 nsec.

Each module issuing a data transfer request compares the slot number given by the system control unit with the slot enable signal appearing in the control bus. Outputs data to the data bus or takes in data on the data bus. In this way, each module identifies the bus slot that is individually set according to the request from each module and exchanges data, so that data can be transferred between multiple modules using a common bus line. Are time-divisionally transferred.

[0005]

However, the above-mentioned conventional apparatus has the following problems. That is,
In the conventional device, the time width assigned to each bus slot, that is, the time width when the slot enable signal corresponding to each bus slot is output to the control bus (hereinafter referred to as bus slot time) is always constant. In order to smoothly transfer data between modules, it is necessary to set the bus slot time according to the module with the slowest access time. For example, when the access time of the module A is 200 nsec, the access time of the module B is 250 nsec, and the access time of the module C is 200 nsec, the bus slot time is set to 250 nsec. 50n per data transfer
This means that a time loss of sec has occurred. As described above, in the conventional device, if at least one of the plurality of modules has a slow access time, the bus slot time is set according to the module, so that the performance of other modules with a fast access time is improved. However, there is a problem in that the system cannot be fully utilized and the system as a whole has low data transfer efficiency.

Further, in order to prevent a decrease in transfer efficiency of the entire system as described above, an existing module having a slow access time may be replaced with a new module having a fast access time. Since the module cannot be used effectively, another problem arises that the development period of the system becomes unreasonably long and the cost required for realizing the system increases.

The present invention has been made in view of such circumstances, and it is possible to perform time division data transfer between modules relatively efficiently and effectively use existing modules. It is an object of the present invention to provide a time-division transfer device capable of transmitting data.

[0008]

In order to achieve the above object, the present invention has the following constitution. That is, the present invention sets a bus slot which is a minimum time unit of data transfer and repeats a bus cycle composed of a plurality of bus slots according to the number of data transfer requests,
A device for time-division transfer of data, comprising a plurality of modules connected to a common data bus for transmitting and receiving data through the data bus, bus control means for controlling the time division transfer of the data exchange, A module and a system control means provided in association with the bus control means, wherein the system control means receives the data transfer request from each module, and thereby the bus control means receives the data transfer request. A command for setting a necessary bus slot and a command for setting a bus slot time according to the access time of the module for data transfer are issued, and the module for data transfer is informed of the slot number used for data transfer. The control means transfers the data based on the bus slot setting command from the system control means. The slot enable signal specific to each bus slot used is repeatedly transmitted, and the time for transmitting each slot enable signal is controlled based on the bus slot time setting command from the system control means. A series of slot enable signals sent from the bus control means are sequentially compared with the slot number given in advance by the system control means, and data is transferred to and from the data bus based on the fact that they match. ..

[0009]

The operation of the present invention is as follows. When there is a data transfer request from each module, the system control means issues a command to the bus control means to set a bus slot used for the data transfer, and a period for generating the bus slot (bus slot time). Issue a command to set. The system control means grasps the access time of each module in advance, and the bus slot time is set according to the access time of the module that has requested the data transfer. Further, the system control means notifies the module relating to the data transfer of the slot number used for the data transfer. Based on the command from the system control means, the bus control means sends a slot enable signal specific to the designated bus slot for the designated bus slot time. On the other hand, the module related to data transfer compares a series of slot enable signals sent from the bus control means with a slot number preset by the system control means, and based on the fact that both match, the data bus is transferred to the data bus. Transfer data to and from it.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a data time division transfer device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a data time division transfer device. The device according to the present embodiment is composed of the following elements.

The bus line 1 includes interface circuits 3 (3 ₁ , ..., 3 _i , 3 _i , 3 _i , 3 _i , 2 _i ) provided corresponding to a plurality of external data processing devices 2 (2 ₁ , ..., 2 _i , ..., 2 _n ). … 、
By performing data transfer between 3 _n ) in a time division manner, the interface circuits 3 commonly use each other. In the present embodiment, the bus line 1 is composed of a data bus consisting of 32 signal lines and a control bus consisting of 5 signal lines. The external data processing device 2 and the interface circuit 3, which are paired with each other, correspond to the module in the present invention.

The type of the external data processing device 2 is not particularly limited. For example, in the case of an electronic plate collecting system used in a plate making process, a reading scanner for reading an original image or image data read by the scanner is used. An external image storage device such as an optical disk for storing, an image processing device that cuts out a specific pattern from the image data read from the external storage device, performs a layout process on each pattern, or displays a layout-processed image Monitor, a recording scanner for exposing and recording a layout-processed image on a film, and the like.

The interface circuit 3 has only the function of outputting data to the bus line 1 in relation to the function of the external data processing device 2 connected thereto,
Some have only the function of inputting data, and some have both functions. The external data processing device 2 and the interface circuit 3 are connected by an external connection line 6 including 32 data lines and 2 handshake lines.

The bus controller 4 outputs bus control data necessary for time-division transfer of data between the interface circuits 3 connected to the bus line 1. Although details of the bus control data will be described later, here, a "bus cycle" and a "bus slot" set by the bus controller 4 for time division transfer of data.
The concept of will be described with reference to FIGS. 2 and 3.

FIG. 2 shows an example of the external data processing device 2 connected to the bus line 1. In FIG. 2, the interface circuit 3 and the bus controller 4 are omitted.
FIG. 3 shows the relationship between bus slots and bus cycles. The bus controller 4 time-divides the transfer time axis of the 32-bit data bus in the bus line 1 in a minimum time unit (bus slot) of data transfer that is predetermined according to the access time of the external data processing device 2. It has a function. One bus slot allows one data transfer between predetermined external data processing devices 2.

The same number of bus slots as the number of data transfer requests for the data bus are generated. For example, in FIG.
As shown in, a request for data transfer A from the disk 2 ₁ as the external data processing device 2 to the image processing device 2 ₂ ,
Assuming that a request for data transfer B from the image processing device 2 ₂ to the color monitor 2 ₃ and a request for data transfer C from the scanner 2 ₅ to the disk 2 ₄ exist at the same time, the bus controller 4 operates as shown in FIG. As shown in (a), three bus slots # 1, # 2, and # 3 are set. For example, transfer A is bus slot # 1, transfer B is bus slot # 2, and transfer C is bus slot. # 3. These bus slots # 1 to # 3 are repeatedly generated until the data transfer is completed. The repetition time of such a group of bus slots is called a bus cycle.

Therefore, the bus cycle is increased or decreased according to the number of data transfer requests. In the example above, transfer B
Is completed first, the bus cycle is composed of slots # 1 and # 3, as shown in FIG. Further, if another data transfer request is made, a bus cycle may be composed of four or more bus slots as shown in FIG. The bus slot time is not necessarily constant, and is set according to the access time of the external data processing device 2 involved in data transfer as described above. For example, in FIG. 2, the disc 2 ₄ access time 2
When the access time of another external data processing device is 50 nsec and 200 nsec, the bus slot time t of the bus slots # 1 and # 2 used for the transfer A and B is 200 nsec as shown in (d) of FIG. Although set to, bus slot time T of the bus slots # 3 which will be used to forward C according to a slow disk 2 ₄ accessed time 250nsec
Is set to. As described later in detail, the bus controller 4 performs such bus slot generation and bus slot time control processing.

The bus controller 4 informs each interface circuit 3 of the timing of time division transfer by outputting a signal (slot enable signal) corresponding to the generated bus slot to the control bus in the bus line 1.

Returning to FIG. 1, the system control unit 5 controls the entire time-division transfer device for data, and each interface circuit 3 via the bidirectional command line 7.
And the bus controller 4. The system controller 5 monitors the number of the bus slot generated by the bus controller 4 (hereinafter referred to as “slot number”). Then, by receiving a data transfer request from the external data processing device 2 via the interface circuit 3, the bus controller 4 is designated with an appropriate slot number from among the bus slots that are not currently used, A request is made to generate a slot, and the slot number is sent to each interface circuit 3 of the external data processing device 2 for data transfer. Further, the system control unit 5 grasps the access time of each external data processing device 2 connected to the bus line 1 in advance, and when there is a data transfer request from a certain external data processing device 2, the above-mentioned In addition to designating the slot number, the bus slot time corresponding to the access time of the external data processing device 2 is designated to the bus controller 4. The interface circuit 3 sequentially compares the slot number sent from the system control unit 5 and each slot enable signal sequentially transferred by the bus controller 4 via the control bus, and based on the fact that both match, Know the timing of data transfer.

Next, a connection structure between the bus line 1 and the interface circuit 3 and a connection structure between the interface circuit 3 and the external data processing device 2 will be described with reference to FIG. The bus line 1 and the interface circuit 3 are
A data bus DB including 32 signal lines and a control bus including 5 signal lines are connected. The structure of the control bus is as follows. Basic clock line: A single signal line for transmitting the basic clock CL of the bus. This basic clock C
L is sent from the bus controller 4. The cycle of the basic clock CL is controlled according to the set bus slot time. Bus clock line: A single signal line for transmitting a bus clock BCL having a cycle twice that of the basic clock. This bus clock BCL is sent from the bus controller 4. Slot enable line: A slot enable signal SE for transmitting the slot enable signal SE generated by the bus controller 4, and is composed of two signal lines in this embodiment. Since the slot enable signal SE is composed of 2 bits, the bus controller 4 can generate four types of bus slots # 0 to # 3. It should be noted that it is possible to generate more bus slots by increasing the number of bits forming the slot enable signal SE. Data valid line: One signal line for handshaking between the interface circuits 3 for transferring data. This data valid line is pulled up to a logic [1] (usually 5 V) via a pull-up resistor (not shown) at one point on the line, so that the line itself is wired-and (Wired-AND).
Is formed. Hereinafter, the signal on the data valid line is referred to as a data valid (DV) signal.

As described above, the interface circuit 3a dedicated to data reception and the external data processing device 2a shown in FIG. 4 have 32 data lines for data transfer and 2 handshake lines for handshake. Connected with and. As a signal for handshake, a data output preparation completion signal OR sent from the interface circuit 3a to the external data processing device 2a when the data transfer becomes possible, and an interface when the external data processing device 2a receives data There is a data reception signal DG sent to the circuit 3a. Between the interface circuit 3b dedicated to data transmission and the external data processing device 2b,
Similarly, 32 data lines for data transfer and 2 handshake lines are connected. As a signal for handshake, a data input preparation completion signal IR sent from the interface circuit 3b to the external data processing device 2b when the data can be received.
And a data transfer signal D sent to the interface circuit 3b when the external data processing device 2b transfers data.
There is T.

Next, referring to FIG. 5, the bus controller 4
The configuration of the slot enable signal output section provided in the above will be described. The bus controller 4 includes a CPU 41 for generating a slot number and the like based on a slot generation request from the system control unit 5, latch circuits L3a, L2a, L1a, L0a for latching the slot number, and these latch circuits L3a. To latch circuits L3b, L2b, L1b and L0b respectively corresponding to L0a, and a latch circuit LN1 for latching the number of slots currently occurring.
And LN2, a selection circuit 42 for selecting an output of any of the latch circuits L3b to L0b, and a selection circuit 42.
A counter 43 that gives a selection signal to
An oscillator OSC, a timing signal generation circuit 45, a bus clock generation circuit 46, a reference pulse generation circuit 47,
NAND gate 48 and SR flip-flop 49
, Monostable multivibrator 50, and latch circuit 51
It has and.

Oscillator OSC, timing signal generation circuit 4
5, the bus clock generation circuit 46, and the reference pulse generation circuit 47 generate the basic clock CL as shown in FIG. 6, the bus clock BCL having a cycle twice the basic clock CL, and the reference pulses P1 to P4. Occur. Of these, the basic clock CL and the bus clock BCL are also sent to each interface circuit 3 via the bus line 1 as described above. The cycle of the basic clock CL is controlled according to the set bus slot time. In the present embodiment, 1/2 of the bus slot time T is set to the cycle T _CL of the basic clock CL.

The timing signal generation circuit 45 stores the bus slot time information BT designated by the system control unit 5,
The basic clock CL corresponding to the designated bus slot time is generated by dividing the output of the oscillator OSC on the basis of the slot enable signal SE output to the slot enable line.
Here, for four types of bus slots # 0 to # 3,
A bus slot time of either 200 nsec or 250 nsec is set. Hereinafter, a configuration example of the timing signal generation circuit 45 will be described with reference to FIG. 7.

As shown in FIG. 7, the timing signal generating circuit 45 includes four pairs of AND gates for determining the bus slot times of the bus slots # 0 to # 3. A
The ND gates G00 and G01 determine the bus slot time of the bus slot # 0. AND gates G10 and G11
Determines the bus slot time of bus slot # 1.
AND gates G20 and G21 determine the bus slot time of bus slot # 2. AND gates G30 and G3
1 determines the bus slot time of bus slot # 3. The outputs of the AND gates G00, G10, G20, G30 are given to the NOR gate G200. On the other hand, AND
Each output of the gates G01, G11, G21 and G31 is NO
It is applied to the R gate G250. The timing signal generation circuit 45 includes a counter 451 that counts the output pulse of the oscillator OSC, and the count value of this counter 451 is AN.
It is applied to D gates G201 and G251. Also,
The output of the NOR gate G200 is given to the AND gate G201, and the NOR gate G251 is given to the AND gate G251.
250 outputs are provided. The outputs of the AND gates G201 and G251 are passed through the NOR gate G300,
It is applied to the clock terminal of the flip-flop 452 and the reset terminal R of the counter 451. The Q output of the flip-flop 452 is output as the basic clock CL.

The operation of the timing signal generating circuit 45 having the above-mentioned structure will be described below. The slot enable signal SE fetched from the slot enable line is composed of 2-bit data,

[00] is bus slot # 0
In addition, [01] corresponds to bus slot # 1, [10] corresponds to bus slot # 2, and [11] corresponds to bus slot # 3. The bus slot time information BT given from the system control unit 5 is the bus slot time information BT0, BT1, corresponding to each of the bus slots # 0 to # 3.
It consists of BT2 and BT3,

[0] is 200 nsec,
[1] corresponds to 250 nsec.

Now, the slot enable signal SE of the bus slot # 0 is set on the slot enable line.

It is assumed that [00] is output and the bus slot time of 200 nsec is designated by the system controller 5 at this time. As a result, of the four pairs of AND gates for bus slot time determination, A
Only the output of the ND gate G00 becomes "H" level, and the outputs of the other AND gates become "L" level. Therefore, the output of the NOR gate G200 becomes "L" level, and the output of the NOR gate G250 becomes "H" level.

On the other hand, the counter 451 counts the output pulse of the oscillator OSC. In this embodiment, since the 80 MHz oscillator is used, the count value of the counter 451 changes its state every 12.5 nsec. When the count value of the counter 451 changes from 0 → 1 → 2 → 3,
That is, the output of the counter 451 [C2, C1, C0]
Becomes [011], the output of the AND gate G201 becomes "H" level. As a result, the NOR gate G
The output of 300 becomes "L" level, and this output is given to the reset terminal R of the counter 451. As a result, the counter 451 is reset at the next clock pulse,
The output is

Return to [000]. Hereinafter, similarly, the counter 4
Whenever the count value of 51 changes from 0 → 1 → 2 → 3, NO
The R gate G300 outputs the "L" level. That is,
The output of the NOR gate G300 becomes "L" level every 50 nsec. The output of the NOR gate G300 is
It is also used as a clock for the flip-flop 452. The inverted signal Q is applied to the D terminal of the flip-flop 452.
Since the bar is input, flip-flop 452
Changes every time the NOR gate G300 outputs the "L" level, that is, every 50 nsec. Therefore, the basic clock pulse CL with a cycle of 100 nsec is output from the Q terminal of the flip-flop 452. As described above, since the bus slot time is equal to the double cycle of the basic clock pulse CL, the bus slot time of 200 nsec is set. FIG. 8 shows a timing signal generation circuit 4 for setting the above-mentioned bus slot time of 200 nsec.
5 shows the operation timing of No. 5.

Next, the slot enable signal SE becomes [0
0] (that is, bus slot # 0), the case where the bus slot time of 250 nsec is designated by the system controller 5 will be described. Bus slot time information BT at this time
0 is [1]. As a result, of the four pairs of AND gates for determining the bus slot time, only the output of the AND gate G01 becomes the “H” level, so the NOR gate G20
0 outputs the “H” level, and the NOR gate G250 outputs the “L” level.

On the other hand, the count value of the counter 451 is 0 → 1 →
When it changes from 2 → 3 → 4, that is, the counter 451
When the output [C2, C1, C0] of the above becomes [100], the output of the AND gate G251 becomes "H" level. As a result, the NOR gate G300 outputs the "L" level, and the counter 451 is reset at the next clock pulse. Similarly, every time the count value of the counter 451 changes in the order of 0 → 1 → 2 → 3 → 4, the NOR gate G300 outputs the “L” level. Since the NOR gate G300 outputs the "L" level every 62.5 nsec, the basic clock pulse C having a cycle of 125 nsec is output from the Q terminal of the flip-flop 452.
L is output. Therefore, the bus slot time is set to 250 nsec which is a double cycle of the basic clock pulse CL. FIG. 9 shows the operation timing of the timing signal generation circuit 45 when the bus slot time of 250 nsec described above is set.

Next, the operation when the bus controller 4 generates an arbitrary number of bus slots will be described. Reference is made to the timing chart of FIG. For example,
A request from the system control unit 5 to set two bus slots # 0 and # 1 and a request to set the bus slot time to 200 nsec for the bus slot # 0 and 250 nsec to the bus slot # 1. It is assumed that the data is sent to the bus controller 4.

Based on the bus slot setting request from the system controller 5, the CPU 41 of the bus controller 4 issues a data output pulse to the slot set output port <2>, and at the same time, corresponds to the bus slot # 0 on the CPU bus. 2-bit data

[00] is output. That data is latched in the latch circuit L2a at the rising edge of the output to the output port <2> data output pulses (timing T ₁ of the FIG. 10).

Subsequently, the CPU 41 issues a data output pulse to the slot set output port <3> and
Data corresponding to bus slot # 1 on the CPU bus [0
1] is output. This data, the a is latched by the latch circuit L3a in the same output data output pulse rise timing (not shown) (timing T ₂ of the FIG. 10) to the output port <2>.

When the data corresponding to the bus slots # 0 and # 1 is latched, the CPU 41 issues a data output pulse to the slot number set output port <N> and, at the same time, determines the number of bus slots currently occurring. The 2's complement value in the 2-bit configuration is output to the CPU bus. For example, the number of bus slots in one bus cycle is "1".
If so, "3", if "2", "2", if "3", "1", and if "4", "0" is output. Here, since the number of set bus slots is "2", "2" (that is, 2-bit data [10]) on the CPU bus.
Is output. This data is latched by the latch circuit LN1 at the output port <N> output data output pulse of the rise timing (the timing T ₃ in FIG. 10). This data is latched in the latch circuit LN2 at the next rising edge of the reference pulse P3.

All latch circuits L _Xa (subscript X is "3"-
When the data setting to "0" is completed, the CPU 4
1 issues a control pulse to the output port <L-end> in order to transfer these data to the corresponding latch circuit L _Xb .
The control pulse becomes a reset signal to the RS flip-flop 49 (corresponding to the timing T ₄ in FIG. 10) to set its Q terminal output signal LE to the "L" level.
The “L” level output signal LE of the RS flip-flop 49 is given to the D input terminal of the latch circuit 51. As a result, at the rising timing of the reference pulse P2 input to the clock terminal CK of the latch circuit 51, the latch circuit 5
When the Q-bar terminal output signal LE 'of 1 becomes "H" level, the gate of the NAND gate 48 is released, and the carry terminal signal C of the counter 43 is changed to the output side signal Load-b.
And let it pass.

The counter 43 receives the input clock CK.
Every time (reference pulse P1) rises, output data (2 bits) is counted up. On the other hand, when the load clock terminal LDE is at "H" level, the clock CK
The data input to the load data terminal LDD is preset at the rising edge of. The carry terminal C outputs an "H" level when the count value of the counter 43 becomes "3". At the same time that "2" is preset in the counter 43, the carry terminal C becomes "L" level.

In the initial state of the timing chart of FIG. 10, it is assumed that the value "1" is set in the latch circuit LN2. At this time, the counter 43 sets the carry terminal C to the “H” level at timing T ₅ ,
The carry terminal signal C is passed through the D gate 48 as the output side signal Load-b. And the output signal Load
At the rising edge T ₆ of -b, with transfer the contents of the latch circuits L _Xa in the latch circuit L _Xb, to trigger the monostable multivibrator 50. The monostable multivibrator 50 generates a pulse having a constant time width (for example, 200 nsec) by this trigger signal. The RS flip-flop 49 is set by this pulse (SET signal), and as a result, the Q-bar terminal output signal LE ′ of the latch circuit 51 becomes “L” level and the NAND gate 48.
Is generated, the counter 4 is generated later
Output data of the latch circuit L _Xa is prevented from being latched into the latch circuit L _Xb by 3 carry signal.

As a result, the input terminal <2 of the selection circuit 42
> To 2-bit data

2-bit data [01] is input to the input terminal <3>. On the other hand, at the same timing T ₆ , the counter 43 has the latch circuit LN
Data 2 (here, “2”) is fetched from the LDD input terminal and used as preset data.

The count value of the counter 43 at this time is "2".
And the output data is the selection terminal SE of the selection circuit 42.
By being applied to L, the input terminal of the selection circuit 42 <
2-bit data input to 2>

[00] is selected and output to the slot enable line in the bus line 1 via the buffer 44. This 2-bit data is the slot enable signal SE # 0 corresponding to the bus slot # 0. When the slot enable line slot enable signal SE # 0 is output to actuate the timing signal generation circuit 45 described above, bus slot time (time from the timing T ₆ in FIG. 10 to T ₇₎ 20
The setting to 0 nsec is as described above. In addition,
In the present embodiment, in the initial state, for example, the slot enable signal SE # 0 is provided on the slot enable line.
(Ie data

[00]), so as to output a timing T ₆ earlier reference pulse P1 in FIG. 10
The cycle is also 200nsec.

The counter 43 is incremented by the next reference pulse P1 (timing T _{7 in} FIG. 10), and the count value becomes "3". By supplying this output data to the selection terminal SEL of the selection circuit 42, the 2-bit data [01] input to the input terminal <3> of the selection circuit 42 is selected and output to the slot enable line. This output data is the slot enable signal SE # 1 corresponding to the slot # 1. Slot enable signal SE # on the slot enable line
When 1 is output, the timing signal generating circuit 45 operates and sets the bus slot time (time from timing T ₇ to T _{8 in} FIG. 10) at that time to 250 nsec.

At the same time when the count value of the counter 43 becomes "3", the "H" level is output from the carry terminal C again. Then, at the next rising timing of the reference pulse P ₁ (timing T _{8 in} FIG. 10), the latch circuit LN2
The data "2" is reset to the counter 43 again. As a result, the output data of the counter 43 becomes "2", the slot enable signal SE # 0 corresponding to the slot # 0 is output from the selection circuit 42, and the bus slot time is 20 by the timing signal generation circuit 45.
It is set to 0 nsec.

When the counter 43 is further incremented by the next reference pulse P1 (timing T _{9 in} FIG. 10) and the output data becomes "3", the selection circuit 42 outputs the slot enable signal SE # 1. , The bus slot time is set to 250 nsec.

Thereafter, similarly, the bus slot time is set to 200 in synchronization with the rising timing of the reference pulse P1.
nsec bus slot # 0 and bus slot time is 25
The bus cycle composed of 0 nsec and bus slot # 1 is repeated.

In the device according to the present embodiment, the number of bus slots forming one bus cycle can be arbitrarily increased or decreased within the range of up to 4. Since the increase / decrease of the bus slot is not directly related to the control of the bus slot time which is the gist of the present invention, only a brief description will be given here. For example, when the currently used slots are # 0 and # 1, when the system control unit 5 receives a new data transfer request from the external data processing device 2, an appropriate slot is selected from the currently unused empty slots. (For example, slot #
2) is designated, bus slot time information corresponding to the slot generation request and the access time of the external data processing device 2 which has issued the data transfer request is provided to the bus controller 4
To a new bus slot is set. Further, when the data transfer is completed between certain external data processing devices 2, the system control unit 5 receives a notification of the data transfer completion from those external data processing devices 2.
Based on this notification, the bus controller 4 is instructed to erase the slot used for the data transfer to erase the slot.

The operation of the bus controller 4 has been described above. Next, the specific configurations of the interface circuit 3a dedicated to data reception and the interface circuit 3b dedicated to data transmission shown in FIG. 4 will be described. Note that the interface circuit 3 capable of transmitting and receiving data has a configuration that also includes the configurations of interface circuits 3a and 3b to be described later, and a description thereof will be omitted. First,
Referring to FIG. 11, an interface circuit 3b dedicated to transmission
The configuration of will be described.

The interface circuit 3b receives a slot setting command from the system control section 5 via the command line 7 and sets a slot number (SL0T #), a control command processing section 31, and the slot number and the bus controller 4 in this order. Slot enable signal S sent
A comparator 32 that compares E # with a first handshake processing unit 33 that validates the output of the comparator 32 based on a handshake between the destination via the data valid line of the bus line 1; A second handshake processing unit 34 for performing a handshake with the external data processing device 2b, a latch circuit 35 for latching the data sent from the external data processing device 2b, and the like. Although not shown, the interface circuit 3
b also includes an internal circuit that generates reference pulses P1 to P4 as shown in FIG. 6 based on the reference clock CK and the bus clock BCL sent from the bus controller 4.

The operation of the interface circuit 3b will be described below with reference to the timing chart of FIG. The shaded area in the figure means that the data or level may be in any state. Here, it is assumed that data is transferred using slot # 1. The control command processing unit 31 receives the setting command of the slot # 1 from the system control unit 5, and thereby the data (here, 2-bit data [0
1]) and provides it as an input to one of the comparators 32. The comparator 32 compares the slot number set by the control command processing unit 31 with the slot enable signal SE # sequentially sent from the bus controller 4, and the slot enable signal SE # 1 corresponding to the bus slot # 1. Is sent, the match signal EQ
The data is output to the handshake processing unit 33 (timing T _{1 in} FIG. 12).

At this time, if the destination interface circuit 3 is in a state of accepting data and the DV _OUT signal of "H" level is on the data valid line, this DV _OUT signal is passed through the buffer B1. AND
It is provided as an input to one of the gates G1. As a result, the coincidence signal EQ of the comparator 32 passes through the AND gate G1 and is input to the D terminal of the flip-flop FF1. This coincidence signal EQ is latched at the rising timing (timing T _{2 in} FIG. 12) of the reference pulse P4 given to the T terminal of the flip-flop FF1.

Output signal SL of flip-flop FF1
TE is provided as an input to each one of NAND gate G2 and AND gate G3. Now, it is assumed that the data transferred to the latch circuit 35 is latched. Then, the output of the AND gate G3 becomes "H" level during the period when the reference pulse P4 is not output (that is, the period from the reference pulse P1 to P3), the buffer B3 is opened, and the output of the latch circuit 35 is output. Data is output on the data bus. Here, the reference pulse P4
The reason why the data is transferred while avoiding the period is to prevent the data transferred in the adjacent bus slots from buffering each other on the data bus.

On the other hand, the NAND gate G2 is a flip-flop.
When the next reference pulse P3 is applied as the other input (timing T _{3 in} FIG. 12) while the output signal SLTE of the flop FF1 is applied, the output of the NAND gate G2 falls and the second handshake processing unit The reset terminal RS bar of the flip-flop FF2 of 34 is activated. As a result, the Q-bar output of the flip-flop FF2 becomes "H" level, and this output is given to the external data processing device 2b as the data input preparation completion signal IR. At this time, the output signal DV _IN of the Q terminal of the flip-flop FF2 becomes "L" level. The output signal DV _IN is output from the data valid line via the buffer B2 of the first handshake processing unit 33 and informs the transfer destination interface circuit 3 that no data is output.

CP (not shown) of the external data processing device 2b
When U confirms that the data input preparation completion signal IR has become "H" level, the interface circuit 3b
And outputs the data transfer signal DT to the flip-flop FF3 (timing T _{4 in} FIG. 12). This makes the second
Flip-flop FF3 of the handshake processing unit 34
Is the rising timing of the next reference pulse P1 (see FIG.
In second timing T _5), latches the data transfer signal DT, and outputs the "H" level. This output signal IDG
Is supplied to the latch circuit 35, the next transfer data output from the latch circuit 21 in the external data processing device 2b is latched in the latch circuit 35. In this example, the pulse width of the data transfer signal DT is longer than the cycle of the reference pulse P1, and the latch circuit 35 is used.
It is assumed that the data input to is also stable enough.

When the IDG signal goes to the "H" level, the output of the flip-flop FF2 is inverted, the DV _IN signal for handshake goes to the "H" level, and the state in which data can be transmitted is transferred to the transfer destination. Inform.

Thereafter, in the same manner as described above, when the slot enable signal SE # 1 is transferred from the bus controller 4 and the DV _OUT signal for handshake becomes the "H" level, the data of the latch circuit 35 is changed. Is transferred.

Next, the structure of the interface circuit 3a dedicated to reception shown in FIG. 4 will be described with reference to FIG. The interface circuit 3a dedicated to reception also has the same control command processing unit 31, comparator 32, and first handshake processing unit 33 as the interface circuit 3b dedicated to transmission described above.
And a second handshake processing unit 36 unique to the interface circuit 3a.

The operation of the interface circuit 3a will be described below with reference to the timing chart of FIG. Here, a case where data transfer is performed using slot # 1 will be described.

As in the case of the interface circuit 3b described above, D of the data valid line in the bus line 1
When the slot enable signal SE # 1 is sent from the bus controller 4 while the V _OUT signal is at “H” level, the comparator 32 outputs the coincidence signal EQ, whereby the first handshake process is performed. The SLTE signal of "H" level is output from the section 33 (timing T _{1 in} FIG. 14). This SLTE signal is input to the D terminal of the flip-flop FF4 of the second handshake processing unit 36.

The output signal (BDG signal) from the Q terminal of the flip-flop FF4 is the reference pulse P input to the T terminal.
At the rising timing of 3 (timing T _{2 in} FIG. 14), the level becomes “H”. The BDG signal causes the transfer data on the bus line 1 to be latched in the latch circuit 35.

When the BDG signal becomes "H" level, the output of the Q terminal of the flip-flop FF5 becomes "H".
The output of the Q bar terminal is inverted to the “L” level. The Q output is sent to a CPU (not shown) of the external data processing device 2a as a data output preparation completion signal OR. Further, the Q-bar output (DV _IN signal) is output to the data valid line via the buffer B2 of the first handshake processing unit 33, and the data is not accepted by setting this data valid line to the “L” level. Notify the destination that the status is.

The CPU of the external data processing device 2a, which has received the data output preparation completion signal OR, returns the data reception signal DG to the second handshake processing unit 36 (timing T _{3 in} FIG. 14) and performs external data processing. The output data of the latch circuit 35 is latched in the latch circuit 21 in the device 2. Here, it is assumed that the pulse width of the DG signal is longer than the cycle of the reference pulse P1.

[0060] Flip-flop FF6 in the second handshake processor 36 for receiving the DG signal at the rising edge of the next reference pulse P1 (timing T ₄ in FIG. 14), at its Q output is "H" level Inversion, and this Q output is given as one input of the NAND gate G4. Then, the output of the NAND gate G4 becomes active at the timing of the next rising of the reference pulse P1 (timing T _{5 in} FIG. 14), whereby the flip-flop FF5 is reset and the Q and Q bar outputs are inverted, The data output preparation completion signal OR falls and the DV _IN signal rises. When the data output preparation completion signal OR becomes the “L” level, the external data processing device 2a is notified that the preparation for data output is not completed. Further, when the DV _IN signal rises, the transfer destination is notified that the preparation for accepting the data is completed.

In the same manner as described above, when the slot enable signal SE # 1 is sent while the DV _OUT signal of the data valid line of the bus line 1 is at "H" level, the comparator 32 outputs the coincidence signal EQ. By outputting
The SLTE signal is output from the first handshake processing unit 33, and the data on the data bus is latched by the latch circuit 35. Then, the data in the latch circuit 35 is transferred to the external data processing device 2a by performing a handshake with the external data processing device 2a.

In the above embodiment, 200 nsec.
Although two types of bus slot times of 250 nsec and 250 nsec can be set, the present invention is not limited to this, and the type of bus slot time set and each time are arbitrary. For example, FIG. 15 shows four types of bus slots # 0 to #.
3 types, 4 types of bus slot time 100 nsec,
The configuration example of the timing signal generation circuit 45 used when setting 150 nsec, 200 nsec, and 250 nsec is shown. The other configuration of the time division transfer device is the same as that of the above-mentioned embodiment.

In this example, in order to set four types of bus slot times, the bus slot time information BT is composed of 2-bit data for each of the bus slots # 0 to # 3. Here, the bus slot time information BT _X0 , BT _X1 (the subscript X is any of “0” to “3” corresponding to the bus slots # 0 to # 3),

[00]
Is 100 nsec when, and [01] is 150 nsec
, [10] is set to 200 nsec, and [11] is set to 250 nsec.

The timing signal generating circuit 45 includes four AND gate groups G corresponding to the bus slots # 0 to # 3.
00-G03, G10-G13, G20-G23, G3
0 to G33, and each AND gate group is composed of four AND gates corresponding to four types of bus slot times. Also, four NOR gates G100, G150, G200, G25 are provided corresponding to four types of bus slot times.
0 and four AND gates G101, G151, G20
1, G251.

For example, on the slot enable line,
When the slot enable signal [01] corresponding to the bus slot # 1 appears, AND gate groups G10 to G13
Is selected. At this time, if the bus slot time information BT ₁₀ and BT ₁₁ corresponding to the bus slot # 1 is [01], AND of the AND gate groups G10 to G13 is performed.
The gate G11 is selected and outputs "H" level. As a result, the NOR gate G150 outputs the "L" level, and the AND gate G151 is selected. The AND gate G151 outputs "H" level every time the counter 451 outputs [010], and accordingly, the NOR gate 3
00 outputs the “L” level. As a result, counter 4
51 is cleared and the flip-flop 45
The Q output of 2 is inverted. Counter 451 is 37.5nse
Since [010] is output for each c, the flip-flop 452 outputs the basic clock CL of 75 nsec.
That is, the bus slot time is set to 150 nsec which is a double cycle of the basic clock.

The types of bus slots are not limited to four types. For example, if the slot enable signal has a 4-bit structure, 16 types of bus slots can be generated. Along with this, 16 AND gate groups for bus slot determination of the timing signal generating circuit 45 shown in FIG. 15 are added, and bus slot time information (in 4 types) corresponding to each bus slot is added to each AND gate group. If there is 2-bit data). It goes without saying that 16 signal lines are connected to each of the NOR gates G100 to G250 as the AND gate group is added.

A bus controller 4 as a bus control means and an interface circuit 3 as a module
The configurations of a and 3b are not limited to those of the above-described embodiment, and can be appropriately modified and implemented. in short,
The bus controller 4 generates a bus slot necessary and sufficient for data transfer between the external data processing devices 2 based on a command from the system control unit 5, and the external data processing device 2 for each bus slot. It is only necessary to be able to set the bus slot time according to the access time. Further, the interface circuit 3 compares a series of slot enable signals sent from the bus controller 4 with a slot number given in advance by the system control unit 5, and based on the fact that the two coincide with each other, the interface bus 3 stores the data in the data bus. Any data transmission / reception can be used.

[0068]

As is apparent from the above description, according to the time-division transfer device for data according to the present invention, the bus slot time, that is, the time corresponding to the access time of the module which has requested the data transfer, Since the time to send the slot enable signal specific to the bus slot used for data transfer is controlled, the bus slot time is set to be uniformly long according to the module with the slow access time as in the conventional device. Compared with, the data transfer efficiency of the entire system can be improved. Further, according to the present invention, even if there is a module with a slow access time among a plurality of modules, the data transfer efficiency of the entire system is not significantly deteriorated, so that the existing module with a slow access time is used. Therefore, it is possible to shorten the development period of the system and reduce the development cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a time division transfer device for data according to the present invention.

FIG. 2 is an explanatory diagram of an example of transfer between external data processing devices.

FIG. 3 is an explanatory diagram of a bus cycle including a plurality of bus slots.

FIG. 4 is an explanatory diagram of a connection structure of an interface circuit.

FIG. 5 is a block diagram showing a specific configuration of a bus controller.

FIG. 6 is a waveform diagram of pulses used for controlling time division transmission.

FIG. 7 is a block diagram showing a specific configuration of a timing signal generation circuit.

FIG. 8 is a timing chart for explaining the operation of the timing signal generation circuit.

FIG. 9 is a timing chart for explaining the operation of the timing signal generation circuit.

FIG. 10 is a timing diagram relating to the operation of the bus controller when generating a plurality of bus slots.

FIG. 11 is a block diagram showing a specific configuration of an interface circuit dedicated to data transmission.

FIG. 12 is a timing chart for explaining the operation of the interface circuit dedicated to data transmission.

FIG. 13 is a block diagram showing a specific configuration of an interface circuit dedicated to data reception.

FIG. 14 is a timing chart for explaining the operation of the interface circuit dedicated to data reception.

FIG. 15 is a block diagram showing a configuration of another embodiment of the timing signal generation circuit.

[Explanation of symbols]

1 ... Bus line 2 (2 ₁ , ..., 2 _i , ..., 2 _n ) ... External data processing device 3 (3 ₁ , ..., 3 _i , ..., 3 _n ) ... Interface circuit 3 a ... Data reception dedicated interface circuit 3 b ... Data transmission dedicated interface circuit (2, 3 ... module) 4 ... Bus controller (bus control means) 5 ... System control unit (system control means) 45 ... Timing signal generation circuit

Claims (1)

[Claims] 1. An apparatus for time-division transfer of data by setting a bus slot, which is the minimum time unit of data transfer, and repeating a bus cycle composed of a plurality of bus slots according to the number of data transfer requests. A plurality of modules that are connected to a common data bus and exchange data through the data bus; a bus control unit that controls time-division transfer of the data exchange; and the modules and the bus control unit. The system control means is provided with a bus slot setting command necessary for the data transfer to the bus control means by receiving a data transfer request from each module. , Issuing a bus slot time setting command according to the access time of the module related to data transfer, and The module for data transfer is informed of the slot number used for data transfer, and the bus control means, based on the bus slot setting command from the system control means, a slot enable signal unique to each bus slot used for data transfer. Repeatedly, and controls the time for sending each slot enable signal based on the bus slot time setting command from the system control means, and each module controls the series of slots sent from the bus control means. A time-division transfer of data, characterized in that the enable signal is sequentially compared with a slot number given in advance by the system control means, and data is transferred to and from the data bus based on the coincidence between the two. apparatus.