JPH05298093A - Processor - Google Patents

Abstract

PURPOSE:To improve the practical use efficiency of hardware and to realize a high performance computer by realizing the processor which simultaneously processes plural instructions in the constitution of fractionizing the computer function to increase the pipeline pitch. CONSTITUTION:The processor consists of an adder 10, an MDR(memory data register) 120, an ACC(accumulator) 110, a PC (program counter) 140, an IR (instruction register) 150, a one adder 141, and channels 161, 162, 171, 172, 300 to 302, and 304 to 307. The address register of an instruction memory 170 is the PC 140 in stage 0 and the data register is the IR 150 in stage 2. The address register of a data memory 160 is the IR 150 in stage 2 and the data register is the MDR 120 in stages 3 and 4. Correlations of simultaneously processed instruction trains are eliminated to prevent the degradation of the processing efficiency due to a branch instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer construction method, and more particularly to a multiprocessor construction method for operating a large number of processing devices in parallel.

[0002]

2. Description of the Related Art In order to improve computer performance, there are a method of improving device performance, especially a circuit speed, and a method of improving computer structure. In order to improve the computer structure, it is extremely effective to divide the functions of the computer and use the so-called pipeline method, which uses the functions in an instruction sequence in a time division manner. For this pipeline system, for example, "Gear Architecture of Pipelined Computers" Hemisphere Publishing
Corporation 1981 ("The Archi
texture of pipelined comp
uters ”Hemisphere Publish
ing Corporation 1981). In the conventional pipeline method, for example, the execution order of each instruction is read by an instruction read (Instruction).
Fetch), instruction decoding (Decord), operand read (Operand Fetch), instruction execution (Execution), and write (Write) are divided into five consecutive operations, and these consecutive operations are sequentially overlapped. While doing.

[0003]

However, the above-mentioned prior art is a method for effectively utilizing the prepared hardware in a time division manner, but it does not necessarily utilize the prepared hardware with high efficiency. It can not be said. In the ultimate pipeline, time-division operations can be performed in units of the gates that make up the computer, and instructions for the number of logical stages of the computer can be executed at one time. In any case, in order to improve the performance of the computer, it is effective to subdivide the structure of the computer and increase the pitch of the pipeline. However, in the conventional pipeline method, the computer function is divided into at most about five, and the multiple operations of that degree are realized. This is a so-called S that executes one instruction sequence one after another.
ingle Instruction Stream
Single Data Stream (SISD)
This is because, in the processing form of the method, the change of the sequential processing order by the branch instruction disturbs the order of the pipeline processing, invalidates the processing performed earlier, and lowers the overall processing efficiency.

An object of the present invention is to provide a computer configuration method in which the computer function is further subdivided and the pipeline pitch is increased in order to improve the utilization efficiency of computer hardware and realize a high-performance computer. It is a thing.

[0005]

SUMMARY OF THE INVENTION The above-mentioned object is to allocate a register set to each subdivided computer function so that the data of the register set is decremented as the instruction execution sequence progresses.
This is achieved by adopting a method of sequentially moving the data.

[0006]

When the system according to the present invention is adopted, the instructions of a different program (instruction string) can be executed for each stage of each pipeline, so that the same effect as operating a plurality of processors by one hardware can be obtained. There is. In this form, it is possible to eliminate the correlation between the instruction sequences being processed by a single hardware at the same time, and the branch instruction, which is a problem of the conventional pipeline system, does not suffer from the reduction in processing efficiency. Therefore, according to the present invention, it is possible to configure a multiprocessor that executes a plurality of programs with high efficiency with a single hardware.

[0007]

EXAMPLES The present invention will be described below with reference to examples.
The present invention takes a simple calculator as an example. The computer is an instruction memory (Instruction Mem).
ory: IM) to read the instruction from the data memory (D
The operand is read from the data memory (DM) and the operation is executed. This computer has an adder and the following four registers. ACC: Accumulator (holding operation registers and operation data) MDR: Memory data register (holding operands read from data memory and holding data to be written in data memory) PC: Program counter (Holding program execution address) IR: Instruction register (holding instruction code) The instruction format of this computer is shown in FIG.
The instruction format comprises an instruction code (OP Code) and an instruction address (Address). This instruction is read from the instruction memory, set in IR, decoded, and then executed. The computer has the following seven types of instructions. JMP: Unconditional jump to instruction address CAL: Subroutine jump to instruction address RTN: Return from subroutine jump JAN: Jump to instruction address if accumulator is negative (conditional jump) LAC: Instruction address data To the accumulator SAC: Write the data of the accumulator to the instruction address ADD: Add the data of the instruction address to the accumulator The computer of the present embodiment has a simple structure and the conventional pipe. Instruction reading of line technology (Instruction F
Only the operations corresponding to "etch" and instruction execution (Execution) are performed. However, in more detail, instruction reading and instruction execution are subdivided into more complicated operations. FIG. 3 shows subdivided operations for executing the above seven instructions. In FIG. 3, instruction reading is divided into three operation stages and instruction execution is divided into three operation stages, and each instruction is completed through six operation stages. For example, in the instruction reading, the data of the PC is transferred to the instruction memory as an address in stage 0, and the instruction memory is set as a read cycle.
In stage 1, PC is incremented by 1 and the execution address of the next instruction is held. In step 2, the instruction code to be executed from the instruction memory started in step 0 is returned to IR. In this stage, the instruction part (OP
When Code) is set to IR, a specific location (for example, address 0) holding the instruction address or the return address of the CAL instruction is sent to the data memory as an address. The operation of instruction execution differs depending on the instruction code in which IR is set. For example, the JMP instruction simply transfers the jump destination address set in IR in step 3 to the PC. On the other hand, in the CAL instruction, in order to save the return destination address, the data of the PC is transferred to the MDR and the data memory is used as a write cycle to save the return destination address, and at the same time, the subroutine address is set in the PC. To do so, transfer the address from the IR to the PC. In the LAC instruction, the data is returned from the data memory whose reading was started in step 2 in step 4 and set in the MDR. The data set in the MDR in stage 5 is transferred to the ACC. In the ADD instruction, the data set in the MDR in step 4 and the ACC data
Data is added in stage 5 and the result is set in ACC.

It can be understood from FIG. 3 that the contents of operation to be executed for each instruction are determined for each stage. FIG. 1 shows an embodiment of the hardware configuration of a computer according to the present invention for executing the subdivided operations shown in FIG.
In FIG. 1, the computer is composed of an adder 100 and a register group provided for each operation stage (stage 0 to stage 5). The same type of register constitutes a shift register so that data is transferred in a stage order. A series of shift registers are omitted in the middle when they are unnecessary, depending on the application, and can be deleted by a program (instruction sequence).
The shift register is connected in an annular shape so that the data needs to be retained, and the data circulates in the shift register. The operation of the embodiment shown in FIG. 1 will be described in detail below. The processing apparatus according to this embodiment includes an adder 100, AC
It is composed of C110, MDR120, PC140, IR150, data memory 160, and instruction memory 170. The ACC 110 has a register for holding data in each stage from the stage 0 to the stage 5. The register of each stage is configured as a shift register in the stage direction so that data can be transferred to the next stage bit by bit. In the program (instruction sequence),
In order to retain the data, the data of stage 5 has a structure transferred to stage 0. Similarly, the MDR120 is
It consists of shift registers from stage 3 to stage 5. In stage 4 of MDR120, data memory 160
Data is transferred from the memory, and in step 3, the data memory 1
The data is transferred to 60. The PC 140 is composed of shift registers from stage 0 to stage 5, and the data of stage 5 is stored in order to hold the next instruction address.
It has a structure to be transferred to the 0. PC140 in stage 0
Data is transferred to the instruction memory 170 as an address to read the instruction, and the instruction memory is set in the reading cycle. In addition, the data to be held in stage 1 is 1
A 1-adder 141 is attached for the purpose of increasing and setting the next instruction address. The IR 150 is composed of shift registers of stages 2 to 5. Steer
In step 2, the IR 150 receives an instruction from the instruction memory 170.

Next, the operation shown in FIG. 3 will be described with reference to FIG. PC14 for stage 0 when reading instructions
0 is used as an address register and its data is sent as an address to the instruction memory 170 via the channel 171.
Put memory into read cycle. PC in Stage 1
The data of 140 is incremented by 1 using the adder 141. In stage 2, an instruction is read from the instruction memory 170 and transferred to the IR 150 via the channel 172. Further, in this stage 2, a specific address holding the address part of the instruction code set in the IR 150 or the return destination of the CAL instruction is transferred to the data memory 160 via the channel 161. Here, it is clear that the instruction read is executed by sequentially transferring the data from stage 0 to stage 2. IR15 in stage 2
The instruction unit transferred to 0 controls execution of the following instructions from stage 3 to stage 5.

In the instruction execution, in the case of the JMP instruction, the channel 300 is transmitted from the IR 150 to the PC 140 in step 3.
The jump destination address is transferred via. In the CAL instruction, in step 3, the return address is transferred from the PC 140 to the MDR 120 via the channel 301, and the data is transferred.
Data memory 160 into a write cycle. Also, IR
The jump destination address is transferred from 150 to the PC 140 via the channel 300. In the RTN instruction, the return address is transferred to the MDR 120 in step 4, and the return address is transferred from the MDR 120 to the PC 140 in step 5.
To the channel 304. The JAN instruction determines the sign of the ACC 110 and performs the same operation as the JMP instruction. In the LAC instruction, the data memory 160 at stage 4
More data is transferred to the MDR 120, and the data transferred in stage 5 is transferred from the MDR 120 to the ACC 110 via the adder 100 and channels 306 and 307. In the SAC instruction, the ACC110 to MD in stage 3
The write data is transferred to the R120 via the channel 302, and at the same time, the data memory 160 is set to the write cycle. In the ADD instruction, data memory 1 in step 4
Data is transferred from MDR 60 to MDR 120 and stage 5
The data of ACC110 and MDR120 is channel 3
05 and 306 are supplied to the adder 100, and the adder 1
The output of 00 is transferred to ACC 110 via channel 307. From the above explanation, it is clear that the instruction is executed by sequentially transferring the data from stage 3 to stage 5 to the next stage. After the instruction execution is completed in step 5, the process returns to step 0 and the instruction reading is started. Therefore, in the processing device shown in FIG.
A program (instruction sequence) can be executed by cyclically executing the steps from 0 to 5.

Using the embodiment of FIG. 1, one hardware can process a plurality of instructions simultaneously. In the above description, it was clarified that the instruction sequentially executes each stage. This means that an instruction only occupies one of several stages. Therefore, the embodiment of FIG. 1 suggests that multiple instructions can be assigned to each stage. That is, in the embodiment shown in FIG. 1, 6 instructions are assigned to each stage, and 6 instructions can be simultaneously processed by 1 hardware. Further, in the embodiment of FIG. 1, since registers (ACC, MDR, PC, IR) are placed in each stage, the correlation between each stage can be eliminated. For this reason, a plurality of uncorrelated instructions can be executed at the same time, so that there is no reduction in processing efficiency due to branch instructions, which has been a problem in the conventional pipeline method. Therefore, since there is no invalidity in the execution of instructions, the pipeline is not disturbed. Further, since a plurality of different programs (instruction strings) can be executed by one piece of hardware, the present invention realizes the same function as the multiprocessor.

In the above description, the present invention has been described by exemplifying a case in which the stage is divided into six stages, but it is possible to decompose the stage into more stages and execute more instructions simultaneously. It is clear that you can do it. It is clear that this stage can be decomposed to the next level of the gate. In the embodiment shown in FIG. 1, the memory is divided into an instruction memory and a data memory. Therefore, the general purpose memory registers, especially the address register and the data register, which are placed in the conventional computer, can be omitted and the data can be transferred efficiently. That is, in FIG.
The address register of the instruction memory is the PC of stage 0, and the data register of the instruction memory is the IR of stage 2. The address register of the data memory is the IR of stage 2, and the data register is the MDR of stage 3 or stage 4. The usage of these registers is essentially compatible with the meaning of the registers placed in the computer, and there is no waste. A configuration in which the original functions of these registers are executed without any waste can be assigned to each stage, but this is possible in the embodiment of FIG. Further, although the instruction memory is accessed every time, the data memory may or may not be accessed depending on the content of the execution instruction. In particular, as the number of data registers in the computer increases, the frequency of referring to the data memory decreases. Further, although the capacity of the instruction memory is relatively small, the data memory is required to have a large capacity. From the above, it is appropriate that the instruction memory has a high speed and a small capacity, and the data memory has a low speed and a large capacity. The embodiment of FIG. 1 can handle this hierarchical structure of memory.

[0013]

According to the present invention, it is possible to provide a multiprocessor capable of improving the efficiency of use of hardware and simultaneously executing a plurality of instruction sequences with one piece of hardware. Therefore, the present invention provides an extremely effective means for realizing a high performance processing device.

[Brief description of drawings]

FIG. 1 is a structural diagram of a processing apparatus according to the present invention.

FIG. 2 is an instruction format of a processor.

FIG. 3 is an operation sequence of the processing device.

[Explanation of symbols]

100: Adder, 110: ACC, 120: MD
R, 140: PC, 141: 1 adder, 150: I
R, 160: data memory 170: instruction memory 161, 162, 171, 172, 200, 201, 2
02, 300, 301, 302, 304, 305, 30
6, 307: Channel

Claims (5)

[Claims] 1. A structure in which processing contents are divided into a plurality of stages, a register is provided for each stage, and data of the same kind of registers is sequentially transferred in the order of the stages. And a single instruction occupies one of the plurality of stages, and the instruction is executed by advancing the dedicated stage. 2. A processing device according to claim 1, wherein a plurality of instructions are assigned to the plurality of stages. 3. A device according to claim 1, wherein at least one of said registers is closed between stages.
A processor which constitutes a group, and the data stored in the loop is held between a plurality of instructions as necessary. 4. The structure according to claim 1, wherein the instruction read memory and the data memory are referred to, the instruction read stage refers to the instruction memory, and the instruction execution stage refers to the instruction memory. A processing device characterized by referring to the data memory. 5. The instruction register according to claim 1, wherein the address register of the instruction memory is a program counter in the instruction reading stage, and the data register of the instruction memory is the instruction cushion of the stage. A processing device characterized by being a register.