JPH05298094A - Processor - Google Patents

Abstract

PURPOSE:To improve the practical use efficiency of computer and to obtain a high performance computer by switching an instruction execution controlling register among stages plural times. CONSTITUTION:Since an instruction register(IR) 150 simultaneously performs instruction read out, operand readout, and instruction execution with a single instruction train, the instruction register(IR) 150 consists of shift registers passing the stages plural times so that the read-out instruction controls stages plural times. The IR 150 consists of the shift register from stage 2 to stage 5 of a second cycle, that from stage 0 to stage 5 of a third cycle, and that from stage 0 to stage 3 of a fourth cycle. The IR 150 receives an instruction from an instruction memory 170 in stage 2 of the second cycle, and execution of the instruction is controlled by the instruction code which the IR 150 receives at this time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer configuration method, and more particularly to a pipeline type multiprocessor configuration method for operating a large number of processing devices in parallel.

[0002]

2. Description of the Related Art In order to improve computer performance, there are a method of improving device performance, especially a circuit speed, and a method of improving computer structure. In order to improve the computer structure, it is extremely effective to divide the functions of the computer and use the so-called pipeline method, which uses the functions in an instruction sequence in a time division manner. This pipeline system is described, for example, in "The Architecture of Pipelined Computers", Hemisphere Publishing Corporation, 1981 ("The Archit
image of pipelined compu
ters "Hemisphere Publishi
ng Corporation 1981). In the conventional pipeline method, for example, the instruction reading (Instruction F
etch), instruction decoding (Decord), operand reading (Operand Fetch), instruction execution (E)
X operation) and write (Write) are divided into five continuous operations, and a series of these operations are executed while sequentially overlapping different instructions.

[0003]

However, the above-mentioned prior art is a method of effectively utilizing the prepared hardware in a time division manner, but it is not always necessary to utilize the prepared hardware with high efficiency. I can't say that In the ultimate pipeline, time-division operations can be performed in units of the gates that make up the computer, and instructions for the number of logical stages of the computer can be executed at one time. For this purpose, there is disclosed a micro-pipeline type computer configuration method in which the computer operation is divided into fine stages and the computer functions independent of the stages are assigned. In this already disclosed micro-pipeline type computer, the reference of the instruction memory and the data memory is arranged to be executed serially during a series of stages of the computer processing. Therefore, the conventional technique has a drawback that the processing speed of the computer cannot be increased because the reference speed of the instruction memory and the data memory is slow.

An object of the present invention is to improve the utilization efficiency of computer hardware and realize a high performance computer by a micropipeline system in which computer functions are subdivided.
It is an object of the present invention to provide a method of constructing a micro-pipeline type computer in which the instruction reading, the operand reading, and the instruction execution are simultaneously performed with respect to the processing function of a single instruction string.

[0005]

SUMMARY OF THE INVENTION The above-mentioned object is to allocate a register set to each subdivided computer function so that the data of the register set is decremented as the instruction execution sequence progresses.
This is achieved by adopting a micropipeline type processing device of a method of sequentially moving the data, and adopting a method of moving a register controlling instruction execution between the stages a plurality of times.

[0006]

If the method according to the present invention is adopted, it is a micropipeline method for executing a plurality of instruction sequences (programs), and even if an instruction memory or data memory with a long reference time is used, a fine pipeline pitch processing is performed. The device can be realized. Therefore, according to the present invention, it is possible to configure a multiprocessor that executes a plurality of programs with high efficiency with a single hardware.

[0007]

EXAMPLES The present invention will be described below with reference to examples.
The present invention takes a simple calculator as an example. The computer is an instruction memory (Instruction Mem).
ory: IM) to read the instruction from the data memory (D
The operand is read from the data memory (DM) and the operation is executed. This computer has an adder and the following four registers. ACC: Accumulator (holding operation registers and operation data) MDR: Memory data register (holding operands read from data memory and holding data to be written in data memory) PC: Program counter (Holding program execution address) IR: Instruction register (Holding instruction code) The instruction format of this computer is the instruction code (O
P Code) and an instruction address (Address). This instruction is read from the instruction memory, set in IR, decoded, and then executed. The computer has the following seven types of instructions. JMP: Unconditional jump to instruction address CAL: Subroutine jump to instruction address RTN: Return from subroutine jump JAN: Jump to instruction address if accumulator is negative (conditional jump) LAC: Instruction address data To the accumulator SAC: Write the data of the accumulator to the instruction address ADD: Add the data of the instruction address to the accumulator The computer of the present embodiment has a simple structure and the conventional pipe. Instruction reading of line technology (Instruction F
and read operands (Operand F
(etch) and instruction execution (Execution). However, more specifically, instruction reading, operand reading, and instruction execution are subdivided into more complicated operations.

An embodiment of the hardware configuration of a computer according to the present invention is shown in FIG. In FIG. 1, the calculator is an adder 1
00 and a group of registers arranged for each operation stage (stage 0 to stage 5). The adder 100 is
It has a pipeline structure in which a pipeline register and an operation logic circuit are combined, and an addition operation is executed in steps 5 to 1. Regarding the registers, the same kind of register constitutes a shift register so that the data is transferred in the stage order. A series of shift registers are omitted in the middle when unnecessary, depending on the application,
Further, in a program (instruction string) that needs to hold data, the shift register is connected in a ring shape, and the data circulates in the shift register. Instruction reading, operand reading, and instruction execution
It is completed by executing four cycles (cycle 1 to cycle 4). The operation of the embodiment shown in FIG. 1 will be described in detail below. The processing apparatus according to the present embodiment is an adder 10
0, ACC110, MDR120, PC140, IR1
50, a data memory 160, and an instruction memory 170. ACC110 is from stage 0 to stage 5
Up to each stage has a register for holding data. The register of each stage is configured as a shift register in the stage direction so that data can be transferred to the next stage bit by bit. Further, since the data is held in the program (instruction string), the data of stage 5 has a structure to be transferred to stage 0. Similarly, MDR12
0 is composed of shift registers from stage 3 to stage 5. In stage 4 of MDR120, data is transferred from data memory 160, and in stage 3, data is transferred.
The data is transferred to the data memory 160. The PC 140 is composed of shift registers from stage 0 to stage 5, and the stage 5 data is stored to hold the next instruction address.
The data has a structure transferred to stage 0. In step 0, the data of the PC 140 is transferred to the instruction memory 170 as an address to read the instruction, and the instruction memory is set to the reading cycle. Further, the stage 1 is provided with a 1 adder 141 for the purpose of increasing the held data by 1 and setting the next instruction address. The IR 150 performs instruction read, operand read, and instruction execution simultaneously in a single instruction sequence, so that the read instruction passes through the stage multiple times so as to control the stage multiple times. It consists of registers. The IR 150 is composed of a stage 2 to stage 5 in the second cycle, a stage 0 to stage 5 in the third cycle, and a stage 0 to stage 3 in the fourth cycle. It In Stage 2 of the second cycle, IR 150 receives an instruction from instruction memory 170. Instruction execution is controlled by the instruction code that IR 150 receives at this time. For example, in stage 2 of the second cycle, an address is sent to the data memory, and in stage 4 of the third cycle, the operand read from the data memory is set in the MDR 120.
Operations between operands are executed during stage 5 of the third cycle to stage 2 of the fourth cycle.

Next, the operation will be described in detail with reference to FIG. When reading an instruction, P at stage 0 of the first cycle
C140 is used as an address register and the data is sent as an address to the instruction memory 170 via the channel 171 to make the memory a read cycle. Next,
In page 1, the data of the PC 140 is incremented by 1 by using the 1 adder 141. In stage 2 of the second cycle, an instruction is read from the instruction memory 170 and transferred to the IR 150 via the channel 172. Also in this stage 2, I
Channel 1 is a specific address holding the address part of the instruction code set in R150 or the return destination of the CAL instruction.
The data is transferred to the data memory 160 via 61. here,
It is clear that the instruction read is executed by sequentially transferring the data from stage 0 of the first cycle to stage 2 of the second cycle. Also, the second cycle
The following second by the instruction section transferred to IR150 in J2
The execution of instructions from stage 3 of the cycle to stage 2 of the fourth cycle is controlled. In the instruction execution, in the case of the JMP instruction, the jump destination address is transferred from the IR 150 to the PC 140 via the channel 300 in step 3 of the second cycle. In the CAL instruction, in step 3 of the second cycle, the return destination address is transferred from the PC 140 to the MDR 120 via the channel 301, and then the data is further deleted.
Data memory 16 via channel 162 of data memory
0, and the data memory 160 is set to a write cycle. Further, the jump destination address is transferred from the IR 150 to the PC 140 via the channel 300. RT
In the N instruction, the return address is transferred to the MDR 120 in step 4 of the third cycle, and the return address is transferred from the MDR 120 to the PC 140 in the channel 304 in step 5.
Be transferred through. The JAN instruction determines the sign of the ACC 110 and performs the same operation as the JMP instruction. In the LAC instruction, data is transferred from the data memory 160 to the MDR 120 in stage 4 of the third cycle and transferred from stage 5 of the third cycle to stage 2 of the fourth cycle.
Data is transferred from the MDR 120 to the ACC 110 via the adder 100 and channels 306 and 307. In SAC instruction, from ACC110 to MD in stage 3 of the second cycle
The write data is transferred to the R120 via the channel 302, and at the same time, the data memory 160 is set to the write cycle. In the ADD instruction, the data is transferred from the data memory 160 to the MDR 120 in stage 4 of the third cycle, and the data of ACC 110 and MDR 120 is supplied to the adder 100 from channels 305 and 306 in stage 5. The output of the adder 100 is transferred to the ACC 110 via the channel 307 in the second cycle of the second stage. From the above description, the instruction execution is the second cycle
Obviously, this is done by sequentially transferring the data from stage 3 to stage 2 of the fourth cycle to the next stage. In the embodiment shown in FIG. 1, the IR 150 always holds the read instruction code. However, as the data is transferred, a part of the contents of the held data can be lost. Is also clear. In this case, the amount of hardware of the processing device can be reduced because the amount of data to be transferred or held is reduced.

FIG. 2 shows the pipeline operation of the processor according to the invention of FIG. Using the example of FIG. 1, 1
Multiple instructions can be processed simultaneously with one piece of hardware. It has already been shown that the instructions execute each stage in sequence. This means that an instruction only occupies one of several stages. Therefore, the embodiment of FIG. 1 suggests that multiple instructions can be assigned to each stage. That is, in the embodiment shown in FIG. 1, 6 instructions are assigned to each stage, and 6 instructions can be simultaneously processed by 1 hardware. In the embodiment shown in FIG. 1, six instruction strings can be processed simultaneously, but if the instruction string A is focused on, the instruction reading (I
F), operand read (OF), instruction execution (EX1
Alternatively, it can be seen that EX2) is simultaneously executed.
In Fig. 2, JMP and CA that do not require reading of operands
The L and JAN instructions end with EX1. The branch destination addresses of these branch related instructions are used as the next next instruction read address. In addition, the other instructions whose operands need to be read are terminated by EX2. The executed result is transferred to the register so that it can be executed in the next next instruction execution. In this embodiment, since the instruction memory and the data memory are referred to in parallel, the instruction reading, the operand reading, and the instruction execution are performed in parallel, the high-speed processing is possible even if the reference time of each memory is slow. The function can be realized. Further, in the embodiment of FIG. 1, since registers (ACC, MDR, PC, IR) are placed in each stage, the correlation between each stage can be eliminated. Therefore, since a plurality of uncorrelated instructions can be executed simultaneously, the present invention realizes the same function as a multiprocessor with a single hardware.

In the above description, the present invention has been described by exemplifying the case where the stage is divided into six, but it is possible to decompose into more stages, and more instructions can be executed simultaneously. It is possible, and it is clear that this stage can be decomposed to one stage of the gate.

[0012]

According to the present invention, the efficiency of use of hardware is improved, a plurality of instruction sequences can be simultaneously executed by one hardware, and a high-speed processing operation is performed using a memory with a slow reference time. , A multiprocessor can be provided. Therefore,
The present invention provides an extremely effective means for realizing a high performance processing device.

[Brief description of drawings]

FIG. 1 is a structural diagram of a processing apparatus according to the present invention.

FIG. 2 is a pipeline operation sequence of a processing device.

[Explanation of symbols]

100: Adder, 110: ACC, 120: MD
R, 140: PC, 141: 1 adder, 150: I
R, 160: data memory 170: instruction memory 161, 162, 171, 172, 200, 201, 2
02, 300, 301, 302, 304, 305, 30
6, 307: Channel

Claims (3)

[Claims] 1. A structure in which processing contents are divided into a plurality of stages, a register is provided for each stage, and data of the same kind of registers is sequentially transferred in the order of the stages. And a single instruction occupies one of the plurality of stages, and executes the instruction by advancing the dedicated stage. The processing device controls the stage a plurality of times by the instruction. 2. A processing device according to claim 1, wherein the register holding the read instruction is composed of a shift register which passes through the stage a plurality of times. 3. The method according to claim 2, wherein when the contents of the register holding an instruction are transferred between stages,
A processing device, wherein a part of the contents is deleted as needed.