JPH05297915A - Sequence simulator of programmable controller - Google Patents

Abstract

PURPOSE:To reduce the adjustment time and total debugging time due to mechanism interference in debugging operation by simulating a sequence and displaying an output state when a minicomputer performs input operation in the input order of a sequence file or simulatively. CONSTITUTION:When input operation is automatically carried out, an SEQIN task 13 registers the sequence file on a disk 14. The minicomputer 10 registers the sequence by an ZSEQEN task 1 first in the simulation execution and starts an SEQRUN (execution) task 12 or the SEQIN task 13. The SEQIN task 13 carries out simulative key input operation or automatic input operation in the input order of the input sequence file. The SEQRUN task 12 performs instruction-by-instruction and address-by-address input operation from the sequence registration file and judges instruction words, branching to processes by the instruction words is performed, and specific address data and the logical arithmetic result before the data are processed. A CRT 16 displays the result of the simulation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence simulator capable of simulating a sequence which is a ladder system of a programmable controller used for controlling an apparatus or the like.

[0002]

2. Description of the Related Art Conventionally, a debugging operation of a sequence of an apparatus for controlling by using a programmable controller is carried out while actually operating the apparatus, or a switch box or the like is connected instead of a sensor or switch of an input port. Then, check the output status by turning the switch on and off one point at a time, or use the debugger of the programmable controller to forcibly set and reset the I / O and see the sequence movement. It was being done.

FIG. 6 shows a conventional debugging procedure performed by connecting the conventional debugging to the apparatus. In this figure, 1 is a procedure for confirming a single operation for each of the n output ports,
Input the x port output condition, forcibly turn on the internal auxiliary memory contact (step S1), and the x port output is OK.
If the x-port output is OK as a result, it is determined whether the confirmation of the x-port output condition is OK (step S3). As a result, the x-port output is OK. If not, or if the confirmation of the x port output condition is not OK, correction is made (step S4) and the process returns to step S1. If the confirmation of the x-port output condition is OK, the process returns to step S1 and the confirmation is repeated n port times.

2 is a portion which can be operated continuously (A output → B
This is a confirmation work procedure for each output → C output, etc.), the step operation of the continuously operable portion is performed (step S5), and it is judged whether or not the operation confirmation is OK (step S6). If is not OK, it is corrected (step S7) and the process returns to step S5. Even if the operation confirmation is OK, the process returns to step S5, and the confirmation is repeated several times for the continuously operable blocks.

Reference numeral 3 is a comprehensive test procedure in the automatic mode, in which automatic operation (step S8) is performed to judge whether or not each operation timing confirmation is OK (step S9).
As a result, when each operation timing confirmation is OK, a continuous test (step S11) is performed. If the confirmation of each operation timing is not OK, the correction is performed (step S10), and the process returns to step S8.

[0006]

However, in the method of debugging a device using a conventional programmable controller while actually operating the device,
There was a risk that the malfunction of the sequence would cause malfunction and the mechanism would interfere, and adjustment of the positioning, etc. would have to be redone. Also, in the method using a switch box or a debugger, input is made one point at a time and checking is performed, so there is less possibility of mechanical interference, but debugging is performed for each single operation, and finally continuous operation Since it is a work to confirm the above, there is a problem that it takes a lot of man-hours.

In order to solve the above-mentioned problems, the present invention uses a minicomputer to enable sequence simulation, and to reduce the adjustment time due to mechanical interference during debug work and the total debug time. -The purpose is to provide a sequence simulator for the controller.

[0008]

In order to achieve the above object, the present invention, in a sequence simulator of a programmable controller, cooperates with the registering / changing means of the sequence of the programmable controller and the registering / changing means. An auxiliary storage device having a sequence registration file and an input sequence file, a sequence simulation executing means cooperating with the auxiliary storage device, and a memory area having an input / output and an internal auxiliary memory cooperating with the sequence simulation executing means. ,
An input sequence for a memory area, which cooperates with the auxiliary storage device and the memory area, and a display device for cooperating with the registration / change means, the sequence simulation executing means, and the input means for the memory area, are provided. The input operation is performed according to the input order of the files, the output state is confirmed on the display device, and the debugging work can be executed.

[0009]

According to the present invention, as described above, during sequence debugging of a device using a programmable controller, the sequence is registered in the minicomputer without using the programmable controller, and the input operation is simulated. Then, it is possible to confirm what kind of output is output at what timing on the display device (CRT) of the minicomputer.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is an overall configuration diagram of a sequence simulator of a programmable controller showing an embodiment of the present invention. As shown in this figure, a minicomputer 10 is used.

Therefore, reference numeral 11 is a task (SEQEN) for registering and changing the sequence on the disk. The file structure is shown in FIG. That is, for each record, on the left side, for example, command words such as LD and AND (maximum 10
It has 5 words for writing (character) and 1 word for writing an output port or address on the right side.

Reference numeral 12 is a task (SEQRU) for executing a simulation, and reference numeral 13 is a key input for simulation during execution of the simulation, writing in a memory area or inputting so that an input operation can be automatically performed. This is a task (SEQIN) for setting the input order and the like in the sequence file. The file structure is shown in FIG. That is, each record has one word for writing the input port or address on the left side and one word for writing the timer setting value on the right side.

Reference numeral 14 is a disk as an auxiliary storage device for registering a sequence registration file and an input sequence file. Reference numeral 15 denotes a memory area on the minicomputer used as an input / output port of the programmable controller and an internal auxiliary memory (the address of the internal auxiliary memory area can be changed by the controller). When executing the simulation, first, the sequence is registered by the SEQEN task 11, and the SEQRU task 12, S
Start the EQIN task 13 and set the SEQIN task 13
Input operation by key input point by point (specified address is ON)
Or an input sequence file is registered in advance and the file is designated to automatically execute the input sequence file based on the registered input order and input interval time. SE
In QRU task 12, 1 from the sequence registration file
Instructions, one address at a time, input words are determined, and processing branches for each instruction word. Then, the data of the designated address and the previous logical operation result are operated.

If the command word is an output command, the address designated by the result of the logical operation up to that point is turned on or off, or output to the display device (CRT) 16 is performed to initialize the logical operation-related registers, flabs and the like. Do.
When the END command is retrieved, the sequence registration file returns to the beginning. FIG. 4 shows the state transition when the sequence simulation is executed. Further, FIG. 5 shows an execution example of the sequence simulation.

That is, in FIG. 4, in the case of a normal command word, one command and one address are input from the disk 14 in which the sequence registration file and the input sequence file are registered (step), and the command word is judged. (Step) and execute the command (SEQR
U) is performed (step), the input / output and the internal auxiliary memory area 15 are read (step), the next one instruction and one address are input (step), and this is repeated sequentially.

Next, in the case of an output instruction word (input / output memory area), the above steps are the same, but after the step, the input / output memory of the memory area 15 is searched (step) and displayed. Output to the device (CRT) (step) and return to input of 1 command, 1 address (step). Next, in the case of the output command word (internal auxiliary memory area), the above steps from the output command word (input / output memory area) are the same, but after the step, the display device (CRT) is displayed. Return to the input of one instruction and one address without outputting (step).

The disk 14 in which the sequence registration file and the input sequence file are registered must be SE
The QEN task 11 can register and change the sequence. Further, from the disk 14 in which the sequence registration file and the input sequence file are registered, the designated address of the memory area 15 can be set or reset to access the memory area 15.

Next, an example of the execution will be described with reference to FIG. Here, as the internal control information of SEQRU, the logical operation result register RERT and the stack register STRT are used.
1, STRT2, STRT3, end flag ENF, interlock flag ILF, shift flag SIF are integer type 1 words.

Execution of an instruction word (SEQ
RU). In this case, in the file shown in Figure 2,
An instruction word and an output port or address are written for each record. (1) First, the processing content of the LD 0000 subroutine is to check 0 if the end flag ENF is 1, check the shift flag SIF if 0, and stack register ST if 1
RT2 → STRT3. Logical operation result register RE
Let RT be STRT2. If the shift flag SIF is 0, the logical operation result register RERT is set to 1 by the stack register STRT2 to set the logical operation result register RERT ← (0000).

(2) Next, the processing content of the subroutine AND 0010 is the stack register STRT1 ← (0
010), and the logical operation result register RERT ← RER
TAND STR T1 In other words, take the logical product. (3) Next, the processing content of the AND NOT 0020 subroutine is the stack register STRT1 ← (002
0), STRT1 is NOT-converted, and logical operation result register RERT ← RERT AND STRT1 is obtained. That is, the logical product is obtained with the back of the specified signal.

(4) Next, the processing content of the LD NOT 0030 subroutine is to check 0 if the end flag ENF is 1, check the shift flag SIF if 0, and set the stack register STRT2 → STRT3 if 1. If the logical operation result register RERT is set to STRT2 and the shift flag SIF is 0, the logical operation result register RERT is set to the stack register STRT2 and the shift flag SIF is set to 1.
Then, the logical operation result register RERT ← (0030)
Then, the RERT is NOT-converted.

(5) Next, the processing contents of the AND NOT 0040 subroutine is the stack register STRT.
1 ← (0040), NOT conversion of STRT1, logical operation result register RERT ← RERT AND ST
Let it be RT1. (6) Next, the processing contents of the OR LD subroutine are
Logical operation result register RERT ← RERT OR ST
Let it be RT2. Here, STRT2 shows the results up to (3).

(7) Next, the processing contents of the LD 0050 subroutine are 0 if the end flag ENF is 1, 0
If so, the shift flag SIF is checked. If it is 1, the stack register STRT2 → STRT3 is set. The logical operation result register RERT is set to STRT2, and the shift flag SI
If F is 0, the logical operation result register RERT is set to the stack register STRT2, the shift flag SIF is set to 1, and
The logical operation result register RERT ← (0050).
Here, the results up to (6) are the stack register STR.
Set to T2.

(8) Next, the processing contents of the subroutine of OR 0060 are stack register STRT1 ← (00
60). Logical operation result register RERT ← RER
This is TOR STR T1. In other words, take the logical sum. (9) Next, the processing contents of the AND LD subroutine are as follows: logical operation result register RERT ← RERT AND
Set to STRT2. Here, STRT2 shows the results up to (6).

(10) Next, the processing contents of the subroutine of AND 1000 are stack register STRT1 ←
(1000) and the logical operation result register RERT ← R
ERT AND STR T1 In other words, take the logical product. (11) Next, the processing contents of the OUT 0200 subroutine are output to the display device (CRT) if the logical operation result register RERT is 1.

(12) Next, the processing contents of the subroutine of TIM 010 pass to the timer task with parameters 010 and # 0005, and when the set value is UP, the timer task receives TI.
Set M010 ← 1. The present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0027]

As described above in detail, according to the present invention, since the debugging work of the sequence of the programmable controller can be performed on the minicomputer, the risk of mechanical interference in the actual machine can be avoided. .. Moreover, since it is not necessary to use a switch box or the like, the work can be simplified.

Further, since the debugging work can be started at the time of manufacturing the device or at the time of mechanical adjustment, the device can be efficiently started up.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a sequence simulator of a programmable controller showing an embodiment of the present invention.

FIG. 2 is a file configuration diagram of SEQEN showing an embodiment of the present invention.

FIG. 3 is a file configuration diagram of SEQIN showing an embodiment of the present invention.

FIG. 4 is a diagram showing a state transition at the time of executing a sequence simulation showing an embodiment of the present invention.

FIG. 5 is a diagram showing an execution example of sequence simulation showing an embodiment of the present invention.

FIG. 6 is a diagram showing a debug procedure for performing conventional debug by connecting to a device.

[Explanation of symbols]

 10 minicomputer 11 SEQEN task (registration / change of sequence) 12 SEQRU task (execution of simulation) 13 SEQIN task (input to memory area) 14 auxiliary storage device (disk) 15 memory area 16 display device (CRT)

Claims (1)

[Claims] 1. A programmable controller sequence registration / modification means, (b) an auxiliary storage device having a sequence registration file and an input sequence file cooperating with the registration / modification means, and (c) Sequence simulation execution means cooperating with an auxiliary storage device, (d) a memory area having input / output and an internal auxiliary memory cooperating with the sequence simulation execution means, and (e) the auxiliary storage device and memory area An input means for cooperating with the memory area, and (f) a display device cooperating with the registering / changing means, execution means for sequence simulation, and input means for the memory area,
(G) According to the input order of the input sequence file,
A sequence simulator of a programmable controller capable of performing an input operation, confirming the output state on the display device, and executing a debug operation.