JPH05297405A - Active matrix display device - Google Patents

Abstract

PURPOSE:To efficiently arrange pixels by arranging the pixels reversely to adjacent pixels across data lines as to an electrostatic display device which has an active matrix. CONSTITUTION:Pixels Zn,m connected to gate lines Xn and data lines Ym are arranged alternately with pixels Zn+1,m. connected to gate lines Xn+1 in lines below them and the same data lines Ym. The pixel electrodes of the pixels Zn,m cross gate lines Xn+1 to form auxiliary capacitances C here. Consequently, TFTs are not nearby the parts where the auxiliary capacitances C are thus formed, so there is not the danger that the TFTs are broken. When the pixels are alternately arranged as mentioned above, the color assignment of the pixels is conveniently performed. Further, ideal hexagonal or honeycomb-shaped structure is obtained without bending electric conductors so as to improve the mixture of colors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic display device such as a liquid crystal display device, and more particularly to a display device having an active matrix.

[0002]

2. Description of the Related Art In recent years, active matrices for driving liquid crystal displays have been extensively studied and put into practical use. In a conventional active matrix circuit, a capacitor sandwiching a liquid crystal is formed between a pixel electrode and a counter electrode, and a thin film transistor (TFT) controls an electric charge which flows in and out of the capacitor. In order to display images stably, it was required that the voltage of both electrodes of this capacitor be kept constant, but it was difficult for several reasons.

The main reason was that even when the TFT was in the off state, the charge leaked from the capacitor. In addition, there was a leak inside the capacitor, but in general, the leak from the TFT was larger by about one digit. When this leak is significant, a phenomenon called flicker occurs in which the contrast of the image changes at the same cycle as the frame frequency. In addition, the phenomenon (ΔV) in which the gate signal capacitively couples with the pixel potential due to the parasitic capacitance between the gate electrode of the TFT and the pixel electrode and the voltage fluctuates (ΔV) is also one of the causes.

In order to solve these problems, an auxiliary capacitance (also called an additional capacitance) has been attached in parallel with the pixel capacitance. This is shown in a circuit diagram as shown in FIG. That is, such an auxiliary capacitance increases the time constant for discharging the charge of the pixel capacitance. Also, ΔV
When the gate pulse (signal voltage) is V _G , the pixel capacitance is C _LC , the auxiliary capacitance is C, and the parasitic capacitance between the gate electrode and the pixel electrode is C ′, ΔV = C′V _G / (C _LC + C ′ + C), and if C is larger than C ′ and C _LC , ΔV could be reduced.

[0005]

Conventionally, such an auxiliary capacitor has a circuit arrangement as shown in FIG. 1 (B) or (C). In the method of FIG. 1B, the gate line X
There has been a technique in which a ground line, for example, X _n 'as shown in the drawing is formed in parallel with _n (or Y _m ) and the pixel electrode is overlapped on this to form a capacitor C. A typical structure is shown in FIG. The auxiliary capacitance C is shown in the shaded area. However, this method has a drawback that the aperture ratio is lowered and the screen becomes dark because the wiring must be newly formed.

[0006] In contrast, with a part of the pixel connected to the gate line X _n are overlapped to the next gate line X _{n + 1} as shown in FIG. 1 (C), which shall be the storage capacitance C Is proposed. In this case, since no new wiring is formed, the aperture ratio does not decrease. But conventionally,
Regarding the pixel arrangement, the pixel Z _{n, m} and the pixel Z _{n + 1, m which} are connected to the same data line Y _m and whose gate lines are adjacent to each other are provided in the same direction with respect to the data line, and are efficient pixels. No particular consideration was given to the placement of. That is, in this case, there is a risk that the pixels in the upper row come into contact with the TFTs in the pixels in the lower row. The present invention has been made in view of such a point, and proposes an efficient pixel arrangement.

[0007]

In order to solve this problem, in the present invention, the adjacent pixels Z _{n, m} and Z _{n + 1, m} are arranged opposite to each other with a data line in between. Is characterized by. It is typically shown in FIG. That is, the pixel Z is connected to the gate lines X _n and the data lines Y _m in the present invention
_{n and m} are the same data line Y as the gate line X _{n + 1 in} the row below
a pixel Z _{n + 1, m} to be connected to _m to staggered. The pixel electrode of the pixel Z _{n, m} crosses the gate line X _{n + 1} and forms an auxiliary capacitance C (hatched portion) there.

The characteristic of the storage capacitor thus formed is that it is easy to manufacture, unlike the case where it is formed in a difficult pattern as in the conventional case. As is clear from the figure, in the conventional method, the pixel electrode had to overlap the gate line adjacent to the TFT. In this case, there was a high risk of destroying the TFT. However, in the present invention, the portion where the auxiliary capacitance is provided is T
Since there is no FT nearby, there is no danger of destroying the TFT. Further, in the case of arranging each other in this way, it is convenient to arrange the pixels in color as they are.

That is, conventionally, in order to improve the color mixing property, the arrangement of pixels has been made into a honeycomb shape or a hexagonal shape, but at that time, the wiring is bent accordingly. This leads to an increase in wiring resistance, and also causes defects due to the difficulty of fabrication. However, according to the present invention, an ideal hexagonal structure can be obtained without the need to bend the wiring.

In order to carry out the present invention, it is not necessary to use a particularly advanced technique, and the conventional TFT manufacturing technique may be used, so that the present invention can be carried out very easily. A method for manufacturing a circuit having the structure of the present invention will be described below as an example.

[0011]

EXAMPLE FIG. 2B shows a schematic view of a circuit having an auxiliary capacitor manufactured in this example, which is seen from above. In the figure,
X _n is a gate wiring. X _{n + 1} is a gate line in the next row, which also forms an auxiliary capacitance of the pixel Z _{n, m} . Y _m is a data line. C _LC represents a pixel capacitance (pixel electrode), and C is an auxiliary capacitance formed by overlapping X _n and C _LC .

FIG. 3 shows the manufacturing process of this embodiment. Drawings (A-1), (B-1), (C-1), (D-1) are sectional views, and (A-2), (B-2), (C-2),
(D-2) is a top view. Since the details of each process are described in Japanese Patent Application Nos. 4-30220, 4-38637 and 3-273377, they will not be described here.

First, a base silicon oxide film 2 is formed on a substrate 1. This may be a multilayer film of silicon oxide and silicon nitride. Then, the island-shaped semiconductor region 3 is formed. further,
A gate insulating film (silicon oxide) 4 was formed, and a gate line X _n (5) and a next line gate line X _{n + 1} (6) were formed of aluminum. Although not shown in FIGS. 3A-1 and 3A-2, a semiconductor region similar to the island-shaped semiconductor region 3 is formed on the left side or the right side of the gate line 6. To be done.

Thereafter, anodic oxidation was performed to form aluminum oxide coatings 7 and 8 around the gate wirings 5 and 6. Then, impurity implantation is performed to form an impurity region (source / drain) 9. (Fig. 3 (B-1)
And (B-2))

Then, a silicon oxide interlayer insulator is formed to a thickness of 50.
Only 0 nm was formed. Here, the silicon oxide 10 is left only in the portion below the data line, and the rest is removed. (Fig. 3
(C-1) and (C-2))

A capacitance is generated at the intersection of the data line and the gate lines 5 and 6, and this capacitance causes a delay of the gate signal and data. In order to reduce the capacitance, it is preferable to form the interlayer insulator thick as described above, but for the other portions, such an interlayer insulator is not particularly required. In particular, when the silicon oxide layer formed up to the one formed as the gate insulating film is removed as in the present embodiment, the conventional contact hole is unnecessary, and therefore, the contact failure is remarkable. It was possible to reduce.

In such a process, a mask is required for the portion of the silicon oxide region 10, but no mask is particularly required for the other portions. This is because the aluminum oxide formed as the anodic oxide film has extremely strong corrosion resistance, and the etching rate, for example, in etching with buffer hydrofluoric acid is sufficiently slower than the etching rate of silicon oxide.

Therefore, with respect to the gate electrode portion, the silicon oxide film can be etched in a self-aligned manner. conventionally,
Fine mask alignment was required to form the contact hole of the TFT, but this is not necessary in this embodiment. Naturally, the silicon oxide formed on the auxiliary wiring is also removed and the anodic oxide film is exposed.

Finally, the data line 11 was formed of aluminum or chrome, and the pixel electrode 12 was formed of ITO. At this time, the auxiliary capacitance 13 could be formed by disposing the pixel electrode and the gate line 6 so as to overlap each other.
(Fig. 4 (D-1) and (D-2)) Of course, the TFT
It is also possible to form an aluminum (or chrome) electrode / wiring on the pixel electrode side of, and form the pixel electrode with ITO thereon.

In the present embodiment, the structure of the cross section of the auxiliary capacitor has a structure of metal wiring (aluminum) / anodic oxide (aluminum oxide) / pixel electrode (ITO). In this case, aluminum oxide has a relative dielectric constant three times as high as that of silicon oxide, and therefore contributes to increasing the auxiliary capacitance. When a larger auxiliary capacitance is required, tantalum or titanium may be used for the gate line, anodic oxidation may be performed, and those oxides may be used as the dielectric of the auxiliary capacitance.

Alternatively, a method of metal wiring / oxide (which can be formed by a CVD method or a sputtering method such as silicon oxide or silicon nitride) which is conventionally used, without using such a manufacturing method / structure is used. May be used.

[0022]

As described above, according to the present invention, the pixels can be efficiently arranged. Such arrangement of pixels not only reduced the number of defects, but was also effective in displaying color. The above description relates to a planar type TFT often used for polysilicon TF, but an inverted stagger type TFT often used for amorphous silicon TFT.
However, it is clear that the same effect can be obtained.

[Brief description of drawings]

FIG. 1 shows a circuit diagram of an active matrix.

FIG. 2A shows a circuit layout of an active matrix according to a conventional method. (B) shows the circuit arrangement of the active matrix according to the present invention.

FIG. 3 shows an example of a process of manufacturing a circuit according to the present invention.

[Explanation of symbols]

 1 Substrate 2 Base Silicon Oxide Layer 3 Island Semiconductor Region 4 Gate Insulating Film 5, 6 Gate Electrode / Wiring 7, 8 Anodic Oxide Film 9 Impurity Region 10 Interlayer Insulator 11 Data Line 12 Pixel Electrode 13 Auxiliary Capacitance

Claims (2)

[Claims] 1. An electrostatic display device having an active matrix, comprising: a first pixel connected to a first gate line and a first data line; and a second gate line in a row next to the first gate line. The second pixel connected to the first data line means the first pixel
It is installed in the opposite positions with the data line of
An active matrix display device, wherein the pixel electrode of each pixel covers the second gate line through an insulator. 2. The method according to claim 1, wherein the first and second
The display device characterized in that the surface of the gate line is covered with anodic oxide.