JPH05297066A - Lsi tester - Google Patents

Abstract

PURPOSE:To comply with an expected-value memory by means of a small- capacity memory by a method wherein a response signal which is output from an object under test is divided into a plurality of blocks and expected-value data is compared with the response signal by giving the data to the individual blocks in a time-sharing manner. CONSTITUTION:In an expected-value memory 11, an address is designated by means of a program counter 2; the expected-value data of a response signal which is output from an object (DUT) 4 under test is output to individual judgment circuits 121, 122 to 12m. A response signal is input to the circuits 121 to 12m from the DUT 4 by making use of jch as one block; the expected-value data at a j-bit is input from the memory 11 in a timesharing manner. The expected-value data is held in the circuits 121 to 12m by means of latch clocks CK11 to CK1m which are input to the circuits 121 to 12m from a latch-signal generation circuit 101; it is compared with the response signal by means of a strobe block CK3 which is input in succession. Thereby, whether the DUT 4 is good or not is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an object to be measured (hereinafter referred to as
An LSI tester that judges pass / fail of a DUT based on fail data obtained by comparing a response signal of (a DUT is omitted) and expected value data. More specifically, the expected value memory in which expected value data is stored has a small capacity. The present invention relates to an LSI tester that can be supported by a memory.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional LSI tester. In the figure, 1 is a timing generator,
A timing clock that is the operation timing of each circuit is output. A program counter 2 designates an address in a pattern memory (not shown) based on a test rate clock CK ₁ (hereinafter referred to as a rate clock CK ₁ ) input from the timing generator 1 and an address in an expected value memory 3. To do.

The pattern memory is a memory in which pattern data for inspecting the DUT 4 is stored, and the pattern data D is stored in accordance with the address designated by the program counter 2.
Output to UT4. On the other hand, the expected value memory 3 is the DUT 4
In the memory in which expected value data for inspecting the response signal is stored, the expected value data is output to the determination circuit 5 in accordance with the address designated by the program counter 2.

In the expected value memory 3, the DUT 4 is used as a comparator.
Type 6₁, 6₂, ~ 6_nSame number of response signals to output via
Has a bit width of₁, 6₂, ~ 6
_nExpected value from each channel in the judgment circuit 5 provided for each
Output the data. The judgment circuit 5 is a timing generator.
Latch clock CK input from the data 1 ₂On the basis of
The expected value data in the expected value memory 3 is held and this expected value data is
Data strobe clock CK₃DUT5 based on
It is compared with the response signal input from.

FIG. 5 is a diagram showing the configuration of the expected value memory shown in FIG. The expected value memory 3 has the same bit width as the number of output channels of the DUT 4, and outputs expected value data according to the address designated by the program counter 2. The drawing shows an example in which expected value data in the address “n + 1” area indicated by hatching is output to the determination circuit.

FIG. 6 is a timing chart for explaining the operation of a conventional LSI tester, which is a case where a register circuit integrated as shown in FIG. 7 is used as a DUT. In FIG. 7, reference numeral 4 ₁ denotes a shift register in which n 1-bit registers are connected in series, and data is sequentially taken in each time the first clock signal CK ₄₁ is input. 4 ₂ is a parallel register for the second clock signal C
When K ₄₂ is input, n stored in the shift register 4 ₁
Collect and output bit data all at once.

In FIG. 6, (A) is the rate clock CK ₁ output from the timing generator, (B) is the address specified by the program counter, and (C) is the latch clock C output from the timing generator to the decision circuit.
K ₂ and (D) are expected value data held in the judgment circuit,
(E) is the data input to the DUT, (F) is the first clock signal CK ₄₁ input to the DUT, and (G) is the DUT.
The second clock signal ₄₂ CK ₄₂ , (H) input to
The data output from the UT, (I), is the strobe clock CK ₃ output from the timing generator to the determination circuit.

(1) The rate clock CK ₁ is input from the timing generator 1 to the program counter 2.
The program counter 2 specifies the address of the expected value memory 3 and the address of the pattern memory based on this rate clock CK ₁ . The expected value memory 3 with the specified address outputs the expected value data to the determination circuit 5, and the pattern memory outputs the inspection data to the DUT 4.

(2) Subsequently, the latch clock CK ₂ is inputted from the timing generator 1 to the decision circuit 5,
Expected value data input from the expected value memory 3 is held. The operations (1) and (2) are repeated every time the rate clock CK ₁ is input. (3) On the other hand, the data output from the pattern memory to the DUT 4 is sequentially fetched into the shift register 4 ₁ by the input of the first clock signal CK ₄₁ .

[0010] (4) After the n data is loaded to the shift register 4 _1, the second clock signal CK ₄₂ is input to the DUT 4, the parallel register 4 ₂ collectively are n data comparator It is output to the determination circuit 5 via 6 ₁ , 6 ₂ , and 6 _n . (4) ′ At this time, the determination circuit 5 has already determined that the expected value data specified by the (n + 1) th rate clock CK ₁ from the expected value memory 3, that is, the expected value data stored at the (n + 1) th address. It has been entered.

(5) In this state, when the strobe clock CK ₃ is input from the timing generator 1 to the determination circuit 5, the determination circuit 5 receives the input n from the DUT 4.
This data is compared with the expected value data input from the expected value memory 3, and the result is output to the fail memory.

[0012]

SUMMARY OF THE INVENTION Such a conventional LS
The I tester has one pattern comparison cycle for every n pattern input cycles when the DUT has serial input and parallel output, that is, like a shift register.
In the case where the expected value memory is only used once, the expected value memory is used only at a ratio of n: 1, so that the memory usage rate is low and the expected value memory having a large number of bits is required. is there.

The present invention has been made in view of the above point, and divides the response signal output from the DUT into a plurality of blocks, and gives expected value data to each block from the expected value memory in time division for comparison. It is an object of the present invention to provide an LSI tester characterized in that the expected value memory can be handled by a memory having a small capacity.

[0014]

In order to achieve such an object, the present invention divides a response signal output from an object to be measured from a plurality of pins into a plurality of blocks, and outputs expected value data for each block. An LSI tester for comparing and judging whether the object to be measured is good or bad based on the fail data of the comparison result, the judgment circuit being provided for each of the blocks and receiving a plurality of response signals, and the judgment circuit. Expected value data to be output for each is stored, a memory that sequentially outputs the expected value data to each determination circuit based on the address specified by the program counter, and the expected value data output from this memory to the determination circuit. A latch signal generation circuit for outputting the latched signal to be held to each judgment circuit is provided, and a response signal output from the object to be measured is expected value data for each judgment circuit. Comparison, is characterized by determining the acceptability of the object to be measured.

[0015]

Each component of the present invention operates as follows. The determination circuit divides the response signal output from the measured object into a plurality of blocks, and compares each block with expected value data. The expected value memory stores expected value data to be output for each determination circuit, and sequentially outputs the expected value data to each determination circuit based on the address designated by the program counter. The latch signal generation circuit outputs a latch signal holding the expected value data output from the expected value memory to each determination circuit.

[0016]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of the LSI tester of the present invention. The DUT is assumed to be the n-bit shift register described in the conventional example, and those having the same operation as those in FIG.

In the figure, 10 is a timing generator, and 1
Reference numeral 1 is an expected value memory, an address of which is designated by the program counter 2, and each judgment circuit 12 ₁ , 12 ₂ , to 12 _m.
The expected value data of the response signal output from the DUT 4 is output to. Judging circuit 12 _1, 12 _2, to 12 _m, the response signal from DUT4 is input to jch as one block, expected value data of j bits are input from the expected value memory 11.

FIG. 2 is a diagram showing the structure of the expected value memory of the LSI tester of the present invention, and the portion indicated by the broken line shows the conventional expected value memory. The data in the shaded area of the address “n + 1” is the expected value data output to the determination circuit 12 _1, and the data in the shaded area of the address “n + 2” is the expected value data output to the determination circuit 12 _2. Similarly, the expected value data of the address “n + m” is output to the determination circuit 12 _{m thereafter} . Expected value data latch signal generating circuit 10 ₁ from the determination circuit 12 _1, 12 _2, 12 latch clock is input to the _m CK ₁₁ determined by ～CK _{1 m} circuit 12 _1, 12 _2, held in the 12 _m, Then, it is compared with the response signal by the strobe clock CK ₃ inputted.

FIG. 3 is a timing chart for explaining the operation of the LSI tester of the present invention.
The case where 28 channels are set as one block is described. The data of ₁ to 128 ch is input to the first determination circuit 12 _1, and the data of 129 to 256 ch is input to the second determination circuit 12 ₂ . The expected value memory 11 is a 128-bit memory.

[0020] In the figure_,(A) is a rate clock CK₁,
(B) is the expectation specified by the program counter 2.
Address of the value memory 11, (C) is the expected value memory 11
Expected value data to be output, (D) is the first determination circuit 12₁
Latch clock CK input to₁₁, (E) is the
One determination circuit 12₁Expected value data stored in (F)
Is the second determination circuit 12₂The second latch lock to be input to
CK₁₂, (G) is the second determination circuit 12₂Retained in
Expected value data, (H) is timing generator 10
Each determination circuit 12₁, 12₂, ~ 12_mThe strike to be entered in
Robe clock CK₃Is.

(1) The address is updated by the rate clock CK ₁ input from the timing generator 10, and the expected value memory 11 compares the stored expected value data with the first and second determination circuits 12 ₁ and 12 ₁ . Output to ₂ . still,
Data output from the first data (address “1”) at the 256th rate clock CK ₁ (address “25”)
6 ") is mask data and is not used for determining the response signal of the DUT 4. (2) When the 257th rate clock CK ₁ is output from the timing generator 10, the tester enters a determination cycle.

(3) In the expected value memory 11 in which the address "257" is designated by the 257th rate clock CK ₁ , the expected value data D ₁ is sent to the first decision circuit 12 ₁ and the second decision circuit 12 ₂ . Output. (4) The first determination circuit 12 ₁ is subsequently input with the first latch lock CK ₁₁ from the latch signal generation circuit 10 ₁ .
The expected value data D ₁ is latched.

(5) Next, in the expected value memory 11, the address "258" is designated and the expected value data D ₂ is output to the first determination circuit 12 ₁ and the second determination circuit 12 ₂ . (6) The second determination circuit 12 ₂ is subsequently input with the second latch lock CK ₁₂ from the latch signal generation circuit 10 ₁ .
The expected value data D ₂ is latched.

(7) At this time, the response signal has already been input to the first and second determination circuits 12 ₁ and 12 ₂ at the 257th rate clock CK ₁ . First and second determination circuit 1
When the strobe clock CK ₃ is input to the timing signals 2 ₁ and 12 _{2 from} the timing generator 10, the first determination circuit 12 ₁ outputs the expected value data D ₁ and DUT ₁ to 128 c.
Comparison of the data with the h is carried out, in the second judging circuit 12 _2, the expected value data D ₂ and the DUT outputs 129-25
Data comparison with 6ch is performed.

[0025]

As described above in detail, the LS of the present invention
The I tester divides the response signal output from the DUT into a plurality of blocks and inputs the divided signals to a judgment circuit, and time-divisionally supplies expected value data to the judgment circuit from an expected value memory. Therefore, expected value data can be stored in a memory having a small capacity, and an expensive memory having a large storage capacity is not required.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of an LSI tester of the present invention.

FIG. 2 is a diagram showing a configuration of an expected value memory of the LSI tester of the present invention.

FIG. 3 is a timing chart illustrating the operation of the LSI tester of the present invention.

FIG. 4 is a configuration block diagram of a conventional LSI tester.

FIG. 5 is a diagram showing a configuration of an expected value memory used in a conventional LSI tester.

FIG. 6 is a timing chart explaining the operation of a conventional LSI tester.

FIG. 7 is a circuit diagram of a register circuit that is a DUT.

[Explanation of symbols]

10 ₁ Latch signal generation circuit 11 Expected value memory 12 ₁ ~ Judgment circuit

Claims (1)

[Claims] 1. A response signal output from an object to be measured from a plurality of pins is divided into a plurality of blocks, each block is compared with expected value data, and the fail data of the comparison result is used to determine whether the object to be measured is good or bad. An LSI tester for judging, which is provided for each of the blocks, stores a judgment circuit to which a plurality of response signals are input, and expected value data to be output for each judgment circuit, and specifies the program counter. A memory that sequentially outputs the expected value data to each determination circuit based on an address; and a latch signal generation circuit that outputs a latch signal that holds the expected value data output from the memory in the determination circuit to each determination circuit. And a response signal output from the object to be measured is compared with expected value data for each of the determination circuits to determine the quality of the object to be measured. LSI tester was.