JPH0529372A - Integrated circuit package - Google Patents
Integrated circuit packageInfo
- Publication number
- JPH0529372A JPH0529372A JP20622591A JP20622591A JPH0529372A JP H0529372 A JPH0529372 A JP H0529372A JP 20622591 A JP20622591 A JP 20622591A JP 20622591 A JP20622591 A JP 20622591A JP H0529372 A JPH0529372 A JP H0529372A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit package
- power supply
- pattern
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、集積回路を収容する集
積回路パッケージに係わり、特に集積回路パッケージの
電源供給パターンの構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit package containing an integrated circuit, and more particularly to the structure of a power supply pattern of the integrated circuit package.
【0002】[0002]
【従来の技術】従来、この種の集積回路パッケージにお
いて、集積回路パッケージの電源供給パターンは、実装
されている集積回路の電源パッドから集積回路パッケー
ジの外部の電源ピンあるいは 電源パッドに直接接続さ
れており、パターンの途中で集積回路パッケージ表面層
を経由することはなかった。2. Description of the Related Art Conventionally, in this type of integrated circuit package, a power supply pattern of the integrated circuit package is directly connected to a power supply pin or a power supply pad outside the integrated circuit package from a power supply pad of the mounted integrated circuit. However, it did not pass through the surface layer of the integrated circuit package in the middle of the pattern.
【0003】[0003]
【発明が解決しようとする課題】前述した従来の集積回
路パッケージにおいては、集積回路パッケージの電源ピ
ンの全てに電源が供給され、不要なチップまで動作する
ことにより、他の回路が誤動作を起こす可能性があるこ
とおよび不要な電力消費や冷却のための手段が必要とな
る等の問題があった。In the above-mentioned conventional integrated circuit package, power is supplied to all the power supply pins of the integrated circuit package, and unnecessary chips operate, so that other circuits may malfunction. However, there is a problem in that there is a need for power consumption and unnecessary means for cooling.
【0004】したがって本発明は、前述した従来の問題
に鑑みてなされたものであり、その目的は、必要な集積
回路を動作可能とし、機能追加等で当面動作が不要な集
積回路を動作しないようにした集積回路パッケージを提
供することにある。Therefore, the present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to enable a necessary integrated circuit to operate and not to operate an integrated circuit which does not need to operate for the time being due to addition of functions. To provide the integrated circuit package.
【0005】[0005]
【課題を解決するための手段】このような目的を達成す
るために本発明による集積回路パッケージは、集積回路
の電源パターンの一端を集積回路パッケージの表面層に
設けた導電性パッドと、集積回路パッケージの電源ピン
あるいは 電源パッドに接続される電源パターンの一端
を集積回路パッケージ表面層に設けた導電性パッドとを
集積回路パッケージ上に設けた複数の導電性パッド同士
で対応する電源のパッドを接続可能とする構造を有して
いる。In order to achieve such an object, an integrated circuit package according to the present invention includes a conductive pad having one end of a power supply pattern of the integrated circuit provided on a surface layer of the integrated circuit package, and an integrated circuit. Connect one end of the power supply pattern that is connected to the power supply pin or power supply pad of the package to the conductive pad provided on the surface layer of the integrated circuit package, and connect the corresponding power supply pad between the multiple conductive pads provided on the integrated circuit package It has a structure that enables it.
【0006】[0006]
【作用】本発明においては、集積回路の電源パターンと
集積回路パッケージの電源ピンとを電気的に接続させる
構成により、必要な集積回路については動作可能とし、
不用な集積回路には接続させずに動作不可能とし、不用
な集積回路が動作しないためにこの動作による雑音の発
生等がなく、動作が安定するとともに不用な集積回路部
分の電力発生がなくなる。In the present invention, the necessary integrated circuit can be operated by the structure in which the power supply pattern of the integrated circuit and the power supply pin of the integrated circuit package are electrically connected,
The operation is not performed without connecting to an unnecessary integrated circuit, and since the unnecessary integrated circuit does not operate, noise is not generated due to this operation, the operation is stable, and unnecessary electric power is not generated in the integrated circuit portion.
【0007】[0007]
【実施例】以下、図面を用いて本発明の実施例を詳細に
説明する。図1は本発明による集積回路パッケージの一
実施例による構成を示す要部拡大斜視図である。同図に
おいて、集積回路パッケージ1の電源ピン2は、集積回
路パッケージ1の表面層に設けられた導電性パッド3に
接続されている。一方、集積回路パッケージ1の中に収
容されている集積回路4の電源端子5は、ボンディング
配線6により集積回路パッケージ1の中の導電性パター
ン7に接続され、この導電性パターン7が集積回路パッ
ケージ1の表面層に設けられた導電性パッド8に接続さ
れている。集積回路パッケージ1の信号ピン9は、電源
ピン2のように集積回路パッケージ1の表面層のパッド
3は経由せず、集積回路4の図示しない信号ピンへ接続
されている。Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is an enlarged perspective view of an essential part showing a configuration according to an embodiment of an integrated circuit package according to the present invention. In FIG. 1, the power supply pin 2 of the integrated circuit package 1 is connected to the conductive pad 3 provided on the surface layer of the integrated circuit package 1. On the other hand, the power supply terminal 5 of the integrated circuit 4 housed in the integrated circuit package 1 is connected to the conductive pattern 7 in the integrated circuit package 1 by the bonding wiring 6, and this conductive pattern 7 is integrated into the integrated circuit package. 1 is connected to the conductive pad 8 provided on the surface layer. The signal pin 9 of the integrated circuit package 1 is connected to a signal pin (not shown) of the integrated circuit 4 without passing through the pad 3 on the surface layer of the integrated circuit package 1 unlike the power supply pin 2.
【0008】ここで集積回路パッケージ1をプリント配
線板上等に実装した場合、プリント配線板に電源が供給
されても、電源パターンは集積回路パッケージ1上で断
線状態となっているため、集積回路4は動作を行わな
い。すなわちプリント配線板上で動作する必要のある集
積回路に関してのみ、集積回路パッケージ表面層の集積
回路側と集積回路パッケージ側との対応するパッドを電
気的に接続することにより、集積回路を動作させること
ができる。Here, when the integrated circuit package 1 is mounted on a printed wiring board or the like, even if power is supplied to the printed wiring board, the power supply pattern is in a disconnected state on the integrated circuit package 1. 4 does not operate. That is, only for an integrated circuit that needs to operate on the printed wiring board, the integrated circuit is operated by electrically connecting the corresponding pads on the integrated circuit side of the integrated circuit package surface and the integrated circuit package side. You can
【0009】このような構成によると、導電性パッド3
と導電性パッド8とを接続するというように集積回路パ
ッケージ1の表面層の全ての対応する電源を接続するこ
とにより、必要な集積回路について動作可能な状態にす
ることができる。According to this structure, the conductive pad 3
By connecting all corresponding power supplies on the surface layer of the integrated circuit package 1, such as by connecting the conductive pads 8 with the conductive pads 8, the necessary integrated circuits can be put into operation.
【0010】[0010]
【発明の効果】以上説明したように本発明は、集積回路
パッケージの電源供給パターンを途中で分断し、その両
端側を集積回路パッケージ表面のパッドとして設置した
後で接続可能とすることにより、とりあえず動作させる
必要のない集積回路については、動作させないようにす
ることにより、不用な雑音を発生させず、かつ消費電力
を低減し、後で機能追加等で動作させていなかった集積
回路の追加の場合も集積回路パッケージ表面層のパッド
間配線を行うのみで簡単に実施できるという極めて優れ
た効果が得られる。As described above, according to the present invention, the power supply pattern of the integrated circuit package is divided in the middle, and both ends of the pattern are installed as pads on the surface of the integrated circuit package, and then connection is possible. For integrated circuits that do not need to be operated, by not operating them, unnecessary noise is not generated, power consumption is reduced, and additional integrated circuits that have not been operated by adding functions later are added. Also has an extremely excellent effect that it can be easily implemented only by wiring between the pads on the surface layer of the integrated circuit package.
【図1】本発明による集積回路パッケージの一実施例に
よる構成を示す要部拡大斜視図である。FIG. 1 is an enlarged perspective view of essential parts showing a configuration according to an embodiment of an integrated circuit package of the present invention.
1 集積回路パッケージ 2 電源ピン 3 導電性パッド 4 集積回路 5 電源パッド 6 ボンデイング配線 7 導電性パターン 8 導電性パッド 9 信号ピン 1 Integrated Circuit Package 2 Power Pin 3 Conductive Pad 4 Integrated Circuit 5 Power Pad 6 Bonding Wiring 7 Conductive Pattern 8 Conductive Pad 9 Signal Pin
Claims (1)
において、前記集積回路の電源パターンの一端と集積回
路パッケージの電源ピンまたは電源パッドに接続される
電源パターンの一端とを集積回路パッケージの表面に設
け、前記それぞれの電源パターンの一端を集積回路パッ
ケージの表面で接続することにより、集積回路の電源パ
ターンと集積回路パッケージの電源ピンとが電気的に接
続されることを特徴とする集積回路パッケージ。Claim: What is claimed is: 1. In an integrated circuit package containing an integrated circuit, one end of a power supply pattern of the integrated circuit and one end of a power supply pattern connected to a power supply pin or a power supply pad of the integrated circuit package are integrated. The power supply pattern of the integrated circuit and the power supply pin of the integrated circuit package are electrically connected by being provided on the surface of the circuit package and connecting one end of each of the power supply patterns to the surface of the integrated circuit package. Integrated circuit package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20622591A JPH0529372A (en) | 1991-07-24 | 1991-07-24 | Integrated circuit package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20622591A JPH0529372A (en) | 1991-07-24 | 1991-07-24 | Integrated circuit package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0529372A true JPH0529372A (en) | 1993-02-05 |
Family
ID=16519840
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20622591A Pending JPH0529372A (en) | 1991-07-24 | 1991-07-24 | Integrated circuit package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0529372A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7342837B2 (en) | 2005-07-07 | 2008-03-11 | Samsung Electronics Co., Ltd. | Semiconductor memory device |
-
1991
- 1991-07-24 JP JP20622591A patent/JPH0529372A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7342837B2 (en) | 2005-07-07 | 2008-03-11 | Samsung Electronics Co., Ltd. | Semiconductor memory device |
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