JPH05292296A - Thinning processing circuit for picture data - Google Patents

Abstract

PURPOSE:To flexibly cope with the various reduction ratios of the picture data without altering picture processing circuits corresponding to the reduction ratios of the picture data for the thinning processing circuit provided at a facimile equipment to reduce the picture data. CONSTITUTION:At a host CPU 2, the various kinds of mask pattern signals which the reduction ratios of the picture data are variously differentiated are provided, and the optimum mask pattern signal from these is written in a mask register 3 as needed. The mask pattern signal written in the mask register 3 is formed to a read instruction signal by output from a selector 4, and thus, the thinning processing of picture signals is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thinning processing circuit for image data provided in a facsimile machine or the like.

[0002]

2. Description of the Related Art In recent facsimile machines, when the recording paper set in the receiving facsimile machine is smaller than the size of the original document to be transmitted, the image data of the original document is read and scanned at the stage of scanning. Some have a thinning-out processing circuit for image data in order to reduce the size in advance corresponding to the recording paper size. The thinning-out processing circuit forms a reading command signal by thinning out pulses at predetermined intervals in the clock signal, and performs reading scanning in synchronization with the reading command signal, thereby thinning out pixel signals at predetermined intervals. As a result, the image data that has been reduced as a whole is obtained, but the pulse thinning pattern for the clock signal in this case is limited to a predetermined one that reduces the B4 plate to the A4 plate or the B5 plate. It was fixed in ROM.

However, there are various types of reduction ratios of image data other than the standard reduction of B4 size to A4 size. For example, even if the same version number is used, one of them is cut. A subtle reduction ratio is required when the other is roll paper, but in such a case, all thinning patterns corresponding to various reduction ratios are written in the ROM as the pulse thinning pattern for the clock signal. It was troublesome and difficult.

[0004]

SUMMARY OF THE INVENTION An object of the present invention, which has been proposed in view of the above circumstances, is to reduce a wide variety of image data reduction ratios without bothering to write in a ROM, which is troublesome and difficult. Therefore, it is to provide a thinning-out processing circuit of image data which is flexible and easy to handle.

[0005]

In order to achieve the above object, the present invention is proposed in which a mask pattern signal transmitted from the host CPU side is sequentially allocated and stored for each bit according to the reduction rate of image data. And a selector for sequentially and selectively outputting the mask pattern signal stored in the mask register bit by bit in synchronization with the clock signal.

[0006]

The host CPU selects from the various mask pattern signals provided in advance the one having the optimum image data reduction rate, and transmits this to the mask register, and the mask consisting of a plurality of bits. The pattern signal is stored so as to be assigned to each bit of the mask register. From this state, the selector sequentially outputs the mask pattern signal from each bit of the mask register in synchronism with the clock signal, so that the pulses at predetermined intervals in the clock signal are thinned out accordingly. Then, a read command signal is formed, and by scanning the original document for transmission and the like in synchronization with this read command signal, image data with an optimum reduction ratio can be obtained.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a hardware configuration of an image data thinning processing circuit 1 according to the present invention. The thinning-out processing circuit 1 includes a mask register 3 connected to a host CPU 2, a selector 4, a latch circuit 7, and a counter 9.
The 8-bit counter 9 is supplied with the inverted clock signal (clock inversion signal) via the NOT gate 5, and sequentially outputs the count signal for controlling the selector 4. It is composed. Further, the output signal from the selector 4 is input to the NOR gate 6 together with the clock inversion signal from the NOT gate 5, and a read command signal corresponding to the mask pattern is formed here. On the other hand, in the above-mentioned host CPU 2, a mask pattern signal composed of a plurality of bits with different reduction ratios of image data is stored in advance as a program or in an external memory. From the above, the one determined to be optimum according to each set reduction is sent to the mask register 3 together with the write control signal. Each bit is stored so as to be sequentially assigned. When the host CPU 2 selects the predetermined mask pattern signal, it may be determined by a protocol signal exchanged between transmission / reception devices (for example, a facsimile device), or by another method.

FIG. 2 is a time chart showing the basic operation of the thinning processing circuit 1. In this embodiment, both the mask register 3 and the selector 4 are constructed by using 8 bits, and the octal counter 9 is also adapted to repeat counting from 0 to 7. Also, host C
The mask pattern signal written in the mask register 3 by the PU 2 is also 8 bits, and as an example, the pixel signal is masked only at the 8th bit. Therefore, the selector 4
Outputs the mask pattern signal stored in the register 8 one bit at a time every time the counter 9 outputs a count signal based on the clock inversion signal from the knot gate 5. When the count value is 7, Only then, the masking signal is output from the selector 4 to the NOR gate 6. In this way, the control signal of the selector 4 and the clock inversion signal pass through the NOR gate 6,
The masking signal is synchronized with the clock signal to generate a read command signal in which only predetermined pulses of the mask pattern signal are thinned out. The pixel signal as image data transmitted in 8-bit units is Since the read running command signal is input to the latch circuit 7 as a latch pulse,
It is held in 8-bit units and output. Therefore, in the case where such a thinning-out processing circuit is provided, if the pixel signal read scanning is performed in synchronization with the read command signal, the pixel signal (corresponding to D7) for every 8 pulses of the clock signal is changed. Image data thinned out in the NOR gate 6 and reduced as a whole is obtained.

In the embodiment shown as a block diagram in FIG. 3, five mask registers 3A to 3E form a 40
Masking processing can be performed with the pixel signal of a pixel as one unit. 10 is a knot gate. By increasing the number of mask registers in this way, the number of bits forming the mask pattern signal can be similarly increased, whereby the types of mask pattern signals can be further subdivided and the reduction ratio of image data can be finely handled. In FIG. 4A, a 40-bit pixel signal is taken as one unit and 90
Shows an example of the mask pattern signals stored in the mask registers 3A to 3E when performing the reduction processing of 80%, and FIG. 9B shows the mask registers 3A to 3E when performing the reduction processing of 80%. 2 shows an example of the mask pattern signal stored in the above, and in each case, the shaded portion shows the masked portion.

The basic operation of the image data thinning processing circuit shown in FIG. 3 is substantially the same as that shown in FIGS. 1 and 2, so a detailed description thereof will be omitted here, but the mask registers 3A to 3A. The number of 3E is increased, and the selector 9 performs the masking selection operation as shown in the time chart of FIG. That is, the selector 9 first determines the mask register 3
The signal (A) for selecting A is output, and the upper 8 bits (MA) of the 40-bit mask pattern signal transmitted from the host CPU 2 side are bit by bit for each bit of the mask register 3A. Write sequentially while allocating. Then, the signal (B) for selecting the mask register 3B is output, and the next 8 bits in the mask pattern signal are output.
Write bit (MB) to mask register 3B,
Thereafter, similarly, all the remaining bits (MC to ME) of the mask pattern signal are assigned to the mask registers 3C to 3E and written. After the writing of the mask pattern signal is completed in this way, the selector 9 outputs the selection signal (A) again and the mask register 3
After connecting with A, the mask pattern signal is transmitted to the NOR gate 6 bit by bit in synchronization with the count signal from the counter 8.

When the thinning processing circuit 1 of the present invention is provided in a facsimile machine (not shown), the host CPU 2 is provided in a signal processing section (CPU etc.) which the facsimile machine generally has. It may be something like this. In addition, reduction of image data is
Normally, this is performed by the facsimile machine on the transmitting side, but it may be performed by the facsimile machine on the receiving side. Further, not only the number of bits of the mask register 3 and the selector 4, but also the number of bits of the mask pattern signal, the number of mask registers 3, the necessity of the counter 8 as a separate independent form, and various logic gates (5, 6, 7) The combination and the like can be appropriately changed according to the embodiment.

[0012]

As can be understood from the above description, according to the image data thinning-out processing circuit of the present invention, a mask pattern signal for obtaining a wide variety of reduction ratios of image data can be generated as necessary. Since the data is written in the mask register from the host CPU side, a single image circuit can be used for a large number of models without changing the image reduction circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of a thinning processing circuit of the present invention.

FIG. 2 is a time chart showing the basic operation of the thinning processing circuit of the present invention.

FIG. 3 is a block diagram showing a hardware configuration of another embodiment of the thinning-out processing circuit of the present invention.

4A and 4B are time charts showing a register selection operation showing an example of a mask pattern signal stored in the mask register shown in FIG.

[Explanation of symbols]

1 ... Thinning-out processing circuit 2 ... Host CPU 3, 3A to 3
E ... Mask register 4, 9 ... Selector

Claims (1)

[Claims] 1. A host CPU according to a reduction rate of image data
The mask pattern signal transmitted from the side is sequentially assigned to each bit and stored, and the mask pattern signal stored in the mask register is sequentially and selectively output bit by bit in synchronization with the clock signal. An image data thinning processing circuit having a selector.