JPH05291833A - Peak value measurement circuit - Google Patents

Abstract

PURPOSE:To reduce the effect of reduction in a hold voltage by starting A/D conversion according to an A/D conversion start trigger outputted from a peak detection circuit. CONSTITUTION:An output signal VH of a peak hold circuit 1 holding a peak value of an analog input signal Vin is inputted to an A/D converter 2. Moreover, the circuit is provided with a peak detection circuit 3 detecting the peak value of the analog input signal Vin and outputting a start trigger Vsnc of A/D conversion to the A/D converter 2. In this case, a waveform diagram for each section indicates the analog input signal Vin in solid lines, and a difference between an ideal peak hold voltage shown in 2-dashed chain lines and an actual peak hold voltage VH shown in dotted lines is a droop voltage and the measurement result with less error is obtained by implementing the A/D conversion when the droop voltage is small. Then a rectangular pulse signal is the start trigger Vsnc for the A/D conversion and the A/D conversion is started at the leading of the start trigger Vsnc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak value measuring circuit, and more particularly to improvement of a circuit for converting a peak value of an analog input signal into a digital signal.

[0002]

2. Description of the Related Art Peak value measurement is one of the AC signal measuring functions of a digital multimeter. As such an AC signal peak value measuring circuit, a peak hold circuit for holding the peak value of the AC signal and an A / D converter for converting the peak value of the AC signal held by the peak hold circuit into a digital signal It is conceivable that the A / D converter is driven in a free-run mode by a sampling clock that is set independently of the AC signal to be measured.

[0003]

However, in this way,
When the / D converter is driven by free-running, there is a problem that it becomes unclear which peak value is being measured. Further, if the sampling is performed at a time point delayed from the peak position, the hold voltage is lowered (droop), and a correct measurement result cannot be obtained. Then, this effect becomes remarkable when the capacitance of the sample capacitor is reduced in order to make the peak hold circuit compatible with high-speed signals.

The present invention solves such a problem, and an object of the present invention is to realize a peak value measuring circuit which can obtain a measurement result with less influence of a decrease in the hold voltage.

[0005]

In order to solve such a problem, the present invention provides a peak hold circuit for holding a peak value of an analog input signal and an analog input signal held by the peak hold circuit. And a peak detection circuit that detects a peak value of an analog input signal and outputs an A / D conversion start trigger to the A / D converter. And

[0006]

The A / D converter starts A / D conversion according to the A / D conversion start trigger output from the peak detection circuit. As a result, the time delay from the position of the peak value of the A / D conversion start time becomes small, and the measurement result that is less affected by the decrease in the hold voltage can be obtained.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. Figure 1
1 is a peak hold circuit for holding the peak value of the analog input signal V _in , and its output signal V _H
Is input to the A / D converter 2. 3 detects the peak value of the analog input signal V _in , and the A / D converter 2 receives the A / D signal.
It is a peak detection circuit that outputs a conversion start trigger V _snc .

FIG. 2 is a waveform diagram of each part of FIG. In Figure 2
The solid line indicates the analog input signal V _inIs shown. Two
The dotted line shows the ideal peak hold voltage and the dotted line shows the actual peak hold voltage.
Peak hold voltage V_HIs shown. These ideals
Peak hold voltage and actual peak hold voltage V
_HIs the droop voltage, and this droop voltage is small.
A / D conversion is performed at
A fixed result is obtained. The rectangular pulse signal is an A / D conversion star
Trigger V_sncAnd A / D conversion at the rising edge
Is started. Before the droop voltage is generated in the example of FIG.
A / D conversion will be started at
Therefore, the measurement result without error can be obtained.

FIG. 3 shows a concrete example of the peak detection circuit 3 used in FIG. In FIG. 3, the transistor Q1 doubles as a switch and a buffer. Transistors Q _ref and Q _{s rc} constitutes a level shift circuit composed of a current mirror. A1 is a comparator. The analog input signal V _in is input to the base of the transistor Q1 via the resistor R _s, and the emitter of the transistor Q1 is _connected to the power source −V _F via the parallel circuit of the capacitor C _smpl and the resistor R _smpl.
The collector of the transistor Q1 is connected to the collector and the base of the transistor Q _ref and the base of the transistor Q _src via a current limiting resistor R _d for determining one end of the operating point of the transistor Q1. The collectors of the transistors Q _ref and Q _src are connected to the power supply + V, and the collector of the transistor Q _src is the comparator A1.
Is connected to one of the input terminals and is also connected to the ground via the resistor RL. A voltage source that outputs the comparison voltage ΔV is connected to the other input terminal of the comparator A1.

The operation of the circuit of FIG. 3 will be described with reference to the simulation waveform diagram of FIG. 4, □ − □ represents the waveform of the analog input signal V _in , ■ − ■ represents the waveform of the emitter of the transistor Q1, and ◇ − ◇ represents the terminal voltage of the resistor _RL , that is, one input terminal of the comparator A1. The voltage waveform is shown. Then, (a) is an example in which the frequency of the analog input signal V _in is 100 kHz, (b) is an example in which the frequency of the analog input signal V _in is 10 kHz,
(C) is an example _{in which} the frequency of the analog input signal V _in is 1 kHz.

In the circuit of FIG. 3, the capacitor C _smpl holds the voltage of the analog input signal V _in . The voltage _held in the capacitor C _smpl is discharged with a time constant determined by the resistor R _{smpl as} shown by (1)-(4). By inputting a new peak value larger than the voltage currently held, a charging current flows through the transistor Q _ref , and a current proportional to this charging current is generated in the transistor Q _src . The resistor R _{L converts} the charging current to the capacitor C _smpl into a voltage as shown by ◇-◇. The comparator A1 compares the voltage converted by the resistor R _L with the comparison voltage ΔV and outputs the comparison result signal as a peak trigger.

As a result, the peak trigger is output to the A / D converter 2 as the start trigger V _snc near the position of the peak value. However, the circuit of FIG.
_Since the discharge time constant of the capacitor C _smpl , which is determined by _smpl , is fixed, the operable frequency range is limited, and the constants applicable to the frequencies as shown in FIGS. 4 (a) and 4 (b) are as shown in (c). Thus, there arises a problem that the output position of the peak trigger is delayed with respect to the peak value position. The problem that the operable frequency range is limited is
This can be solved by changing the resistance R _smpl to a variable resistance as shown in FIG.

In FIG. 5, a depletion type FET J _dis is provided as a variable resistance element in place of the resistance R _smpl of the circuit of FIG. 3, and an integrating circuit composed of an operational amplifier A2 and its peripheral circuit are provided as its control circuit. And shows the case of positive input. That is, the operational amplifier A2
Is connected to the transistor Q _src and one input terminal of the comparator A1 via the resistor R _L , the non-inverting input terminal of the operational amplifier A2 is connected to the power supply −V _F, and the output terminal of the operational amplifier A2 is J through resistance R _j1
A parallel circuit of a resistor R _i and a capacitor C _i is connected between the inverting input terminal and the output terminal of the operational amplifier A2, which is connected to the gate of _dis . The gate of J _dis is resistor R _j2.
Is connected to the power supply -V _F through the source of the J _dis is connected to the emitter of the transistor Q1, the drain of the J _dis is connected to the power source -V _F via a resistor R _j3.

In the configuration of FIG. 5, the parallel circuit of the operational amplifier A2 and the resistor R _i and the capacitor C _i is the capacitor C.
_Calculate the average value of the voltage proportional to the charging current to _smpl .
J _dis is calculates the discharge current of the capacitor C _smpl amplifier A2
Controlled by the output of. That is, a kind of AGC is formed by the integrating circuit composed of the operational amplifier A2 and its peripheral circuits.
(Automatic gain control) is applied to function as a variable resistor that controls the discharge current of the capacitor C _smpl so that the charge current can be easily detected.

[0015] Figure 6 is an operation simulation waveform diagram of each part of FIG. 5, □ - □ shows a waveform of the analog input signal V _in, ■ - ■ represents the emitter of the waveform of the transistor Q1, ◇ - ◇ is integral 3 shows a generated voltage waveform. (A)
10k is an example of a 100kHz frequency of the analog input signal V _in, the frequency of the (b) is an analog input signal V _in
(C) is an example _{in which} the frequency of the analog input signal V _in is 1 kHz. The upper part of (a) to (c) shows the input voltage waveform of the comparator A1.
The V is set to 700 mV.

According to the structure shown in FIG. 5, the droop plate becomes variable, and the charging current to the capacitor C _{sm pl is made} to flow only _in the vicinity of the peak of the analog input signal V _in , so that the comparison is made even in the low frequency region. A stable trigger output can be obtained. 7 is a modification of the circuit of FIG. 5 so that it can be applied to a negative input, and detailed description thereof will be omitted.

[0017]

As described above, according to the present invention,
It is possible to realize a peak value measurement circuit that can obtain a measurement result that is less affected by a decrease in the hold voltage.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram of each part of FIG.

FIG. 3 is a specific example diagram of a peak detection circuit used in FIG.

FIG. 4 is a waveform diagram of each part of FIG.

5 is another specific example diagram of the peak detection circuit used in FIG. 1. FIG.

FIG. 6 is a waveform diagram of each part of FIG.

7 is another specific example diagram of the peak detection circuit used in FIG. 1. FIG.

[Explanation of symbols]

 1 Peak hold circuit 2 A / D converter 3 Peak detection circuit

Claims (1)

[Claims] 1. A peak hold circuit for holding a peak value of an analog input signal, an A / D converter for converting an analog input signal held by the peak hold circuit into a digital signal, and a peak value of the analog input signal. A peak value detection circuit which detects and outputs an A / D conversion start trigger to the A / D converter.