JPH0529149B2 - - Google Patents
Info
- Publication number
- JPH0529149B2 JPH0529149B2 JP61260941A JP26094186A JPH0529149B2 JP H0529149 B2 JPH0529149 B2 JP H0529149B2 JP 61260941 A JP61260941 A JP 61260941A JP 26094186 A JP26094186 A JP 26094186A JP H0529149 B2 JPH0529149 B2 JP H0529149B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- region
- film
- present
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 description 21
- 239000012535 impurity Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- -1 boron ions Chemical class 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】
（概 要〕
本発明は、ゲート電極を形成した後に該ゲート
電極の上方から不純物イオンを打ち込むことによ
り、バツクチヤネル防止用の不純物領域を形成す
ることを特徴とする。Detailed Description of the Invention (Summary) The present invention is characterized in that after forming a gate electrode, impurity ions are implanted from above the gate electrode to form an impurity region for preventing backchannels.
本発明によればゲート電極の厚みを利用するこ
とにより該ゲート電極の下方の絶縁膜／半導体層
の界面付近にのみ不純物領域を形成することがで
きるので、特別のマスクを必要としないで高耐圧
のSOI／MOSFETを容易に製造することができ
る。 According to the present invention, by utilizing the thickness of the gate electrode, it is possible to form an impurity region only near the interface between the insulating film and the semiconductor layer below the gate electrode. SOI/MOSFET can be easily manufactured.
本発明は半導体装置の製造方法に関するもので
あり、更に詳しく言えば高耐圧のSOI／
MOSFETを形成する半導体装置の製造方法に関
するものである。
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a semiconductor device forming a MOSFET.
第２図は従来の製造方法を説明するSOI／
MOSFETの断面図である。１はSi基板、２は
SiO2膜、３は多結晶Si層を再結晶化したｐ型Si
層、４はソース領域、５はドレイン領域、６はオ
フセツト領域に形成された低濃度領域、７はゲー
ト酸化膜、８はゲート電極である。また９はソー
ス・ドレイン間のリーク電流の原因となるバツク
チヤネルを防止するために、ゲート電極８の下方
でSi／SiO2の界面近くに形成された高濃度のｐ
型領域である。
Figure 2 shows SOI/
FIG. 3 is a cross-sectional view of a MOSFET. 1 is Si substrate, 2 is
SiO 2 film, 3 is p-type Si obtained by recrystallizing polycrystalline Si layer
4 is a source region, 5 is a drain region, 6 is a low concentration region formed in an offset region, 7 is a gate oxide film, and 8 is a gate electrode. In addition, 9 is a high-concentration p-oxide layer formed near the Si/SiO 2 interface below the gate electrode 8 to prevent back channels that cause leakage current between the source and drain.
It is a type area.
ところで従来例の製造方法によれば、高濃度の
ｐ型領域９は、ｐ型Si層３の上方から、例えばボ
ロンイオン（B+）を打ち込むことによつて形成
されるが、打ち込む位置が深いため、ゲート電極
８の下方に正確に形成することが難しい。
By the way, according to the conventional manufacturing method, the highly doped p-type region 9 is formed by implanting, for example, boron ions (B + ) from above the p-type Si layer 3, but the implantation position is deep. Therefore, it is difficult to form it accurately below the gate electrode 8.
このためバツクチヤネルによるリーク電流を十
分に抑えることができなかつたり、あるいはｐ型
領域９がドレイン領域５や低濃度領域６に接近し
てこれらの領域との間でｐ−ｎ接合が形成されて
耐圧が低くなる場合がある。 For this reason, the leakage current due to the back channel cannot be suppressed sufficiently, or the p-type region 9 approaches the drain region 5 and the low concentration region 6, and a p-n junction is formed between these regions, resulting in a breakdown voltage. may be lower.
本発明はかかる従来の問題点に鑑みて創作され
たものであり、バツクチヤネルの確実な防止を可
能とする高耐圧のSOI／MOSFETを形成する半
導体装置の製造方法の提供を目的とする。 The present invention was created in view of such conventional problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device forming a high-voltage SOI/MOSFET that can reliably prevent back channels.
本発明の半導体装置の製造方法は、絶縁膜上に
一導電型の多結晶又は非晶質の半導体層を形成す
る工程と、前記半導体層を再結晶化する工程と、
前記再結晶化半導体層をパターニングして該半導
体層を各MOSFET形成領域に分離する工程と、
分離された再結晶化半導体層の表面にゲート酸化
膜を形成する工程と、前記ゲート酸化膜上にゲー
ト電極を形成する工程と、前記ゲート電極の上方
から一導電型の不純物イオンを打ち込み、該ゲー
ト電極の下方で前記絶縁膜と前記半導体層の界面
付近に高濃度の一導電型の不純物領域を形成する
工程と、前記半導体層にソース・ドレイン領域を
形成する工程とを有することを特徴とする。
The method for manufacturing a semiconductor device of the present invention includes a step of forming a polycrystalline or amorphous semiconductor layer of one conductivity type on an insulating film, a step of recrystallizing the semiconductor layer,
patterning the recrystallized semiconductor layer to separate the semiconductor layer into MOSFET formation regions;
A step of forming a gate oxide film on the surface of the separated recrystallized semiconductor layer, a step of forming a gate electrode on the gate oxide film, and a step of implanting impurity ions of one conductivity type from above the gate electrode. The method comprises the steps of: forming a highly concentrated impurity region of one conductivity type near the interface between the insulating film and the semiconductor layer below the gate electrode; and forming a source/drain region in the semiconductor layer. do.
前記ゲート電極の上方から打ち込む不純物イオ
ンのエネルギーを、該ゲート電極の存在する領域
を透過して注入された不純物イオンが半導体層／
絶縁膜の界面付近に留まるように調節しておく。
このときゲート電極の存在しない領域を介して注
入された不純物イオンは、半導体層／絶縁膜の界
面を超えて絶縁膜中に注入される。
The energy of impurity ions implanted from above the gate electrode is transmitted through the region where the gate electrode is present, and the implanted impurity ions form a semiconductor layer/
Adjust so that it remains near the interface of the insulating film.
At this time, the impurity ions implanted through the region where the gate electrode does not exist are implanted into the insulating film beyond the semiconductor layer/insulating film interface.
このようにして、ゲート電極の下方のみに自己
整合的に不純物イオンを注入することができるの
で、バツクチヤネル防止用の高濃度の不純物領域
を所定の位置に確実に形成することができる。 In this way, impurity ions can be implanted only under the gate electrode in a self-aligned manner, so that a high concentration impurity region for back channel prevention can be reliably formed at a predetermined position.
次に図を参照しながら本発明の実施例について
説明する。第１図は本発明の実施例に係る半導体
装置の製造方法を説明する図である。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
(1) まずSi基板１０の上に膜厚1μmのSiO2膜１１
を形成した後に0.4μmのボロンドープの多結晶
Si層１２を減圧CVD法で形成する（同図ａ）。(1) First, a SiO 2 film 11 with a thickness of 1 μm is placed on the Si substrate 10.
0.4μm boron-doped polycrystal after forming
The Si layer 12 is formed by a low pressure CVD method (FIG. 1a).
(2) 次いでレーザ光を多結晶Si層１２に照射して
溶融し、再結晶化してｐ型Si層１３を形成す
る。その後該ｐ型Si層１３をパターニングして
各MOSFET形成領域分離する（同図ｂ）。な
お以下の図においては、Si基板１０は省略して
いる。(2) Next, the polycrystalline Si layer 12 is irradiated with laser light to melt and recrystallize to form the p-type Si layer 13. Thereafter, the p-type Si layer 13 is patterned to separate each MOSFET formation region (FIG. 2(b)). Note that the Si substrate 10 is omitted in the following figures.
(3) 同図ｃに示すように、ｐ型Si層１３を酸化し
て膜厚500ÅのゲートSiO2膜１４を形成する。(3) As shown in Figure c, the p-type Si layer 13 is oxidized to form a gate SiO 2 film 14 with a thickness of 500 Å.
(4) 次いで同図ｄに示すように、膜厚0.4μmの多
結晶Si膜を全面に形成した後にパターニングし
てゲート電極１５を形成する。このときオフセ
ツト型にするため、ゲートSiO2膜１４上の多
結晶Si膜の一部は除去されている。(4) Next, as shown in Figure d, a polycrystalline Si film with a thickness of 0.4 μm is formed on the entire surface and then patterned to form the gate electrode 15. At this time, a part of the polycrystalline Si film on the gate SiO 2 film 14 is removed to make it an offset type.
(5) 次に同図ｅに示すように、上方からダブルチ
ヤージのボロンイオン（B+）を180KeV、１×
1012／cm2で注入する。このときRPはほぼ
0.8μm、△RPは0.1μmである。これによりボロ
ンイオンはゲート電極の下方のSi／SiO2界面
付近に注入される。一方、ゲート電極１５の領
域以外に打ち込まれたボロンイオンはSi／
SiO2界面を透過してSiO2膜１１中に注入され
る。(5) Next, as shown in figure e, double-charge boron ions (B + ) are applied from above at 180 KeV, 1×
Inject at 10 12 /cm 2 . At this time, R P is approximately
0.8 μm, ΔR P is 0.1 μm. As a result, boron ions are implanted near the Si/SiO 2 interface below the gate electrode. On the other hand, boron ions implanted in areas other than the gate electrode 15 are Si/
It is injected into the SiO 2 film 11 through the SiO 2 interface.
(6) この後、同図ｆに示すように、ソース・ドレ
イン形成用のイオン等を注入した後、熱処理を
施すことにより各注入イオンを活性化してｐ型
領域１６、ソース・ドレイン領域１７，１８お
よび低濃度領域１９を形成する。このようにし
て所定の高耐圧のSOI／MOSFETが形成され
る。(6) After this, as shown in FIG. 18 and a low concentration region 19 are formed. In this way, a predetermined high breakdown voltage SOI/MOSFET is formed.
以上説明したように、本発明の実施例によれば
自己整合的にゲート電極１５の下方のみにｐ型領
域１６を形成することができるので、該ｐ型領域
１６がドレイン領域１８や低濃度領域１９に接近
しすぎてｐ−ｎ接合が形成され耐圧が低下するこ
ともない。 As explained above, according to the embodiment of the present invention, the p-type region 16 can be formed only under the gate electrode 15 in a self-aligned manner, so that the p-type region 16 can be formed in the drain region 18 or in the low concentration region. 19, a pn junction will be formed and the withstand voltage will not be lowered.
またｐ型領域１９はゲート電極１５を利用して
自己整合的に形成されるので、特別のマスクを必
要としない。 Furthermore, since p-type region 19 is formed in a self-aligned manner using gate electrode 15, no special mask is required.
なお実施例ではｎチヤネルMOSFETについて
説明したが、ｐチヤネルMOSFETについても適
用できることは明らかである。 In the embodiment, an n-channel MOSFET has been described, but it is clear that the present invention can also be applied to a p-channel MOSFET.
以上説明したように、本発明によればバツクチ
ヤネルによるリーク電流防止用の不純物領域を自
己整合的にゲート電極の下方に確実に形成するこ
とができるので、高性能で高耐圧のSOI／
MOSFETの製造が容易となる。
As explained above, according to the present invention, an impurity region for preventing leakage current due to back channels can be reliably formed below the gate electrode in a self-aligned manner.
It becomes easier to manufacture MOSFETs.
第１図は本発明の実施例に係る半導体装置の製
造方法を説明する断面図、第２図は従来例に係る
半導体装置の製造方法を説明する断面図である。
（符号の説明） １，１０…Si基板、２，１１
…SiO2膜、３，１３…ｐ型Si層、４，１７…ソ
ース領域、５，１８…ドレイン領域、６，１９…
低濃度領域、７，１４…ゲートSiO2膜、８，１
５…ゲート電極、９，１６…中間濃度領域、１２
…ボロンドープ多結晶Si層。
FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example. (Explanation of symbols) 1, 10...Si substrate, 2, 11
...SiO 2 film, 3,13...p-type Si layer, 4,17...source region, 5,18...drain region, 6,19...
Low concentration region, 7, 14... Gate SiO 2 film, 8, 1
5... Gate electrode, 9, 16... Intermediate concentration region, 12
...Boron-doped polycrystalline Si layer.
１ 半導体基板上に少なくとも浮遊ゲートと制御
ゲートとが積み重ねられて構成されるスタツクト
ゲート構造部を有する紫外線消去型不揮発性メモ
リセルと、
前記スタツクトゲート構造部を覆うように形成
され、紫外線が透過するようにリンを含む第１の
二酸化シリコン膜と、
少なくとも前記スタツクトゲート構造部の側壁
上に前記第１の二酸化シリコン膜を介して形成さ
れ、前記スタツクトゲート部により生ずる段差を
緩和するように構成された、前記第１の二酸化シ
リコン膜よりも融点が低くなるようにボロンおよ
びリンを含む第２の二酸化シリコン膜と
を具備したことを特徴とする半導体装置。
1. An ultraviolet erasable nonvolatile memory cell having a stacked gate structure formed by stacking at least a floating gate and a control gate on a semiconductor substrate; a first silicon dioxide film containing phosphorus so as to be transparent; and a first silicon dioxide film formed on at least a side wall of the stacked gate structure via the first silicon dioxide film to alleviate a step difference caused by the stacked gate structure. 1. A semiconductor device comprising: a second silicon dioxide film containing boron and phosphorus so as to have a melting point lower than that of the first silicon dioxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26094186A JPS63114266A (en) | 1986-10-31 | 1986-10-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26094186A JPS63114266A (en) | 1986-10-31 | 1986-10-31 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63114266A JPS63114266A (en) | 1988-05-19 |
| JPH0529149B2 true JPH0529149B2 (en) | 1993-04-28 |
Family
ID=17354904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26094186A Granted JPS63114266A (en) | 1986-10-31 | 1986-10-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63114266A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4950618A (en) * | 1989-04-14 | 1990-08-21 | Texas Instruments, Incorporated | Masking scheme for silicon dioxide mesa formation |
| JP2782781B2 (en) * | 1989-05-20 | 1998-08-06 | 富士通株式会社 | Method for manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126914A (en) * | 1980-03-11 | 1981-10-05 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1986
- 1986-10-31 JP JP26094186A patent/JPS63114266A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126914A (en) * | 1980-03-11 | 1981-10-05 | Fujitsu Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63114266A (en) | 1988-05-19 |
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