JPH05291384A - Electrostatic attraction method - Google Patents

Electrostatic attraction method

Info

Publication number
JPH05291384A
JPH05291384A JP9134792A JP9134792A JPH05291384A JP H05291384 A JPH05291384 A JP H05291384A JP 9134792 A JP9134792 A JP 9134792A JP 9134792 A JP9134792 A JP 9134792A JP H05291384 A JPH05291384 A JP H05291384A
Authority
JP
Japan
Prior art keywords
wafer
voltage
plasma
electrodes
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9134792A
Other languages
Japanese (ja)
Inventor
Masaya Kobayashi
雅哉 小林
Toshimasa Kisa
俊正 木佐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9134792A priority Critical patent/JPH05291384A/en
Publication of JPH05291384A publication Critical patent/JPH05291384A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To provide an electrostatic attraction method by which a strong attracting force is uniformly obtained throughout the entire surface of a wafer even in plasma; the wafer temperature is evened: the wafer is completely chucked before/after plasma processing; and the wafer is easily removed. CONSTITUTION:An electrostatic attraction apparatus which sucks a wafer onto a flat plate insulator by applying positive and negative voltages to a pair of electrodes, respectively, embeded in the insulator and isolated from each other. For use in plasma processing, the electrostatic attraction apparatus is constituted as follows: negative voltage is changed into positive voltage during plasma processing (t3-t8) so that positive voltage is applied to both electrodes; the original state that positive and negative voltages are applied to a pair of electrodes, respectively, is restored just before the completion (t6-t7) of the plasma processing.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は主として半導体製造装置
に用いられる静電吸着方法に関する。半導体装置の製造
に用いられるドライエッチング装置等のプラズマプロセ
ス装置においては、被処理基板(以下ウエーハと呼ぶ)
の固定に静電吸着装置(以下静電チャックと呼ぶ)が多
く使用されるが、この静電チャックにはプラズマ中にお
いても全面にわたって均一な密着性が得られてウエーハ
温度の均一性が保て、且つプラズマ処理終了後のウエー
ハの取外しが容易なことが望まれる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic attraction method mainly used in semiconductor manufacturing equipment. In a plasma processing apparatus such as a dry etching apparatus used for manufacturing a semiconductor device, a substrate to be processed (hereinafter referred to as a wafer)
An electrostatic chuck (hereinafter referred to as an electrostatic chuck) is often used to fix the wafer, but this electrostatic chuck can provide uniform adhesion over the entire surface even in plasma, and keep the wafer temperature uniform. Moreover, it is desired that the wafer can be easily removed after the plasma treatment.

【0002】[0002]

【従来の技術】ドライエッチング装置等のプラズマプロ
セス装置のステージに用いる従来の静電チャックは、平
板状の絶縁物内に埋め込まれた電極に正の電圧を印加し
てウエーハ吸着させる1極式のものと、電極が1対にな
っていてそれぞれの電極に正と負の異なる電圧を印加し
てウエーハを吸着させる2極式のものとがある。
2. Description of the Related Art A conventional electrostatic chuck used for a stage of a plasma processing apparatus such as a dry etching apparatus is a one-pole type electrostatic chuck that applies a positive voltage to an electrode embedded in a flat plate-shaped insulator to adsorb a wafer. There are two types, one is a pair of electrodes and the other is a two-pole type in which positive and negative different voltages are applied to the respective electrodes to adsorb the wafer.

【0003】図8は1極式静電チャックによる従来の静
電吸着方法を示す図で、(a) はウエーハを設置(プラズ
マなし)する場合、(b) プラズマ中での場合をそれぞれ
表し、図中の符号における、1は半導体ウエーハ、2は
チャック電極、3はチャック誘電体(絶縁物)、4はD
C電源、5はプラズマ、G1及びG2は接地、CUはプラズマ
からの荷電粒子によりチャージアップされた負電荷を示
している。
FIG. 8 is a diagram showing a conventional electrostatic attraction method using a one-pole type electrostatic chuck. (A) shows a case where a wafer is installed (without plasma) and (b) shows a case where it is in plasma, In the figure, 1 is a semiconductor wafer, 2 is a chuck electrode, 3 is a chuck dielectric (insulator), 4 is D.
C power source, 5 is plasma, G 1 and G 2 are ground, and CU is negative charge charged up by charged particles from the plasma.

【0004】この1極式の静電チャックにおいては、図
(a) に符号G1で示すように被吸着物である半導体ウエー
ハ1を接地しないと吸着されない。プラズマエッチング
装置等に用いる場合には、ウエーハを浮遊電位にしなけ
れば処理ができないので、実際にウエーハ1を接地G1
ることはできず、そのためこの状態での吸着力は得られ
ない。しかし、エッチング中では図(b) に示すように、
プラズマからの荷電粒子により符号UCで示すようにウエ
ーハ1が負にバイアスされるため、ウエーハを接地しな
くても吸着力が得られる。
In this one-pole type electrostatic chuck,
As indicated by reference numeral G 1 in (a), the semiconductor wafer 1 which is the object to be adsorbed is not adsorbed unless it is grounded. When used in a plasma etching apparatus or the like, the wafer cannot be processed unless it is brought to a floating potential, so that the wafer 1 cannot actually be grounded G 1 and therefore the suction force in this state cannot be obtained. However, during etching, as shown in Figure (b),
Since the wafer 1 is negatively biased by the charged particles from the plasma as indicated by the symbol UC, the attraction force can be obtained without grounding the wafer.

【0005】図9は2極式の静電チャックによる従来の
静電吸着方法を示す図で、図中の符号における、2A、2B
は1対のチャック電極、PC1 及びPC2 は分極された電荷
を示し、その他の符号は図8と同一対象物を示してい
る。
FIG. 9 is a diagram showing a conventional electrostatic attraction method using a two-pole type electrostatic chuck. Reference numerals 2A and 2B in FIG.
Indicates a pair of chuck electrodes, PC 1 and PC 2 indicate polarized charges, and other symbols indicate the same objects as in FIG.

【0006】この2極式の静電チャックにおいては、1
対のチャック電極2Aと2Bに極性の異なる正電圧と負電圧
をそれぞれ印加してウエーハ1を吸着させる。そのため
に図示のようにウエーハ1がウエーハ1が浮遊電位の状
態で吸着力が得られる特徴がある。
In this two-pole type electrostatic chuck, 1
A positive voltage and a negative voltage having different polarities are applied to the pair of chuck electrodes 2A and 2B, respectively, to attract the wafer 1. Therefore, as shown in the figure, the wafer 1 has a characteristic that an attracting force can be obtained when the wafer 1 is at a floating potential.

【0007】[0007]

【発明が解決しようとする課題】前記のように1極式の
静電チャックは、プラズマ中でないと吸着力が働かな
い。よってプラズマが発生していないウエーハ処理の前
後でチャック上でのウエーハの位置ずれが生じ易く、ウ
エーハの搬送等に支障を来す。また、プラズマ中で過剰
の電子がウエーハに蓄積されるため、チャックをオフ(O
FF) しても残留吸着力が強く、ウエーハを無理に引き剥
がそうとすると、ウエーハが破損したり、またウエーハ
が飛び跳ねて位置ずれを生ずる等の問題があった。
As described above, in the one-pole type electrostatic chuck, the attraction force does not work unless it is in plasma. Therefore, the wafer is likely to be displaced on the chuck before and after the wafer processing in which plasma is not generated, which hinders the transportation of the wafer. In addition, since excess electrons are accumulated on the wafer in the plasma, the chuck is turned off (O
(FF) Even if the wafer is forcibly peeled off due to the strong residual adsorption force, there were problems such as damage to the wafer and jumping of the wafer, resulting in misalignment.

【0008】また前記のような2極式の静電チャック
は、これをプラズマ装置に用いると、図8及び図9と同
符号を用いた図10に示すように、プラズマ5処理中にウ
エーハに印加される負(−)のバイアス電圧(CU)のため
に、チャックの負電極2A上ではウエーハ1に斥力(F1 )
が働いてしまう。そのため、負電極2A上ではウエーハ1
が浮き上がる状態になってウエーハ1とチャック間の熱
伝導が負電極2A上と正電極2B上で異なり、ウエーハ1上
で大きな温度分布を生ずるという問題があった。 (F2は吸引力)そこで本発明は、プラズマ中においても
ウエーハ全面にわたつて一様に強い吸着力が得られてウ
エーハ温度の均一化が図れ、且つプラズマ処理前後の固
着も完全になされ、更にウエーハの取外しが容易な静電
吸着方法を提供することを目的とする。
When the bipolar electrostatic chuck as described above is used in a plasma device, as shown in FIG. 10 using the same reference numerals as those in FIGS. 8 and 9, the electrostatic chuck is applied to a wafer during plasma 5 treatment. Due to the negative (−) bias voltage (CU) applied, the repulsive force (F 1 ) is applied to the wafer 1 on the negative electrode 2A of the chuck.
Will work. Therefore, on the negative electrode 2A, the wafer 1
However, there is a problem in that the heat conduction between the wafer 1 and the chuck is different between the negative electrode 2A and the positive electrode 2B due to the floating state, resulting in a large temperature distribution on the wafer 1. (F 2 is a suction force) Therefore, in the present invention, even in plasma, a strong adsorption force is uniformly obtained over the entire surface of the wafer, the temperature of the wafer can be made uniform, and the adhesion before and after the plasma treatment is completely performed. It is another object of the present invention to provide an electrostatic adsorption method in which a wafer can be easily removed.

【0009】[0009]

【課題を解決するための手段】上記課題の解決は、平板
状の絶縁物中に埋め込まれ分離されている対の電極に正
電圧と負電圧をそれぞれ印加して該絶縁物上に被処理基
板を吸着させる静電吸着装置をプラズマ処理に用いるに
際して、プラズマ処理中は前記負電圧を正電圧に切り換
えて総ての電極に正電圧を印加する本発明による静電吸
着方法、若しくは、前記プラズマ処理が終了する直前
に、該対の電極に正電圧と負電圧がそれぞれ印加される
元の状態に復帰せしめる工程を含む本発明による静電吸
着方法によって達成される。
To solve the above problems, a positive voltage and a negative voltage are applied to a pair of electrodes embedded in and separated from a plate-shaped insulator to form a substrate to be processed on the insulator. When an electrostatic adsorption device for adsorbing is used in plasma processing, the negative voltage is switched to a positive voltage during plasma processing to apply a positive voltage to all electrodes, or the plasma processing Immediately before the end of, the electrostatic attraction method according to the present invention includes a step of returning to the original state in which a positive voltage and a negative voltage are applied to the electrodes of the pair.

【0010】[0010]

【作用】図1は本発明の原理説明図で、チャック電圧印
加方法のタイムチャート図である。図中の、t1はウエー
ハ搭載時、t2はA電極及びB電極への吸着電圧印加時、
t3はプラズマ処理開始時、t4はB電極の電圧反転開始
時、t5はB電極の電圧反転完了時、t6はB電極の電圧復
旧開始時、t7はB電極の電圧復旧完了時、t8はプラズマ
処理終了時、t9はA電極及びB電極への電圧印加停止
時、t10 はウエーハ離脱時、τ1 は電圧立ち上がり時
間、τ2 は電圧立ち下がり時間、Tはプラズマ処理時間
を示す。
FIG. 1 is a diagram for explaining the principle of the present invention, which is a time chart of the chuck voltage application method. In the figure, t 1 is when the wafer is mounted, t 2 is when the adsorption voltage is applied to the A electrode and the B electrode,
t 3 is the start of plasma processing, t 4 is the start of voltage inversion of the B electrode, t 5 is the completion of voltage inversion of the B electrode, t 6 is the start of voltage recovery of the B electrode, and t 7 is the recovery of voltage of the B electrode Where t 8 is the end of the plasma treatment, t 9 is the stop of the voltage application to the A and B electrodes, t 10 is the separation of the wafer, τ 1 is the voltage rise time, τ 2 is the voltage fall time, and T is the plasma. Indicates the processing time.

【0011】本発明においては従来同様の構造を有する
2極式静電チャックを用いる。そして本発明によれば、
静電チャック上にウエーハを搭載し(t1)、最初は対の電
極の例えばA電極に正(+)の電圧をB電極に負(−)
の電圧をそれぞれ印加して前記ウエーハを強固に吸着固
定させる(t2)。次いでウエーハにプラズマを印加してプ
ラズマ処理が行われている間(t3 〜t8) 即ちTは、A,
Bの2電極に共に正(+)電圧を印加する。これにより
プラズマ中より負(−)電荷が供給され負(−)電位に
帯電するウエーハは2電極から同様に吸着力を受け、ウ
エーハの全面が均一な吸着力を受けて静電チャック上に
固着される。従ってウエーハ全面からの静電チャックに
向かう熱伝導が均一化されるので、プラズマ処理中にお
けるウエーハ面内の温度分布が均一化される。
In the present invention, a bipolar electrostatic chuck having the same structure as the conventional one is used. And according to the invention,
A wafer is mounted on the electrostatic chuck (t 1 ), and a positive (+) voltage is applied to the pair of electrodes, for example, the A electrode, and a negative (−) voltage is applied to the B electrode.
Voltage is applied to firmly adsorb and fix the wafer (t 2 ). Next, while plasma is applied to the wafer and plasma processing is being performed (t 3 to t 8 ), that is, T is A,
A positive (+) voltage is applied to both B electrodes. As a result, a negative (-) charge is supplied from the plasma and the wafer charged to a negative (-) potential is similarly attracted by the two electrodes, and the entire surface of the wafer is uniformly attracted and fixed on the electrostatic chuck. To be done. Therefore, the heat conduction from the entire surface of the wafer toward the electrostatic chuck is made uniform, so that the temperature distribution in the wafer surface during the plasma processing is made uniform.

【0012】また、プラズマ処理終了時(t8)直前(t7)に
おいて再び2電極に正(+)と負(−)の異なる極性の
電圧を印加する元の状態に復帰させることで、ウエーハ
内に過剰に蓄積していた負(−)電荷をプラズマ中に逃
がすことができるため、ウエーハ離脱時t10 の残留吸着
力を小さくすることができてウエーハの取外しが容易に
なり、且つプラズマ処理中(t3 〜t8) 以外は2電極に正
(+)と負(−)の電圧が印加されているため、プラズ
マ中でなくても静電チャックが吸着力を失わす、位置ず
れを生ずることがない。
Further, immediately before the plasma processing is completed (t 8 ) (t 7 ), the two electrodes are restored to the original state in which voltages having different polarities of positive (+) and negative (−) are applied again, and the wafer is restored. negative which has been excessively accumulated within (-) because it can escape the charge to the plasma, wafer removed and it is possible to reduce the residual adsorption force of the wafer leaving time t 10 becomes easy, and the plasma treatment Positive (+) and negative (-) voltages are applied to the two electrodes except for medium (t 3 to t 8 ), so the electrostatic chuck loses its attractive force even when it is not in plasma. It never happens.

【0013】なお、電極電圧の極性の切替え時には、急
峻な変化を与えるとウエーハ上に形成されているデバイ
スの電位が瞬間的に変化してデバイス内に電流が流れて
ダメージを与えてしまう。そこで本発明においては、極
性の切替え時に所定の傾斜を有する電圧の立ち上がり時
間τ1 及び立ち下がり時間τ2 を設けてウエーハ上のデ
バイスに及ぼされるダメージを防止することが更に望ま
しい。
When the polarity of the electrode voltage is switched, if a sharp change is applied, the potential of the device formed on the wafer will change instantaneously and a current will flow in the device, causing damage. Therefore, in the present invention, it is more desirable to prevent the damage on the device on the wafer by providing the rising time τ 1 and the falling time τ 2 of the voltage having a predetermined slope when switching the polarities.

【0014】[0014]

【実施例】以下本発明を、図示実施例により具体的に説
明する。図2は本発明の一実施例に用いたリアクティブ
イオンエッチング(RIE) 装置の模式図、図3は同実施例
における基板ステージ部の模式図、図4は同実施例にお
ける静電チャックの模式図、図5は同実施例におけるチ
ャック電圧印加方法のタイムチャート図、図6は同実施
例における被処理ウエーハの面内温度分布図、図7は従
来の方法における被処理ウエーハの面内温度分布図であ
る。全図を通じ同一対象物は同一符合で示す。
EXAMPLES The present invention will be described in detail below with reference to illustrated examples. 2 is a schematic diagram of a reactive ion etching (RIE) apparatus used in one embodiment of the present invention, FIG. 3 is a schematic diagram of a substrate stage section in the same embodiment, and FIG. 4 is a schematic diagram of an electrostatic chuck in the same embodiment. 5, FIG. 5 is a time chart diagram of the chuck voltage application method in the same embodiment, FIG. 6 is an in-plane temperature distribution diagram of the processed wafer in the same example, and FIG. 7 is an in-plane temperature distribution of the processed wafer in the conventional method. It is a figure. The same object is denoted by the same reference numeral throughout the drawings.

【0015】本発明の一実施例に用いたRIE 装置は、図
2に示すように、静電チャック6にSiウエーハ1を吸着
させて保持し、マスフローコントローラ7を通してガス
導入口8から一定量の例えばアルゴン(Ar)ガスを処理室
9内に導入し、高周波(rf)電源10によりrf電極11にrf電
力を供給し、処理室9内にArプラズマ5を発生させ、そ
の時の温度を赤外線透過窓12を通し赤外線カメラaと本
体bからなる赤外線温度計13により測定するように構成
され、更に、静電チャック6にはDC電源4を具備せし
め、このDC電源4と静電チャック6の電極2A、2Bとの
間には極性切り換え手段14を介在させて構成される。
As shown in FIG. 2, the RIE apparatus used in one embodiment of the present invention attracts and holds the Si wafer 1 on the electrostatic chuck 6, and a fixed amount of the Si wafer 1 is supplied from the gas introduction port 8 through the mass flow controller 7. For example, argon (Ar) gas is introduced into the processing chamber 9, rf power is supplied to the rf electrode 11 by a high frequency (rf) power source 10, Ar plasma 5 is generated in the processing chamber 9, and the temperature at that time is transmitted through infrared rays. An infrared thermometer 13 including an infrared camera a and a main body b is used for measurement through a window 12, and further, an electrostatic chuck 6 is equipped with a DC power source 4, and electrodes of the DC power source 4 and the electrostatic chuck 6 are provided. A polarity switching means 14 is interposed between 2A and 2B.

【0016】また、図3は上記RIE 装置における静電チ
ャック配設部即ち基板ステージ部の模式断面図で、(a)
はウエーハ吸着時、(b) はウエーハ離脱時をそれぞれ表
しており、図中の、1はSiウエーハ、6は静電チャッ
ク、11はrf電極、15はイジエクトピン突出口、16はイジ
エクトピン、17は絶縁物を示し、静電チャック6内のイ
ジエクトピン突出口15からイジエクトピン16が突出する
ことにより静電チャック6からウエーハ1が離脱せしめ
られるようになっている。
FIG. 3 is a schematic cross-sectional view of the electrostatic chuck arrangement portion, that is, the substrate stage portion in the above RIE apparatus.
Shows when the wafer is adsorbed and (b) shows when the wafer is detached. In the figure, 1 is a Si wafer, 6 is an electrostatic chuck, 11 is an rf electrode, 15 is an eject pin projecting hole, 16 is an eject pin, and 17 is an eject pin. An insulator is shown, and the eject pin 16 projects from the eject pin projecting port 15 in the electrostatic chuck 6 so that the wafer 1 can be detached from the electrostatic chuck 6.

【0017】また、図4は同実施例に用いた静電チャッ
クの模式図で、(a) は平面図、(b)は断面図を表してお
り、図中の、2A、2BはCu製のチャック電極、3はチャッ
ク誘電体、15はイジェクトピン突出口、18はAl製台座を
示す。
4A and 4B are schematic views of the electrostatic chuck used in the embodiment, where FIG. 4A is a plan view and FIG. 4B is a sectional view, in which 2A and 2B are made of Cu. Of the chuck electrode, 3 is a chuck dielectric, 15 is an eject pin protruding port, and 18 is an Al pedestal.

【0018】この静電チャック6のチャック誘電体3は
アルミナセラミックス製で厚さ 0.5mmである。極性の異
なる対のA電極2AとB電極2Bは、同心円状に交互に配置
されている。
The chuck dielectric 3 of the electrostatic chuck 6 is made of alumina ceramics and has a thickness of 0.5 mm. The pair of A electrodes 2A and B electrodes 2B having different polarities are alternately arranged concentrically.

【0019】このような構成のもとで、本実施例におい
ては、図5に示すタイムチャートに従って静電チャック
6にチャック電圧を印加しながらSiウエーハ1面のプラ
ズマ処理を行った。
With this structure, in the present embodiment, the plasma treatment of one surface of the Si wafer was performed while applying the chuck voltage to the electrostatic chuck 6 according to the time chart shown in FIG.

【0020】即ち、静電チャック6上にt1においてウエ
ーハ1を搭載し、最初にt2において例えばA電極2Aに+
500V、B電極2Bに−500Vの直流電圧を印加してウエーハ
1を吸着する。次いでt3においてrf電極11に、13.56MH
z、300Wの高周波電力を印加させプラズマ5を発生させ
た後、t4〜t5において例えばB電極2Bの電圧を+500Vに
変化させる。この状態でSiウエーハ1はプラズマ5によ
って与えられる負(−)のバイアス電圧により全ての電
極に+500Vが印加されている静電チャック6上に均一に
吸着されている。そして、プラズマ処理終了直前のt6
t7においてB電極2Bの電圧を−500Vに戻した後、t8にお
いてrfパワーを切断しプラズマ処理を終了する。その
後、t9〜t10 においてA電極2A及びB電極2Bを0Vに
し、ウエーハ1をチャック6上から離脱させる。
That is, the wafer 1 is mounted on the electrostatic chuck 6 at t 1 , and first, at t 2 , for example, the A electrode 2A +
The wafer 1 is attracted by applying a DC voltage of -500V to the B electrode 2B of 500V. Then, at t 3 , the rf electrode 11, 13.56MH
z, after generating plasma 5 to apply a high frequency power of 300 W, varying in t 4 ~t 5 for example the voltage of the B electrode 2B to + 500V. In this state, the Si wafer 1 is uniformly attracted by the negative (-) bias voltage given by the plasma 5 onto the electrostatic chuck 6 to which +500 V is applied to all the electrodes. And, t 6 just before the end of the plasma treatment
After returning the voltage of the B electrode 2B to -500V at t 7, to end the cut plasma treatment rf power at t 8. After that, from t 9 to t 10 , the A electrode 2A and the B electrode 2B are set to 0 V, and the wafer 1 is separated from the chuck 6.

【0021】上記実施例において、Arプラズマ5中での
ウエーハ1の直径上の各点の温度を示したのが図6であ
る。この図からわかるように本実施例におけるウエーハ
上での最大の温度差は16℃程度であった。
FIG. 6 shows the temperature at each point on the diameter of the wafer 1 in the Ar plasma 5 in the above embodiment. As can be seen from this figure, the maximum temperature difference on the wafer in this example was about 16 ° C.

【0022】上記結果は、プラズマ処理中、終始AとB
の電極に+500Vと−500V電圧を印加して静電チャック上
にウエーハを吸着させる従来の方法において、上記実施
例と同様のrfパワーで発生させたArプラズマに2分曝し
た後のウエーハ上での温度差が、図7の温度分布図に示
されるように26℃程度あったのに比べて、大幅に改善さ
れた値である。
The above results show that during the plasma treatment, A and B were used all the time.
In the conventional method of applying +500 V and -500 V voltage to the electrode of No. 2 and adsorbing the wafer on the electrostatic chuck, the wafer after being exposed to Ar plasma generated with the same rf power as in the above embodiment for 2 minutes. The temperature difference is about 26 ° C. as shown in the temperature distribution chart of FIG. 7, which is a significantly improved value.

【0023】また、上記実施例においては、プラズマ処
理終了直前に再びA電極とB電極に極性の異なる同じ高
さの電圧即ち+500Vと−500Vが印加されるので、ウエー
ハ1内に過剰に蓄積されている負(−)電荷をプラズマ
中に逃がすことができ、残留吸着力がなくなってウエー
ハの離脱が極めて容易になり、従来の方法のように脱離
時にウエーハが割れたり、跳ねて位置ずれを生じたりす
ることがなかった。
Further, in the above-described embodiment, since the voltages of the same height with different polarities, that is, + 500V and -500V, are applied to the A electrode and the B electrode again immediately before the plasma processing is finished, they are excessively accumulated in the wafer 1. The negative (-) charges that are generated can be released into the plasma, the residual adsorption force is lost, and the wafer can be detached very easily. It never happened.

【0024】更にまた、プラズマ処理の行われない状態
の時は総てAとBの電極に+500Vと−500V電圧がそれぞ
れ印加されるので、従来の1極式の静電チャックのよう
にプラズマ処理の前後でウエーハの位置ずれを生ずるこ
とがない。
Furthermore, since + 500V and -500V voltages are applied to the electrodes A and B, respectively, when the plasma processing is not performed, the plasma processing is performed like the conventional one-pole type electrostatic chuck. There will be no displacement of the wafer before and after.

【0025】更に本発明の方法においては、Siウエーハ
1内に形成されている半導体素子にダメージを与えない
ためには、チャック電圧の極性の切り換えを急峻に行わ
ないことが望ましく、上記実施例においては、図5に示
されるτ1 の電圧の立ち上がり時間及びτ2 の電圧の立
ち下がり時間を1秒に設定した。なお、このτ1 及びτ
2 は1秒以上あれば十分である。
Further, in the method of the present invention, in order to prevent damage to the semiconductor element formed in the Si wafer 1, it is desirable that the polarity of the chuck voltage is not rapidly changed. Set the rise time of the voltage of τ 1 and the fall time of the voltage of τ 2 shown in FIG. 5 to 1 second. Note that τ 1 and τ
A value of 2 for 1 second or more is sufficient.

【0026】[0026]

【発明の効果】以上説明のように本発明の静電吸着方法
によれば、プラズマ中においてもウエーハ全面にわたつ
て一様に強い吸着力が得られてウエーハ温度の均一化が
図れ、且つプラズマ処理前後のウエーハの固着も完全に
なされ、更にウエーハの取外しが容易でウエーハ破損や
位置ずれを生じない。
As described above, according to the electrostatic adsorption method of the present invention, even in plasma, a strong adsorption force can be obtained uniformly over the entire surface of the wafer, and the wafer temperature can be made uniform, and the plasma The wafer is completely fixed before and after the treatment, and the wafer can be easily removed without damaging or misaligning the wafer.

【0027】従って本発明は、プラズマ処理の品質及び
歩留りの向上に極めて有効である。
Therefore, the present invention is extremely effective in improving the quality and yield of plasma processing.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.

【図2】 本発明の一実施例に用いたRIE 装置の模式図FIG. 2 is a schematic diagram of an RIE device used in one embodiment of the present invention.

【図3】 同実施例における基板ステージ部の模式断面
FIG. 3 is a schematic cross-sectional view of a substrate stage section in the example.

【図4】 同実施例における静電チャックの模式図FIG. 4 is a schematic diagram of an electrostatic chuck in the same example.

【図5】 同実施例におけるチャック電圧印加方法のタ
イムチャート図
FIG. 5 is a time chart diagram of a chuck voltage applying method in the embodiment.

【図6】 同実施例における被処理ウエーハの面内温度
分布図
FIG. 6 is an in-plane temperature distribution diagram of the wafer to be processed in the example.

【図7】 従来の方法における被処理ウエーハの面内温
度分布図
FIG. 7 is an in-plane temperature distribution diagram of a wafer to be processed by a conventional method.

【図8】 1極式静電チャックによる従来の静電吸着方
法を示す図
FIG. 8 is a diagram showing a conventional electrostatic attraction method using a one-pole type electrostatic chuck.

【図9】 2極式静電チャックによる従来の静電吸着方
法を示す図
FIG. 9 is a diagram showing a conventional electrostatic attraction method using a two-pole type electrostatic chuck.

【図10】 2極式静電チャックにおける従来方法の問題
点を示す図
FIG. 10 is a diagram showing a problem of the conventional method in the two-pole type electrostatic chuck.

【符号の説明】[Explanation of symbols]

t1 ウエーハ搭載時 t2 A電極及びB電極への吸着電圧印加時 t3 プラズマ処理開始時 t4 B電極の電圧反転開始時 t5 B電極の電圧反転完了時 t6 B電極の電圧復旧開始時 t7 B電極の電圧復旧完了時 t8 プラズマ処理終了時 t9 A電極及びB電極への電圧印加停止時 t10 ウエーハ離脱時 τ1 電圧立ち上がり時間、 τ2 電圧立ち下がり時間、Tはプラズマ処理時間 1 Siウエーハ 2A 静電チャックのA電極 2B 静電チャックのB電極 3 チャック誘電体 4 DC電源 5 Arプラズマ 6 静電チャック 7 マスフローコントローラ 8 ガス導入口 9 処理室 10 rf電源 11 rf電極 12 赤外線透過窓 13 赤外線温度計 14 極性切り換え装置t 1 When mounted on wafer t 2 When adsorption voltage is applied to A and B electrodes t 3 When plasma processing is started t 4 When voltage reversal of B electrode is started t 5 When voltage reversal of B electrode is completed t 6 Voltage recovery of B electrode is started Time t 7 When voltage recovery of B electrode is completed t 8 When plasma processing is completed t 9 When voltage application to A electrode and B electrode is stopped t 10 Wafer detachment τ 1 voltage rise time, τ 2 voltage fall time, T is plasma Processing time 1 Si wafer 2A Electrostatic chuck A electrode 2B Electrostatic chuck B electrode 3 Chuck dielectric 4 DC power supply 5 Ar plasma 6 Electrostatic chuck 7 Mass flow controller 8 Gas inlet 9 Processing chamber 10 rf power supply 11 rf electrode 12 Infrared transmission window 13 Infrared thermometer 14 Polarity switching device

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 平板状の絶縁物中に埋め込まれ分離され
ている対の電極に正電圧と負電圧をそれぞれ印加して該
絶縁物上に被処理基板を吸着させる静電吸着装置をプラ
ズマ処理に用いるに際して、 プラズマ処理中は前記負電圧を正電圧に切り換えて総て
の電極に正電圧を印加することを特徴とする静電吸着方
法。
1. A plasma treatment of an electrostatic attraction device for applying a positive voltage and a negative voltage to a pair of electrodes embedded and separated in a plate-like insulator to attract a substrate to be treated onto the insulator. In the electrostatic adsorption method, the negative voltage is switched to a positive voltage and a positive voltage is applied to all the electrodes during the plasma treatment.
【請求項2】 請求項1記載のプラズマ処理が終了する
直前に、該対の電極に正電圧と負電圧がそれぞれ印加さ
れる元の状態に復帰せしめることを特徴とする静電吸着
方法。
2. An electrostatic adsorption method characterized in that, immediately before the plasma processing according to claim 1 is finished, the electrodes are returned to the original state in which a positive voltage and a negative voltage are applied to the pair of electrodes, respectively.
【請求項3】 前記負電圧と正電圧の切り換えを瞬時に
行わず、該切り換えに際しての電圧の立ち上がりまたは
立ち上がりと立ち下がりの時間を所定の長さに制御する
ことを特徴とする請求項1または2記載の静電吸着方
法。
3. The switching between the negative voltage and the positive voltage is not performed instantaneously, but the rising time or rising time and falling time of the voltage at the time of switching is controlled to a predetermined length. 2. The electrostatic adsorption method described in 2.
JP9134792A 1992-04-13 1992-04-13 Electrostatic attraction method Withdrawn JPH05291384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9134792A JPH05291384A (en) 1992-04-13 1992-04-13 Electrostatic attraction method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9134792A JPH05291384A (en) 1992-04-13 1992-04-13 Electrostatic attraction method

Publications (1)

Publication Number Publication Date
JPH05291384A true JPH05291384A (en) 1993-11-05

Family

ID=14023886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9134792A Withdrawn JPH05291384A (en) 1992-04-13 1992-04-13 Electrostatic attraction method

Country Status (1)

Country Link
JP (1) JPH05291384A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177081A (en) * 1992-12-04 1994-06-24 Tokyo Electron Ltd Plasma processor
JPH08316297A (en) * 1995-05-24 1996-11-29 Sony Corp Electrostatic chuck and its controlling method
JPH11106916A (en) * 1997-10-01 1999-04-20 Anelva Corp Plasma treating device
JP2000058514A (en) * 1998-08-05 2000-02-25 Matsushita Electric Ind Co Ltd Method and device for plasma treatment
JP2002526923A (en) * 1998-09-30 2002-08-20 ラム リサーチ コーポレーション Electrostatic dechucking method and apparatus for a dielectric workpiece in a vacuum processor
JP2003059910A (en) * 2001-08-20 2003-02-28 Shibaura Mechatronics Corp Plasma processing apparatus
JP2019186563A (en) * 2019-07-02 2019-10-24 パナソニックIpマネジメント株式会社 Plasma processing apparatus and plasma processing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177081A (en) * 1992-12-04 1994-06-24 Tokyo Electron Ltd Plasma processor
JPH08316297A (en) * 1995-05-24 1996-11-29 Sony Corp Electrostatic chuck and its controlling method
JPH11106916A (en) * 1997-10-01 1999-04-20 Anelva Corp Plasma treating device
JP2000058514A (en) * 1998-08-05 2000-02-25 Matsushita Electric Ind Co Ltd Method and device for plasma treatment
JP2002526923A (en) * 1998-09-30 2002-08-20 ラム リサーチ コーポレーション Electrostatic dechucking method and apparatus for a dielectric workpiece in a vacuum processor
JP4698025B2 (en) * 1998-09-30 2011-06-08 ラム リサーチ コーポレーション Electrostatic dechucking method and apparatus for dielectric workpieces in a vacuum processor
JP2003059910A (en) * 2001-08-20 2003-02-28 Shibaura Mechatronics Corp Plasma processing apparatus
JP2019186563A (en) * 2019-07-02 2019-10-24 パナソニックIpマネジメント株式会社 Plasma processing apparatus and plasma processing method

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