JPH05290175A - Image plotting device - Google Patents

Abstract

PURPOSE:To set plotting efficiency as the rate of the number of pixels where actual writing is performed to the total number of accessed pixels to 1 at all times irrelevantly to whether a primitive is large or small. CONSTITUTION:Image data generators LP0-LP3 generate picture element data according to commands. Memories Mi have storage capacity 1/16 time as large as the storage capacity corresponding to the resolution of a display screen. Pixel processors XPi decide whether or not picture element data from the image data generators LP0-LP3 are effective data for the memories Mi controlled according to pixel addresses on the display screen, and control the storages of the picture element data asynchronously with one another when the data are the effective data. The picture element data stored in the memories Mi are read out by raster scanning and a video processing circuit 17 converts those picture element data into an RGB signal. A cathode-ray tube 18 displays an image based upon the RGB signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image drawing device,
For example, it relates to a display device in a computer graphics system.

[0002]

2. Description of the Related Art In an image drawing apparatus used in, for example, a computer graphics system or an engineering workstation, the drawing speed thereof has a great influence on the processing capacity of the entire system, and is an important factor (element) for determining the processing capacity. Is becoming Therefore, various methods have been developed to increase the drawing speed. For example, as a typical method, there is a so-called pixel cache method, a memory interleave method such as a block write method, or the like.

Here, the pixel cache method and the memory interleave method will be briefly described.

As shown in FIG. 7, the main part of the image drawing apparatus adopting the pixel cache system corresponds to the resolution of the display screen and the image data generator 71 for decoding the command and generating the pixel data. An image memory 72 having a storage capacity for storing pixel data, and the image data generator 71.
And a pixel cache memory 73 having a storage capacity of n × n pixels (hereinafter referred to as pixels).

For example, a computer (hereinafter CPU)
Command (hereinafter referred to as a command), such as a command for drawing a line segment or a surface, so-called BITB
The image data generator 71 decodes data transfer commands such as LT (BITBLOCK TRANSFER) commands in the image memory and so-called fill commands for filling the inside of the figure to generate pixel data, and the pixel data is generated at high speed in the pixel cache. After the image data is stored in the image memory 72 via the memory 73, the pixel data stored in the image memory 72 is read out in synchronization with the scanning of the cathode ray tube (not shown) (by so-called raster scan) to display the image. It has become. That is, by arranging the pixel cache memory 73 capable of high speed access between the image data generator 71 and the image memory 72, high speed drawing is enabled.

However, this pixel cache method is
The storage capacity of the pixel cache memory 73 is small, and the address indicating the position of the pixel data from the image data generator 71 on the display screen is the pixel cache memory 73.
If the address area of the pixel data currently stored exceeds the area, the pixel cache memory 7
3 requires reading and writing of pixel data between the image memory 72 and the image memory 72, and there is a problem that the efficiency is significantly lowered particularly when the image memory 72 is randomly accessed to update the pixel data.

On the other hand, the main part of the image drawing apparatus adopting the memory interleave method is, as shown in FIG. 8, an image data generator 8 for decoding a command and generating pixel data and the like.
1 and n memories m _i (i = 0 to n−1) each having a storage capacity of 1 / n of the storage capacity corresponding to the resolution of the display screen and respectively storing pixel data, and the n memory cells. constructed from the memory m _i a of n which respectively control the memory controller _{MP i (i = 0~n-1} ).

Further, the n memories m _{i as} a whole form an image memory 82 corresponding to a display screen, and each memory m _i has, for example, 16 (n = 16) image memories 82 as shown in FIG. ) Divide and set the pixel corresponding to the upper left corner on the display screen as the origin and set the horizontal and vertical directions as x.
Set each pixel on the display screen as P and Y axes.
_When expressed by _{x, y} (x and y are coordinates on the display screen and are hereinafter referred to as pixel addresses), the memories m ₀ , m ₁ ,
m ₂ , m ₃ , m ₄ , m ₅ ... m ₁₅ are respectively pixels P _{4q, 4r} , pixels P _{4q + 1,4r} , pixels P _{4q + 2,4r} , pixels P _{4q + 3,4r} , pixels P _{4q, 4r + 1} , pixel P _{4q + 1,4r + 1} ... Pixel P
Pixel data for _{4q + 3, 4r + 3} (q, r = 0, 1, 2, ...) _Is stored.

Then, for example, a command for drawing a line segment, a surface, etc. from the CPU, a data transfer command, a fill command, etc. are decoded by the image data generator 81 to generate pixel data, and this pixel data is stored in the memory controller. M
Under the control of P _i , after storing in each memory m _i based on the address commonly supplied from the image data generator 81, the pixel data stored in each memory m _i is read by raster scan, An image is displayed on a cathode ray tube (not shown). That is, as shown in FIG. 9 described above, 16 memory controllers MP ₀ to
MP ₁₅ has 4 × 4 pixels P _{4q, 4r to} P _{4q + 3,4r + 3}
Block B _X, block address one of _Y, which is supplied from the image data generator 81 consists of (X, Y)
By performing access based on (X, Y = 0, 1, 2, ...), That is _, by simultaneously accessing 16 pixels P _{x, y} in the block B _{X, Y} , a speedup is achieved. There is.

However, also in this memory interleave system, the memory controllers MP _{0 to} MP ₁₅ are arranged in the block B.
Pixel P that does not actually need to be drawn by simultaneously accessing 16 pixels P _{x, y} in _{X, Y
Since} dummy access is also made to _{x and y} , the drawing efficiency, which is the ratio of the number of pixels actually written to the total number of accessed pixels, is reduced.

For example, as shown in FIG. 9 described above, blocks B _3,0 , B _2,1 , B _3,1 , B _4,1 , B _2,2 , B _3,2 , B
_When a triangle that spans nine blocks of _4,2 , B _4,3 , and B _5,3 is drawn, the number of pixels actually written ( represents the pixel actually written) is 57. The total number of accessed pixels (× represents a dummy accessed pixel) is 144 (= 16 × 9), and the drawing efficiency is about 0.4 (= 57/144). It should be noted that this drawing efficiency tends to decrease as the number of drawn primitives such as straight lines, triangles, and squares decreases. In other words, it means that the drawing speed is limited no matter how large the division number n of the image memory 82 is.
Further, if the number of divisions n is increased, the scale of hardware also increases.

[0012]

As described above, in the memory interleave method, the image memory 82 having a storage capacity corresponding to the resolution of the display screen is divided into n, and each divided memory m _i is dedicated. By controlling by the memory controller MP _i , 16 pixels P _{x, y} in the same block B _{X, Y} can be simultaneously accessed by one access, which is a method for increasing the speed.
The memory controller MP _i does not have a function of generating an address, and as described above, a dummy access is required even for a pixel that does not need to be written, which causes a problem that drawing efficiency is significantly reduced.

The present invention has been made in view of the above circumstances, and is an image drawing apparatus adopting a memory interleave method, and always sets the drawing efficiency to 1 regardless of the size of the primitive to be drawn. It is an object of the present invention to provide an image drawing device capable of performing the above.

[0014]

According to the present invention, in order to solve the above-mentioned problems, image data generating means for generating pixel data based on a drawing command and 1 / n of a storage capacity corresponding to the resolution of a display screen. N storage means for storing pixel data, and n control means for respectively controlling pixel data from the image data generation means in the n storage means asynchronously with each other. It is characterized by including.

Further, the n storage means have a pipeline structure.

[0016]

In the image drawing apparatus according to the present invention, the n control means asynchronously control the storage of the pixel data from the image data generation means in the n storage means.

Further, the n control means carry out control of storing the pixel data from the image data generation means in the n storage means by a pipeline consisting of a plurality of stages.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image drawing apparatus according to the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a circuit configuration of a so-called graphics engine to which the image drawing device according to the present invention is applied.

First, the graphics engine will be described. The graphics engine is, as shown in FIG. 1, a workstation main body 11, a memory 12 connected to an internal bus of the workstation main body 11 for storing an instruction for image processing, and an instruction stored from the memory 12. Are sequentially read out to calculate the parameters necessary for generating the pixel data, the RP 14 for managing the data flow of this graphics engine, and the pixel data are generated in accordance with the instruction and the parameter for generating the pixel data from the SP 13. An image data generation circuit 15 for generating the image data, an image memory device 16 for storing the pixel data from the image data generation circuit 15, and a video process for converting the pixel data read from the image memory device 16 into so-called RGB signals. Based on the circuit 17 and the RGB signals from the video processing circuit 17, To display consists of a cathode-ray tube 18..

In this graphics engine, the workstation main body 11 and the memory 12 are connected by, for example, a so-called VME (Versa Module European) bus, and the memory 12 receives instructions from the workstation main body 11 for image processing. Command), for example, a command for drawing a line segment, a surface, etc., a data transfer command, a fill command, etc. are temporarily stored. The stored instructions are sequentially read by the SP 13, converted into commands and parameters for generating pixel data, and supplied to the image data generating circuit 15. Image data generation circuit 1
Reference numeral 5 decodes the command and generates pixel data such as pattern information, color information, mask information, coordinate information on the display screen of the cathode-ray tube 18, data transfer command, etc. according to the parameters, and these pixel data, etc. Is supplied to the image memory device 16. The image memory device 16 is, for example, a so-called bit map type memory, and the storage capacity thereof is the resolution of the display screen of the cathode ray tube 18, for example, 1024 × 10.
It corresponds to 24 pixels (hereinafter referred to as pixels), stores the pixel data of each pixel, reads the stored pixel data in synchronization with the scanning of the cathode ray tube 18 (by so-called raster scan), and reads this. The pixel data is supplied to the video processing circuit 17. Video processing circuit 1
Reference numeral 7 is composed of, for example, a D / A converter, which converts pixel data into RGB signals and displays an image based on the RGB signals on the cathode ray tube 18.

Specifically, the image memory device 16 is
As shown in FIG. 1 described above, n memories M each having a storage capacity of 1 / n of the storage capacity corresponding to the resolution of the display screen of the CRT 18 and storing pixel data.
_i (i = 0 to n−1) and the image data generation circuit 15
From the n pixel processors XP _i (i = 0 to n−1) for controlling the storage of the pixel data from the above in the n memory M _i asynchronously with each other, and the input of the n pixel processors XP _i . Connect output port IO ₂ in common,
A bus (hereinafter referred to as TBus (Transfer Bus)) 19 for transferring pixel data between the pixel processors XP _i .

That is, the image memory device 16 adopts the so-called memory interleave system, and the image memory 20 corresponding to the display screen in the bitmap system is formed by the n memories M _i . For example, as shown in FIG. 2, each memory M _i includes an image memory 20 such as 1
The pixel is divided into 6 (n = 16), the pixel corresponding to the upper left corner of the display screen of the cathode ray tube 18 is the origin, the horizontal and vertical directions are the x-axis and the y-axis, respectively, and each pixel on the display screen is P _{x, y.} (X and y are coordinates on the display screen and are referred to as pixel addresses below), the memories M ₀ , M ₁ ,
M ₂ , M ₃ , M ₄ , M ₅ ... M ₁₅ are respectively pixels P _{4q, 4r} , pixels P _{4q + 1,4r} , pixels P _{4q + 2,4r} , pixels P _{4q + 3,4r} , pixels P _{4q, 4r + 1} , pixel P _{4q + 1,4r + 1} ... Pixel P
Pixel data for _{4q + 3, 4r + 3} (q, r = 0, 1, 2, ...) _Is stored. In addition, each memory M
For example, in color display, _i has a plurality of plane structures, and red data, green data, blue data of three primary colors, depth data for three-dimensional (so-called 3D), etc. are provided in each plane for each pixel P _{x, y} . It also stores and uses one of its planes as a fillwork buffer to perform the fill.

On the other hand, the pixel processor XP _i is provided in the memory M _i in a 1: 1 relationship as shown in FIG.
When divided, the number is 16. Then, these pixel processors XP _{0 to} XP ₁₅ determine whether or not the pixel data should be processed based on the pixel addresses x and y from the image data generation circuit 15, and the pixel data from the image data generation circuit 15 is determined. Is asynchronously stored in the corresponding memories M _{0 to} M ₁₅ via the input / output port IO ₁ .

When each pixel processor XP _i transfers data in the image memory 20, for example, the pixel data read from the memory M _i via the input / output port IO ₁ has its own number i. The data is output to the TBus 19 via the input / output port IO _{2 in the} ascending order, and the number j of the pixel processor XP _j of the pixel data transfer source is obtained, and based on this number j, the pixel processor XP _i of the transfer source transfers the TBus 19 and I / O port I
The pixel data supplied via O ₂ is received, and the received pixel data is received through the memory M via the input / output port IO _1.
It is designed to control writing to _i .

On the other hand, the image data generation circuit 15 has four image data generators LP _{0 to} LP ₃ when the image memory 20 is divided into 16 as shown in FIG.
The image data generator LP ₀ supplies the pixel data and the like generated by the image data generator LP ₀ to the pixel processors XP _{0 to} XP ₃ by decoding the command from the SP 13 and generating pixel data and pixel addresses x and y according to the parameters. Then, the image data generator LP ₁ becomes the pixel processor XP.
_{4 to} XP ₇ are supplied with pixel data and the like, the image data generator LP ₂ supplies pixel data and the like to pixel processors XP _{8 to} XP ₁₁ , and the image data generator LP ₃ is supplied to pixel processors XP _{12 to} XP ₁₅ with pixels. It supplies data and so on.

The configuration of the image memory device 16 and the image data generating circuit 15 is not limited to the configuration in which the image memory 20 shown in FIG. 1 is divided into 16 parts. For example, the image memory 20 is divided into 4 parts. For example, as shown in FIG. 3a, one image data generator LP and
Each of the pixel processors XP _{0 to} XP ₃ uses one basic unit consisting of the pixel processors XP _i .
As shown in FIG. 3b, reading and writing of pixel data for each corresponding pixel (corresponding pixels are indicated by numbers) on the display screen of the image memory 20 divided into four are controlled respectively. Good.

Further, when the image memory 20 is divided into eight, for example, as shown in FIG. 3C, each of the pixel processors XP _{0 to} XP _{7 is} used by using the two basic units described above.
However, as shown in FIG.
The reading and writing of the pixel data for each corresponding pixel on the display screen may be controlled.

When the image memory 20 is divided into 32, for example, as shown in FIG. 4a, each of the pixel processors XP _{0 to} XP _{0 is} used by using the eight basic units described above.
_As shown in FIG. 4b, ₃₁ may control reading and writing of pixel data for each corresponding pixel on the display screen of the image memory 20 divided into 32. In short, if the image memory device 16 is of a memory interleave type that divides the image memory 20 according to the resolution of the display screen into a plurality of parts and each pixel processor XP _i controls one of the divided memories M _i. Well, the description will be continued below with a specific example in which the image memory 20 is divided into 16.

The specific circuit configuration of the pixel processor XP _i is, for example, as shown in FIG. 5, the pixel data supplied from the image data generators LP _{0 to} LP ₃ respectively via the input / output port IO _1. supplies to the memory M _i, the main path circuit 21 for a pixel data read via the input and output ports IO ₁ from the memory M _i through the input and output ports IO ₂ outputs to the TBus 19,
The address decoder 22 for decoding the pixel addresses x and y respectively supplied from the image data generators LP _{0 to} LP ₃ to control the so-called pipeline operation of the main path circuit 21 and the main path circuit 21. A sequencer 23 that controls the flow of data and the like, a memory controller 24 that controls reading and writing of pixel data to and from the memory M _i, and a pixel processor X that is a transfer source.
The TBus controller 25 that determines the number j of P _j , determines whether or not there is a transfer, and controls the TBus 19
An address generator 26 that generates an address of a rectangular area to be transferred and supplies it to the sequencer 23 when transferring data such as a BITBLT command, and the main path circuit 21.
The control register 27 stores, for example, parameters for controlling the address generator 26.

Then, the address decoder 22 decodes the pixel addresses x and y respectively supplied from the corresponding image data generators LP _{0 to} LP _3, and is also supplied from the image data generators LP _{0 to} LP _3. It is determined whether or not the pixel data is data for the memory M _i managed by itself, and if it is applicable, the pipeline operation of the main path circuit 21 is controlled.

Specifically, the image memory 20 is divided into 2 ^u (u = 1, 2, 3, ...) In the horizontal direction of the display screen and 2 ^v (v = 1, 2, 3, ...) In the vertical direction.・) With the division
For each pixel processor XP _i , a horizontal unique number NX (NX = 0, 1, 2, ...) And a vertical unique number NY (NY = 0, 1, 2, ...) The address decoder 22 of each pixel processor XP _i compares the unique number NX with the lower u bits of the pixel address x and the unique number NY with the lower v bits of the pixel address y, and when they match, Controls the pipeline operation of the main path circuit 21 by using the pixel data of the pixel addresses x and y as valid data for the memory M _i managed by itself. For example, as shown in FIG. 1 described above, the division number n of the image memory 20 is 16
(U, v = 2), each pixel processor XP _i
In order from the smallest number i, (NX, NY) is (0, 0),
(1,0), (2,0), (3,0), (0,1),
(1,1), (2,1), (3,1), (0,2),
(1,2), (2,2), (3,2), (0,3),
Unique numbers such as (1, 3), (2, 3), and (3, 3) are given, and the address decoder 22 of each pixel processor XP _i has the unique number NX and the lower 2 bits of the pixel address x, and The unique number NY is compared with the lower 2 bits of the pixel address y. Further, as shown in FIG. 4b, for example, the division number n of the image memory 20 is 32 (u = 2,
v = 3), each pixel processor XP _i is assigned (NX, NY) with (0, 0), (1,
0), (2,0), (3,0), (0,1), (1,
1), (2,1), (3,1), (0,2), (1,
2), (2,2), (3,2), (0,3), (1,
3), (2,3), (3,3), (0,4), (1,
4), (2,4), (3,4), (0,5), (1,
5), (2,5), (3,5), (0,6), (1,
6), (2,6), (3,6), (0,7), (1,
7), (2,7), (3,7)
Address decoder 22 of each pixel processor XP _i
Is the lower 2 bits of the unique number NX and the pixel address x, and the lower 3 bits of the unique number NY and the pixel address y.
Compare bits. When they match, only the address decoder 22 of the matched pixel processor XP _i controls the pipeline operation and the like of the main path circuit 21 with the supplied pixel data as valid data.

On the other hand, the sequencer 23 controls the data flow of the main path circuit 21 as described above. Specifically, for example, the flow of data for storing the pixel data from the image data generators LP _{0 to} LP _{3 in} the memory M _i via the input / output port IO ₁ , the memory M _i to the input / output port IO.
Pixel data read via ₁ is input / output port IO
₂ and other pixel processor X via TBus19
It controls the flow of data transferred to P _i and stored in the memory M _i via the input / output port IO ₁ of the transferred pixel data.

Further, the memory controller 24 is adapted to generate the write address and the read address or the like for the memory M _i, controls the reading and writing of pixel data in the memory M _i by using these addresses.

When the TBus controller 25 transfers data between the memories M _i , the TBus controller 25 determines whether or not the transfer is performed, and the pixel data read from the memory M _i via the input / output port IO ₁ is transferred to the pixel processor XP. _i number i
Output to the TBus 19 via the input / output port IO _{2 in the} ascending order, obtain the number j of the pixel processor XP _j of the transfer source, and control the acquisition of the pixel data supplied via the TBus 19 in the ascending order of the number j. ..

The above-described operations of the main path circuit 21 to the control register 27 are composed of a plurality of stages, and each stage is executed by a pipeline operating in parallel.

Specifically, this pixel processor XP
For example, as shown in FIG. 6, the pipeline of _i is generated from the image data generators LP _{0 to} LP ₃ based on the pixel addresses x and y supplied from the image data generators LP _{0 to} LP ₃ , respectively. A stage # 0 for determining whether the supplied pixel data is valid data,
Stage # for performing various processes such as color conversion and shift on pixel data determined to be valid data by 0
And 1 to # 3, consisting of the stage # 4 for writing the pixel data processed in the stage # 1 to # 3 in the memory M _i.

Then, for example, as shown in FIG.
When drawing a triangular surface as a so-called primitive (●
Represents the pixel to be drawn), first, for example, the pixel data of the pixel P _14,3 for the block B _3,0 which is one of the blocks B _{X, Y} which are units that can be simultaneously accessed by each pixel processor XP _i. , Each pixel processor X
P _i , each pixel processor XP _i , at stage # 0, has a pixel address (x = 14, y =
By determining whether the data is valid data based on 3), only the pixel processor XP ₁₄ (NX = 2, NY = 3) sets the pixel data as valid data, and proceeds to the next stage # 1.

Next, for example, the pixel data of the pixel P _11,7 for the block B _2,1 is calculated for each pixel processor XP _i.
To each pixel processor XP _i at stage # 0, the pixel address (x = 11, y =
By determining whether the pixel data is valid data based on 7), only the pixel processor XP ₁₅ (NX = 3, NY = 3) uses the pixel data as valid data, and the pixel processor XP ₁₄ described above has the stage # 1 Perform processing.

Next, for example, pixels for the block _{B 3,1 P 13,4, P 14,4,} P 15,4, P 12,5, P 13,5,
_{P 14,5, P 15,5, P 12,6} , P 13,6, P 14,6, P 15,6, P
_{When the} pixel data of _12,7 , P _13,7 , P _14,7 , and P _15,7 are supplied, each pixel processor XP _{i causes} the stage # 0.
In the pixel address x, by determining whether valid data based on y, pixel processor XP ₁
Pixel processors XP _{1 to} XP ₁₅ other than the above make the pixel data valid data, respectively, and the above-mentioned pixel processor XP ₁₄ carries out the process of stage # 2 and the pixel processor XP ₁₅ carries out the process of stage # 1.

Hereinafter, similarly, each pixel processor XP
_i, each block _X, together with the pixel data for _Y determines whether valid data at stage # 0 for each fed, color conversion in stage # 1 to # 4 followed by the stage # 0, the write to the memory M _i Etc. are performed in parallel.
In addition, after the stage # 1, each pixel processor XP _i executes only the pixel data for which the pixel data is determined to be valid in the stage # 0, that is, operates asynchronously with each other, and the pixel processors XP _i and the other pixel processors XP _i . Completely independent memory access. As a result, the number of pixels actually written (for example, 57) matches the total number of accessed pixels (57), and the drawing efficiency is the ratio of the number of actually written pixels to the total number of accessed pixels. Can always be 1 (= 57/57). In other words, the drawing efficiency can be significantly improved as compared with the conventional device. Further, the drawing efficiency does not decrease even if the size of the primitive becomes small.

By the way, the processing of stages # 0 to # 3 is as follows.
Although it can be completed within one clock, for example, writing to the memory M _{i in} the stage # 4 depends on the write cycle of the semiconductor memory (so-called RAM) used. Therefore, if a RAM with a write cycle of 1 clock is used, all stages # 0 to # 4 can be executed with 1 clock, but it is not realistic to use such a high-speed RAM. Therefore, for example, when the memory M _i is composed of a RAM having a relatively slow write cycle, and the writing process of the stage # 4 takes, for example, 6 clocks, the access to the memory M _i managed by the same pixel processor XP _i is continuous. However, in this embodiment, each stage has a function of accumulating pixel data, and even if the access continues for the number of times corresponding to the number of stages, the memory M _i is stored. Access can be performed without interruption, and the effective drawing speed is not reduced.

As described above, in this embodiment, the pixel processor XP _i is used as the image data generator LP _{0 to} LP _3.
The drawing efficiency can always be set to 1 by controlling the storage of the pixel data from the memory M _i in the memory M _i asynchronously with each other, that is, by completely accessing the memory independently of the other pixel processors XP _i . That is, the drawing efficiency can be significantly improved as compared with the conventional device. Further, the drawing efficiency does not decrease even if the size of the primitive becomes small.

Further, by making the pixel processor XP _i into a pipeline structure, even if the same memory M _{i is} accessed several times in succession, the access to the memory M _i can be performed without interruption. It does not reduce the effective drawing speed.

[0044]

As is apparent from the above description, in the present invention, the n control means asynchronously control the storage of the pixel data from the image data generation means in the n storage means. Thus, the drawing efficiency can always be 1 regardless of the size of the primitive to be drawn.

Further, by making the n control means a pipeline structure, even if the same storage means is accessed several times in succession, it is possible to access the storage means without interruption, which is effective. It does not reduce the drawing speed.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a graphics engine to which an image drawing device according to the present invention is applied.

FIG. 2 is a diagram showing pixel positions on a display screen of a memory M _i forming the graphics engine.

FIG. 3 is a diagram showing another specific circuit configuration of an image data generation circuit and an image memory device which constitute the graphics engine.

FIG. 4 is a diagram showing another specific circuit configuration of an image data generation circuit and an image memory device which form the graphics engine.

FIG. 5 is a diagram showing a specific circuit configuration of a pixel processor XP _i that constitutes the image memory device.

FIG. 6 is a diagram showing each stage for explaining a pipeline of the pixel processor XP _i .

FIG. 7 is a diagram showing a circuit configuration of a main part of a conventional image drawing apparatus adopting a pixel cache system.

FIG. 8 is a diagram showing a circuit configuration of a main part of a conventional image drawing apparatus adopting a memory interleave method.

FIG. 9 is a diagram showing positions of pixels on a display screen of an image memory which constitutes a conventional image drawing apparatus adopting the memory interleave method.

[Explanation of symbols]

15 ... Image data generation circuit LP _{0 to} LP ₃ ... Image data generator 16 ... Image memory device XP _{0 to} XP ₁₅ ... Pixel processor M _{0 to} M ₁₅ ... Memory

Claims (2)

[Claims] 1. An image data generation unit for generating pixel data based on a drawing command, and n number of storage units each having a storage capacity of 1 / n of a storage capacity corresponding to a resolution of a display screen and storing pixel data. An image drawing apparatus comprising: a storage unit; and n control units that perform control of storing pixel data from the image data generation unit in the n storage units asynchronously with each other. 2. The image drawing apparatus according to claim 1, wherein the n storage means have a pipeline structure.