JPH0528909B2 - - Google Patents
Info
- Publication number
- JPH0528909B2 JPH0528909B2 JP61165671A JP16567186A JPH0528909B2 JP H0528909 B2 JPH0528909 B2 JP H0528909B2 JP 61165671 A JP61165671 A JP 61165671A JP 16567186 A JP16567186 A JP 16567186A JP H0528909 B2 JPH0528909 B2 JP H0528909B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance value
- resistance
- gaas
- active layer
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 14
- 238000002513 implantation Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体素子の製造方法に関し、特に
GaAs半導体基板に形成された活性層を用いた抵
抗素子の抵抗値の調整に関する。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
This invention relates to adjusting the resistance value of a resistance element using an active layer formed on a GaAs semiconductor substrate.
（従来の技術）
従来、この種の半導体素子の製造方法について
は、例えば特公昭58−7065号公報に記載されてい
る。一般に、GaAs半導体集積回路（以下GaAs
ICという）における活性層を用いた抵抗素子は、
不純物の拡散あるいはイオン注入及びアニール処
理することにより形成することができる。この様
な方法において、抵抗素子の抵抗値は不純物イオ
ンの注入量（ドーズ量）を変化させることによつ
て行なわれる。(Prior Art) Conventionally, a method for manufacturing this type of semiconductor element is described in, for example, Japanese Patent Publication No. 7065/1983. Generally, GaAs semiconductor integrated circuits (hereinafter referred to as GaAs
A resistive element using an active layer in an IC) is
It can be formed by impurity diffusion or ion implantation and annealing. In such a method, the resistance value of the resistance element is determined by changing the amount of impurity ions implanted (dose).
（発明が解決しようとする問題点）
しかしながら、以上のような半導体素子の製造
方法では、現状の化合物半導体基板の特性のバラ
ツキおよび製造工程での条件のバラツキが不可避
なため、回路設計上望まれる抵抗値を有した抵抗
素子を全部の基板にわたつて再現性良く形成する
のは困難であつた。(Problems to be Solved by the Invention) However, in the above-described semiconductor device manufacturing method, variations in the characteristics of the current compound semiconductor substrate and variations in conditions during the manufacturing process are unavoidable. It has been difficult to form a resistor element having a resistance value over all substrates with good reproducibility.
そこでこの発明の目的は、基板に形成された
GaAs ICの特性を劣化させることなしに、所望
の抵抗値を有する抵抗素子を備えたGaAs ICを
再現性良く製造する方法を提供することにある。 Therefore, the purpose of this invention is to
An object of the present invention is to provide a method for manufacturing a GaAs IC having a resistance element having a desired resistance value with good reproducibility without deteriorating the characteristics of the GaAs IC.
（問題点を解決するための手段）
本発明は前記問題点を解決するために、複数の
化合物半導体基板それぞれに抵抗素子となる活性
層を形成し、前記抵抗素子の抵抗値を測定し所望
の抵抗値よりも小さい抵抗値の抵抗素子を有する
基板を選別し、選別された前記基板に形成された
前記抵抗素子に対して、イオン注入し、その後
300〜400℃程度の温度でアニールすることによつ
て、前記小さい抵抗値を前記所望の抵抗値に補正
するものである。(Means for Solving the Problems) In order to solve the above problems, the present invention forms an active layer serving as a resistance element on each of a plurality of compound semiconductor substrates, measures the resistance value of the resistance element, and obtains a desired value by measuring the resistance value of the resistance element. Selecting a substrate having a resistance element having a resistance value smaller than the resistance value, implanting ions into the resistance element formed on the selected substrate, and then
The low resistance value is corrected to the desired resistance value by annealing at a temperature of about 300 to 400°C.
（作用）
本発明では、以上のように少なくとも活性層に
よる抵抗素子を形成した後、所望の抵抗値よりも
小さい抵抗値の抵抗素子を有する基板に対して、
選択的に抵抗素子にイオン注入しているので、こ
のイオン注入により抵抗素子領域に格子欠陥が発
生する。さらに、このイオン注入後に300℃〜400
℃の温度でアニールすることにより、結晶中に十
分分離されて存在する点欠陥を消滅させているの
で、所望の抵抗値を有する抵抗素子を再現性良く
得ることができる。また300℃〜400℃の温度でア
ニールしているで、ICの特性に著しい劣化は生
じない。(Function) In the present invention, after forming a resistive element using at least an active layer as described above, a substrate having a resistive element having a resistance value smaller than a desired resistance value is
Since ions are selectively implanted into the resistive element, lattice defects are generated in the resistive element region due to the ion implantation. Furthermore, after this ion implantation, the
By annealing at a temperature of .degree. C., point defects that are sufficiently isolated in the crystal are eliminated, so that a resistive element having a desired resistance value can be obtained with good reproducibility. Furthermore, since the IC is annealed at a temperature of 300°C to 400°C, there is no significant deterioration in the characteristics of the IC.
（実施例）
第１図は、本発明の実施例を説明するための素
子断面図であり、第２図は11Bのドーズ量と抵抗
素子の抵抗値との関係を示す図であり、第３図は
11Bイオン注入後のアニール温度と抵抗素子のシ
ート抵抗との関係を示す図である。以下、図面に
沿つて実施例を説明する。(Example) FIG. 1 is a cross-sectional view of an element for explaining an example of the present invention, and FIG. 2 is a diagram showing the relationship between the dose of 11 B and the resistance value of a resistance element. Figure 3 is
11 is a diagram showing the relationship between the annealing temperature after B ion implantation and the sheet resistance of a resistance element. Examples will be described below with reference to the drawings.
第１図に示すように通常の方法により、GaAs
基板１に、29Si等を100keVで選択的にイオン注入
し800℃程度の温度でアニールすることにより活
性層２を形成し、AuGe／Ni／Au等のオーミツ
ク電極３を所定領域に形成することにより、活性
層を用いた抵抗素子を形成する。同様に図示しな
い他のGaAs基板にも、少なくとも抵抗素子を形
成する。次にプローブ針等を用いて抵抗素子の抵
抗値を測定した後、所望の抵抗値より小さい抵抗
値を有する抵抗素子が形成されたGaAs基板に対
し11Bを、注入エネルギー100keV、所定の注入量
でイオン注入した後、380℃の温度で５分間のア
ニールを行うことにより、所望の抵抗値を有する
抵抗素子を形成する。 As shown in Figure 1, GaAs
An active layer 2 is formed by selectively ion-implanting 29 Si or the like at 100keV into the substrate 1 and annealing at a temperature of about 800°C, and an ohmic electrode 3 of AuGe/Ni/Au or the like is formed in a predetermined region. In this way, a resistance element using an active layer is formed. Similarly, at least a resistance element is formed on another GaAs substrate (not shown). Next, after measuring the resistance value of the resistance element using a probe needle, etc., 11 B was implanted at a predetermined implantation amount at 100keV into the GaAs substrate on which the resistance element with a resistance value smaller than the desired resistance value was formed. After ion implantation, a resistive element having a desired resistance value is formed by performing annealing at a temperature of 380° C. for 5 minutes.
第２図に示されるように、11Bの注入量と抵抗
値の変化から、所望の抵抗値より小さい抵抗値の
抵抗素子に対するイオン注入量はわかる。また、
第２図に示されるように、11B注入のみを行なつ
た場合と、11B注入後380℃の５分間のアニールを
する場合を比較すると11B注入後、380℃で５分
間のアニールを行なつた場合には、11B注入量と
活性層の抵抗値の間に良い直線関係が得られ、活
性層の抵抗値を精度良く制御できることがわか
る。 As shown in FIG. 2, from the change in the 11 B implantation amount and the resistance value, the ion implantation amount for a resistive element having a resistance value smaller than the desired resistance value can be determined. Also,
As shown in Figure 2, comparing the cases where only 11 B implantation is performed and the case where 5 minutes of annealing at 380°C is performed after 11 B implantation, the results are as follows: When this is carried out, a good linear relationship is obtained between the amount of 11 B implanted and the resistance value of the active layer, indicating that the resistance value of the active layer can be controlled with high precision.
また、第３図は11B注入後、順次温度を上げな
がらアニールを繰り返した場合の温度と活性層２
のシート抵抗との関係を示している。ここで活性
層２は29Siを100keVの注入エネルギーで1.5×
1013dose／cm2イオン注入することにより形成し、
11Bは注入エネルギー200keVで４×109dose／cm2
イオン注入したものである。第３図に示されるよ
うに、300℃〜400℃の範囲の温度でアニールする
ことにより、シート抵抗がほぼ一定となり、再現
性良く目的とするシート抵抗を得ることができ
る。また、この範囲の温度ではオーミツク電極に
悪影響を及ぼすことはない。 Figure 3 shows the temperature and active layer 2 when annealing is repeated while increasing the temperature after 11 B implantation.
shows the relationship between sheet resistance and sheet resistance. Here, the active layer 2 is made of 29Si with an implantation energy of 100keV at 1.5×
Formed by 10 13 dose/cm 2 ion implantation,
11 B is 4×10 9 dose/cm 2 at implantation energy of 200 keV.
It is ion implanted. As shown in FIG. 3, by annealing at a temperature in the range of 300° C. to 400° C., the sheet resistance becomes approximately constant, and the desired sheet resistance can be obtained with good reproducibility. Furthermore, temperatures within this range do not have any adverse effect on the ohmic electrode.
このように、本発明の実施例によれば、抵抗素
子の形成後も抵抗素子の抵抗値が目的とする値よ
りも小さい場合には大きい方向へずらすことが可
能となり、目的とする抵抗値を得ることができ
る。また選択的に抵抗を高くする場合には抵抗を
高くしたい抵抗以外の部分にレジスト等でマスク
をしてイオン注入を行なえば良い。 As described above, according to the embodiment of the present invention, even after the resistance element is formed, if the resistance value of the resistance element is smaller than the target value, it is possible to shift it in the larger direction, so that the target resistance value can be adjusted. Obtainable. In addition, in order to selectively increase the resistance, ions may be implanted while masking portions other than the resistor whose resistance is desired to be increased with a resist or the like.
したがつて、GaAs ICの製造プロセスにおい
て形成後、活性層を用いた抵抗素子の抵抗値が目
的とする値よりも小さい場合には本発明を用いれ
ば目的とする抵抗をもつたGaAs ICを作製する
ことが可能となる。 Therefore, if the resistance value of a resistive element using an active layer is smaller than the desired value after formation in the GaAs IC manufacturing process, the present invention can be used to fabricate a GaAs IC with the desired resistance. It becomes possible to do so.
さらに、イオン注入後に300℃〜400℃の温度で
アニールしているので、GaAs ICを構成するト
ランジスタ等の他の素子に悪影響を及ぼすことな
く、抵抗値を精度良く制御することができる。 Furthermore, since ion implantation is followed by annealing at a temperature of 300°C to 400°C, the resistance value can be precisely controlled without adversely affecting other elements such as transistors that make up the GaAs IC.
（発明の効果）
以上詳細に説明したように、本発明によれば、
GaAs IC構造が完成した後にも抵抗素子の抵抗
値が目的とする値よりも小さい場合、精度良く制
御することができる。したがつて、所望の抵抗値
を有した抵抗素子を備えたGaAs ICを再現性良
く形成することができる。(Effects of the Invention) As explained in detail above, according to the present invention,
Even after the GaAs IC structure is completed, if the resistance value of the resistor element is smaller than the desired value, it can be controlled with precision. Therefore, a GaAs IC including a resistance element having a desired resistance value can be formed with good reproducibility.
第１図は、本発明の実施例を説明するための素
子断面図であり、第２図は11Bのドーズ量と抵抗
素子の抵抗値との関係を示す図であり、第３図は
11Bイオン注入後のアニール温度と抵抗素子のシ
ート抵抗との関係を示す図である。
１…GaAs基板、２…活性層、３…オーミツク
電極。
FIG. 1 is a cross-sectional view of an element for explaining an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the dose of 11 B and the resistance value of a resistance element, and FIG.
11 is a diagram showing the relationship between the annealing temperature after B ion implantation and the sheet resistance of a resistance element. 1...GaAs substrate, 2...active layer, 3...ohmic electrode.
Claims (1)
となる活性層を形成する工程と、 前記抵抗素子の抵抗値を測定し所望の抵抗値よ
りも小さい抵抗値の抵抗素子を有する基板を選別
する工程と、 選別された前記基板に形成された前記抵抗素子
に対して、イオン注入し、その後300〜400℃程度
の温度でアニールすることによつて、前記小さい
抵抗値を前記所望の抵抗値に補正する工程とを有
することを特徴とする半導体素子の製造方法。[Scope of Claims] 1. A step of forming an active layer serving as a resistance element on each of a plurality of compound semiconductor substrates, and a substrate having a resistance element having a resistance value smaller than a desired resistance value by measuring the resistance value of the resistance element. ion implantation into the resistance element formed on the selected substrate, and then annealing at a temperature of about 300 to 400°C to increase the small resistance value to the desired value. 1. A method for manufacturing a semiconductor device, comprising the step of correcting a resistance value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16567186A JPS6321864A (en) | 1986-07-16 | 1986-07-16 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16567186A JPS6321864A (en) | 1986-07-16 | 1986-07-16 | Manufacture of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6321864A JPS6321864A (en) | 1988-01-29 |
| JPH0528909B2 true JPH0528909B2 (en) | 1993-04-27 |
Family
ID=15816811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16567186A Granted JPS6321864A (en) | 1986-07-16 | 1986-07-16 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6321864A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5384579A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Manufacture for semiconductor device |
| JPS587065A (en) * | 1981-07-06 | 1983-01-14 | 株式会社竹中工務店 | Earthquake-proof reinforcing method of established reinforced concrete building |
| JPS59123274A (en) * | 1982-12-28 | 1984-07-17 | Fujitsu Ltd | Manufacture of semicondcutor device |
| JPS60101960A (en) * | 1983-11-08 | 1985-06-06 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit |
| JPS61141167A (en) * | 1984-12-13 | 1986-06-28 | Nippon Precision Saakitsutsu Kk | Manufacture of semiconductor device |
-
1986
- 1986-07-16 JP JP16567186A patent/JPS6321864A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5384579A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Manufacture for semiconductor device |
| JPS587065A (en) * | 1981-07-06 | 1983-01-14 | 株式会社竹中工務店 | Earthquake-proof reinforcing method of established reinforced concrete building |
| JPS59123274A (en) * | 1982-12-28 | 1984-07-17 | Fujitsu Ltd | Manufacture of semicondcutor device |
| JPS60101960A (en) * | 1983-11-08 | 1985-06-06 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit |
| JPS61141167A (en) * | 1984-12-13 | 1986-06-28 | Nippon Precision Saakitsutsu Kk | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6321864A (en) | 1988-01-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |