JPH0528408B2 - - Google Patents

Description

[Detailed description of the invention]

FIELD OF THE INVENTION The present invention relates to an adder in an arithmetic operation device that uses signed digit number representation for internal operations. BACKGROUND ART Conventionally, an adder for redundant binary numbers (a type of signed digit number) has been discussed in the 1985 Journal of the Institute of Electronics and Communication Engineers General National Conference, page 2-187. Regarding high-speed multipliers that use redundant binary representation internally, the IEEE Transactions of Computers (IEEE Trans.
Comput.), Vol.C−34, No.9, September1985,
Discussed on pages 789-796. These represent each digit with two binary signals with values of -1, 0, and 1, and use a combinational circuit to realize addition of redundant binary numbers, and the addition is performed in a fixed time regardless of the number of digits. can be done. Problems to be Solved by the Invention In the conventional example described above, a circuit that takes advantage of the characteristics of the ECL logic element includes an adder that uses many positive and negative logic values of a signal, a selection circuit that uses a transfer gate, etc. Although several proposals have been made, they all have a large number of elements. Therefore, as the number of digits in the calculation increases, the number of elements increases, making it difficult to implement into an LSI. Also,
There are problems such as the large number of delay stages in the adder. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional adder, to provide an adder with a simple configuration, a small number of elements and a small number of delay stages, and suitable for LSI implementation. Means for solving the problem The above purpose is to determine whether the sum is non-negative, one of them is positive, or A first circuit that outputs a binary signal P _i representing a combination state such as whether both are non-negative, and a sum of a carry C _i of the i-th digit and a logical inversion signal _i of the binary signal P _i . a second circuit that outputs a binary signal B _i having the value represented; the intermediate sum S _i of the i-th digit; and the sum of the binary signal P _i-1 representing the combination state of the i-1st digit. S _i +
a third circuit that outputs a signed digit signal R _i representing the value of P _i-1 ; and a binary signal B _i-1 of the output of the second circuit of the i-1st digit and the signed digit signal R From only _i , the intermediate sum S _i of the i-th digit and the i-th
This is achieved by providing a fourth circuit which outputs a signed digit number representing the value of the sum S _i +C _{i-1 with a} one-digit carry C i-1. Effect The present invention has the above-described configuration, so that the signal outputted from that digit of the adder to the next higher digit, or the signal inputted from the lower digit to that digit, becomes two binary signals, that is, the input signal. Only a binary signal representing an addend and a combination of the addends and a binary signal containing information on carry from that digit is sufficient. In addition, the number of combinations of signals containing intermediate carry information is smaller than the number of intermediate carry values that actually occur, and the signal containing intermediate sum information represents the value of the signed digit number of each digit. It is possible to reduce the number of signal lines to less than the required number. From the above, the circuit configuration of the adder can be simplified. Embodiment Hereinafter, an embodiment of the present invention will be described regarding a redundant binary adder. Table 1 shows an example of an addition rule in which a carry propagates only one digit in addition using redundant binary representation.

[Table] In Table 1, the i-th digit summand x _i , the addend y _i ,
The summand x _i-1 of one lower digit, the addend y _i-1 of one lower digit, the carry C _i of the i-th digit, and the intermediate sum S _i are:
Redundant binary numbers, each 1, 0 or -1
has the value of In Table 1, 1 indicates -1. As can be seen from Table 1, the summand x _i , the addend y _i ,
Furthermore, the values of the carry C _i and the intermediate sum S _i differ depending on the values of the next lower addend x _i-1 and the one lower addend y i _-1 . In the example in Table 1, the values of the carry C _i and the intermediate sum S _i are changed depending on the value of x _i-1 +y _i-1 as the combination of values of the next lower digit. Also, since the carry C _i and the intermediate sum S _i are redundant binary numbers,
Two binary variables are required to represent each value. Therefore, we introduce a binary variable P _i that represents the combination of the addand and the summand, that is, whether x _i + y _i 20 or x _i + Y _i <0,
For example, when x _i + Y _i 0, P _i = 1, and x _i + y _i <
When it is 0, P _i =0. Furthermore, information on carry C i is obtained from the combination variable P _i of the i _- th digit summand and addend, the i-1st digit combination variable P _i-1 , carry C _i and intermediate sum S _i . A variable B _i containing information on the intermediate sum S i and a variable R _i containing information on the intermediate sum S _i are introduced. That is, B _i and
R _i is expressed by the following arithmetic expression: B _i =C _i + _i (1) R _i =S _i +P _i-1 (2). Here, _i indicates the logical inversion of P _i , and when P _i =1, _i =0, and P _i =0
When , _i = 1. Table 1 additionally shows variables P _i , P _i-1 , B _i and R _i for the i-th and i-1-th digit summands and the combinations of the addends. As can be seen from Table 1, the variable B _i containing carry information
and the variable R _i containing intermediate information are binary variables that take only a value of 0 or 1, respectively. Furthermore, the final sum Z _i of the i-th digit can be obtained from the sum of the intermediate sum S _i of the i-th digit and the carry C _i-1 from one lower digit, i.e., the i-1 digit. , (1) and (2), it can be determined as follows. Z _i =S _i +C _i-1 =R _i −P _i-1 +B _i-1 − _i-1 =R _i +B _i-1 −1 ...(3) Here, using identity = 1-A Performing formula transformation. Therefore, the sum Z _i of the i-th digit can be obtained from the binary signals R _i and B _i-1 . Next, the redundant binary numbers, summand x _i , addend y _i and sum
Z _i is encoded into a binary variable as shown in Table 2.

[Table] In Table 2, for example, x _{is is} the sign part of x _i ,
x _ia can be considered as a signal representing the absolute value of x _i . If redundant binary numbers are encoded as shown in Table 2, a combination variable P _i of the i-th digit number x _i and addend y _i , a binary variable B _i containing carry information, an intermediate The binary variable R _i containing the sum information and the final sum Z _i of the i-th digit are:
P _i = _{is is} ( _ia + _ia ) ……(4) B _i = _{is is} (x _ia y _ia )P _i-1 ……(5) R _i =x _ia y _ia P _i-1 ……( 6) Z _is = _{i i-1} ……(7) Z _ia = _i-1 ……(8) is determined by the logical formula. FIG. 1 is a logic circuit diagram showing one embodiment of the present invention, which is constructed using equations (4) to (8). In Figure 1, 101, 105 are OR-
NAND circuit, 102 and 106 are exclusive NOR circuits, 103 is an inverter circuit, 104 is exclusive
The OR circuit and 107 are NAND circuits. In addition, input signals x _is , x _ia , y _is , y _ia and output signals Z _is , Z _ia
are binary signals representing the summand x _i , addend y _i and final sum Z _i of the i-th digit redundant binary number, respectively. The output signal P _i and the input signal P _i-1 are signals representing the combination of the i-th and i-1st digit summand and addend values, respectively, and the sum of the summand and addend is It takes a value of 1 only if it is non-negative. Also, the output signal B _i
and input signal B _i-1 are signals containing carry information of the i-th digit and the i-1-th digit, respectively. Further, the internal signal R _i is a signal containing information on the intermediate division of the i-th digit. In the above example, the variable P _i representing the combination state of the summand and the addend is set to
We have explained the case where P _i = 1 and P _i = 0 when it is negative, but when either the summand or the addend is positive, P _i =
1, and P _i =0 when both are non-positive. The addition rules in this case are as shown in Table 3. At this time, the variable B _i containing the carry information and the signal R _i containing the intermediate sum information are calculated using the formula (1) as in the case of the previous embodiment. and (2), and the values of these binary variables are also shown in Table 3.

[Table] Here, if the redundant binary number is encoded into a binary variable as shown in Table 2 in the same way as in the above embodiment, the i-th digit summand x _i and the addend y _i The combination variable P _i , the binary variable B _i containing carry information, the binary variable R _i containing intermediate sum information, and the final sum Z _i are respectively P _i = _{is is} ... (9) B _i = _{is is} + _{ia ia} + (x _ia y _ia )P _i-1 ...(10) R _i =x _ia y _ia P _i-1 ...(11) Z _is = _{i i-1} ...(12) Z _ia = _{i i-1 .} . . (13) When compared with the previous embodiment, it is completely the same except for the logical expressions for P _i and B _i . FIG. 2 shows a second embodiment constructed from equations (9) to (13). In Figure 2, 201 is a NAND circuit;
202 is an OR-NAND circuit, 203 is an exclusive OR
circuit, 204 is AND-NOR circuit, 205, 20
8 is an exclusive NOR circuit, 206 is a NOR circuit, 20
7 is an inverter circuit. In FIG. 2, the output signal _i and the input signal _i-1 correspond to the circuit diagram of the first embodiment, namely B _i and B _i-1 of FIG. 1, and in this example appear as inverted signals. ing.
Similarly, the internal signal _i corresponds to the inverted signal of R _i in FIG. Furthermore, x _is , x _ia , y _is , y _ia ,
Z _is , Z _ia , P _i and P _i-1 correspond to the respective signals in FIG. In the above two embodiments, the variable P _i representing the combination state of the summand and the addend is set to We have described the method of determination based on the case where at least one of them is positive and the case where both are non-positive, but when the summand and the addend are both non-negative, P _i = 1 and It may be determined that P _i =0 when at least one of the numbers is negative, and in this case as well, the logic can be constructed in the same manner as in the above embodiment. Furthermore, in the embodiment, the redundancy 2
As shown in Table 2, the encoding of base numbers has been explained as {01} for 1, {10} for 0, and {11} for -1, but there are many ways to encode these numbers. but,
The logic can be configured in the same manner as in the previous embodiment. Effects of the Invention According to the present invention, an adder in an arithmetic processing device that uses signed digit representation for internal calculations can be configured with a simple circuit, and the number of delay stages is reduced, so the number of elements in the arithmetic processing device can be reduced. This has the effect of increasing the speed of arithmetic processing.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing a first embodiment of an adder according to the invention, and FIG. 2 is a logic circuit diagram showing a second embodiment of the invention. 101, 105, 202...OR-NAND circuit, 102, 106, 205, 208...exclusive
NOR circuit, 103, 207...inverter circuit,
104,203...Exclusive OR circuit, 107,2
01...NAND circuit, 204...AND-NOR
Circuit, 206...NOR circuit.

Claims (1)

[Claims] 1. In the addition of signed digit numbers, the i-th
a first circuit that outputs a binary signal P _i representing a combination of values from a digit summand and an addend;
i-th digit summand and addend and i-1st lower one
From the binary signal P _i-1 corresponding to the binary signal P _{i of} the digit _, the sum C i + i of the carry C _i of the i-th digit and the logical inversion signal _i of the binary signal P _i or its logic a second circuit that outputs a binary signal B _i represented by inversion;
From the i-th digit summand and addend and the binary signal P _i-1 , the intermediate sum S _i of the i-th digit and the sum S i of the binary signal P _{i- 1}
a third outputting a signed digit signal R _i consisting of at least one binary signal representing a value of +P _i-1;
From only the binary signal B _i-1 of the output of the second circuit of the i-1th digit and the signed digit signal R _i , the intermediate sum S _i of the i-th digit and the i-1th digit are calculated. An adder comprising a fourth circuit for outputting a signed digit signal representing the value of the sum S _i +C _i-1 of the digit carry C i _-1 . 2. The adder according to claim 1, wherein the first circuit outputs a binary signal P _i of 1 or 0 only when the sum of the i-th digit summand and the addend is non-negative. 3. The adder according to claim 1, wherein the first circuit outputs a binary signal P _i of 1 or 0 only when either the i-th digit summand or the addend is positive. . 4. The adder according to claim 1, wherein the first circuit outputs a binary signal of 1 or 0 only when both the i-th digit summand and the addend are non-negative.