JPH05284043A - Linear interpolating method and circuit - Google Patents

Abstract

PURPOSE:To decrease the number of coefficients used for interpolating operation and to reduce the capacity of a ROM with these built-in coefficients by performing the interpolating operation of the next error data by using data already calculated by the interpolating operation after the interpolating operation in the linear interpolating circuit. CONSTITUTION:When performing the interpolating operation in the linear interpolating circuit, the operation is performed by using first-order held data in a shift register 5 for data, data selected from a shift register 1 for data by a selector 4 corresponding to a control signal from a flag decoder 3, and the coefficients built in a ROM 7 decided by the control signal from the flag decoder 3, and this arithmetic result is defined as interpolated data. In the next clock cycle, these interpolated data are temporarily held in the shift register 5 for data, and the next interpolating operation is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing linear interpolation method suitable for digital audio equipment such as a CD player and a circuit thereof.

[0002]

2. Description of the Related Art In the conventional interpolation calculation method of a linear interpolation circuit, if the data error is within n consecutive data, the correct data before and after the consecutive n error data is always used for the calculation. , By changing the multiplication coefficient at the time of calculation,
It is characterized in that the first error data to the nth error data are obtained.

FIG. 3 shows a calculation method of a linear interpolation circuit capable of performing linear interpolation if the number of consecutive data errors is within eight. The calculation method of the conventional interpolation circuit will be described below with reference to FIG.

The operation method when the number of error data (error data number) shown in FIG.

[0005]

[Equation 1]

Therefore, the operation method when the number of error data shown in FIG.

[0007]

[Equation 2]

[0008] In addition, the calculation method when the number of error data shown in FIG. 3C is 9 is to replace the previous correct data with the replaced data (previous value hold data).
Is used to perform the interpolation calculation by using the calculation method shown in FIG.

[0009]

[Equation 3]

FIG. 4 shows an example of the configuration of the linear interpolation circuit in the above conventional case. The configuration of the conventional linear interpolation circuit will be described below with reference to FIG.

In FIG. 4, reference numeral 1 is a data shift register for sequentially shifting the input data 21 of the linear interpolation circuit. Reference numeral 2 is an error flag shift register for sequentially shifting an error flag indicating an error in the input data.
A flag decoder 3 reads the output signal from the error flag shift register 2 and controls each circuit. 4 is 1 out of the output data of the individual stages of the data shift register 1 according to the control signal from the flag decoder 3.
It is a selector to choose one. Reference numeral 5 is a register for temporarily holding the data selected by the first switch 6. 6 selects the output data of the final stage of the data shift register 1 by the control signal from the flag decoder 3 and shifts it to the register 5, or selects the data temporarily held and output by the register 5 and feeds it back to the register 5. It is a first switch for switching whether to input. Reference numeral 7 is a ROM that incorporates coefficients used for interpolation calculation. Reference numeral 8 is a coefficient A built in the ROM 7 which is determined by the data temporarily held by the register 5 and output and the control signal from the flag decoder 3.
It is a first multiplier that performs multiplication with. Reference numeral 9 denotes a second multiplier for multiplying the output data from the selector 4 and the coefficient B contained in the ROM 7 which is determined by the control signal from the flag decoder 3. An adder 10 adds the output data of the first multiplier 8 and the output data of the second multiplier 9. 11 is the output data from the first switch 6 and the adder 10
Is a second switch for switching the output data from the.
Then, the output data from the second switch 11 is used as the output of the entire linear interpolation circuit.

The operation of the linear interpolation circuit configured as described above will be described below with reference to FIG.

In the case of FIG. 3B, when the input data D0 of the linear interpolation circuit is at the final stage of the data shift register 1, an output signal that this data D0 is correct data is output as an error flag shift register 2 Is output to the flag decoder 3, so that the flag decoder 3
The control signal is output to the switch 6 and the second switch 11. With this signal, the first switch 6 selects the output data of the final stage of the data shift register 1, and the second switch 11 selects the output data of the first switch 6.
Further, the register 5 temporarily holds the output data of the final stage of the data shift register in the next clock cycle. The output of the entire linear interpolation circuit at this time is the output data of the final stage of the data shift register (in this case,
The data D0) is output.

Next, when the input data D1 is shifted in the next clock cycle and is in the final stage of the data shift register 1, the error flag shift register 2 outputs an output signal indicating that the data D1 is erroneous data. By outputting to the flag decoder 3, the flag decoder 3 outputs a control signal to the first switch 6 and the second switch 11. This signal causes the first switch 6 to register 5
The data (data D0 in this case) temporarily held by is selected, and the second switch selects the output data from the adder 10. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, the flag decoder 3
From the coefficients stored in the ROM 7, the coefficient A used for the first multiplier 8 (in this case, coefficient A = 8/9) and the coefficient B used for the second multiplier 9 ( In this case, determine the coefficient = 1/9). Then, the first multiplier 8
Is the data temporarily stored in the register 5 and the coefficient A
Then, the second multiplier 9 multiplies the output data (data D9 in this case) of the data shift register 1 selected by the selector 4 and the coefficient B. And
The adder 10 adds the output data of the first multiplier 8 and the output data of the second multiplier 9. Therefore, the output data of the adder 10 is used as the output of the entire linear interpolation circuit. In addition, at this time, the register 5 causes the data (data D in this case) selected by the first switch in the next clock cycle.
0) will be held temporarily.

In the case of FIG. 3C, when all the data in the data shift register 1 are erroneous, the flag decoder 3 causes the first switch 6 and the second switch by the output signal of the error flag shift register 2. The control signal is output to 11. By this signal, the first switch 6 selects the data (in this case, the data D0) temporarily held and output by the register 5, and the second switch 11 selects the output data of the first switch 6. Therefore, the output of the entire linear interpolation circuit at this time is the data temporarily held and output by the register 5. This is an operation of holding the correct data before the erroneous data in the previous value.

[0016]

However, since the number of coefficients used for interpolation calculation is large in the above-mentioned conventional configuration,
There is a problem that the capacity of the ROM incorporating the above coefficient is large.

The present invention solves the above-mentioned conventional problems, and provides a linear interpolation circuit in which the capacity of a ROM containing the above-mentioned coefficient can be significantly reduced by reducing the number of coefficients used for the interpolation calculation. With the goal.

[0018]

In order to achieve this object, the linear interpolation circuit of the present invention, if the data error is within n consecutive data, the first of the consecutive n error data is first described. When performing the interpolation calculation of the above data, the correct data before and after the consecutive n error data are used to perform the calculation, and when performing the interpolation calculation of the second data, it is already obtained by the above interpolation calculation. The first data obtained and the continuous n
The operation is performed using the correct data after the error data. Similarly, when the m-th (m ≦ n) data is interpolated, the m−1-th data already obtained by the above-mentioned interpolating operation and the correct data after the consecutive n error data are calculated. It is configured to be used to perform calculation.

[0019]

With this configuration, the number of coefficients used for the interpolation calculation can be reduced in the interpolation calculation of the linear interpolation circuit of the present invention, so that the capacity of the ROM containing the coefficients used for the interpolation calculation can be reduced.

[0020]

EXAMPLE 1 The configuration of the first example of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram of a linear interpolation circuit in the first embodiment of the present invention. In FIG. 1, the data shift register 1, the error flag shift register 2, the flag decoder 3, the selector 4, the register 5, and the ROM 7 are the same as the conventional configuration. 12 is a flag decoder 3
Select the output data of the final stage of the data shift register 1 and input it to the register 5 by the control signal from, or select the data temporarily held and output in the register 5 and feed it back to the register 5, or , A first switch for selecting whether the output data of the arithmetic unit 13 is selected and input to the register 5. Reference numeral 13 denotes an arithmetic unit that uses the data temporarily held by the register 5 and output and the output data from the selector 4 to perform processing by a predetermined arithmetic operation. Reference numeral 14 is a second switch for switching the output data from the first switch 12 and the output data of the arithmetic unit 13.
The data selected by the second switch 14 is used as the output of the entire linear interpolation circuit. In the arithmetic unit 13, 15 is a first multiplier for multiplying the data temporarily held and output by the register 5 and the coefficient A incorporated in the ROM 7 which is determined by the control signal from the flag decoder 3. Reference numeral 16 is a coefficient B built in the ROM 7 which is determined by the output data from the selector 4 and the control signal from the flag decoder 3.
It is a second multiplier that multiplies with. 17 is the first multiplier
It is an adder that adds the output data from 15 and the output data from the second multiplier 16. The output data from the adder 17 is used as the output of the calculation unit 13.

With respect to the linear interpolation circuit configured as described above, the calculation method and operation will be described with reference to FIG.

FIG. 3 shows a calculation method of a linear interpolation circuit capable of performing linear interpolation if the number of consecutive data errors is within eight. The calculation method of the linear interpolation circuit of the first embodiment is
When the number of error data (the number of error data) shown in FIG. 3A is 1, the calculation method shown in (Equation 1) is used as in the conventional example, and the number of error data shown in FIG. When,

[0024]

[Equation 4]

[0025] When the number of error data shown in FIG. 3C is 9, the previous correct data is replaced and the replaced data (previous value hold data) is used.
Interpolation calculation is performed using the calculation method shown in FIG.

[0026]

[Equation 5]

In the case of FIG. 3B, when the input data D0 of the linear interpolation circuit is at the final stage of the data shift register 1, an output signal that this data D0 is correct data is output as an error flag shift register 2 Is output to the flag decoder 3, so that the flag decoder 3
The control signal is output to the switch 12 and the second switch 14. By this signal, the first switch 12 causes the output data of the final stage of the data shift register 1 (in this case, the data D
0) and the second switch 14 selects the output data from the first switch 12. As a result, the register 5 causes the data shift register 1 in the next clock cycle.
The output data of the final stage of is temporarily retained. The output of the linear interpolation circuit at this time is output data of the final stage of the data shift register 1.

Next, when the input data D1 is shifted in the next clock cycle and is at the final stage of the data shift register 1, the error flag shift register 2 flags an output signal indicating that the data D1 is error data. By outputting to the decoder 3, the flag decoder 3 outputs a control signal to the first switch 12 and the second switch 14. With this signal, the first switch 12 selects the output data of the arithmetic unit 13, and the second switch 14 selects the output data from the arithmetic unit 13. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, according to the control signal from the flag decoder 3, the coefficient A used in the first multiplier 15 (in this case
The coefficient A = 8/9) and the coefficient B (in this case coefficient = 1/9) used for the second multiplier 16 are determined. And the first multiplier
Reference numeral 15 multiplies the data temporarily stored in the register 5 and output (data D0 in this case) by the coefficient A, and the second multiplier 16 outputs the output data of the data shift register 1 selected by the selector 4 (this Case Data D9) is multiplied by coefficient B. The output data of the data shift register 1 selected by the selector 4 is always correct data after n consecutive error data. Then, the adder 17 adds the output data of the first multiplier 15 and the output data of the second multiplier 16. Therefore, the output data of the adder 17 is used as the output of the entire linear interpolation circuit. Also at this time,
In the next clock cycle, the register 5 temporarily holds the data selected by the first switch, that is, the output data of the calculation unit 13 (in this case, the interpolation data D1).

Further, when the input data D2 is shifted in the clock cycle and is in the final stage of the data shift register 1, this data D2 is the same as when the input data D1 is in the final stage of the data shift register 1. When the error flag shift register 2 outputs an output signal indicating that the data is error data to the flag decoder 3, the flag decoder 3 outputs a control signal to the first switch 12 and the second switch 14. This signal causes the first switch
The second switch 14 selects the output data of the calculation unit 13, and the second switch 14
Selects the output data from the calculation unit 13. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, the ROM 7 is controlled by the control signal from the flag decoder 3.
The coefficient A used in the first multiplier 15 (in this case, coefficient A = 7/8) and the coefficient B used in the second multiplier 16 (in this case, coefficient = 1/8) ) Is determined. Then, the first multiplier 15 multiplies the data temporarily stored in the register 5 and output (in this case, the interpolated data D1) by the coefficient A, and the second multiplier 16 for the data selected by the selector 4. The output data of the shift register 1 (data D9 in this case) and the coefficient B are multiplied. Then, the adder 17 adds the output data of the first multiplier 15 and the output data of the second multiplier 16. Therefore, the output data of the adder 17 is used as the output of the entire linear interpolation circuit. Also at this time,
In the next clock cycle, the register 5 temporarily holds the data selected by the first switch, that is, the output data of the calculation unit 13 (in this case, the interpolation data D2).

Thereafter, the same operation is sequentially repeated, and finally all eight consecutive error data are interpolated.

In the case of FIG. 3 (c), when all the data in the data shift register 1 are erroneous, the flag decoder 3 causes the first switch 12 and the second switch to operate in accordance with the output signal of the error flag shift register 2. The control signal is output to 14. By this signal, the first switch 12 selects the data (data D0 in this case) temporarily held and output by the register 5, and the second switch 14 selects the output data from the first switch 12. Therefore, the output of the entire linear interpolation circuit at this time is the data temporarily held and output by the register 5. This means that the correct data before the error is held in the previous value. Then, using this previous value hold data, interpolation is performed using the same calculation method as in the case of FIG.

Table 1 compares the number of coefficients used in the interpolation calculation of the linear interpolation circuit in the case of this embodiment and the conventional case.

[0033]

[Table 1]

As is clear from this (Table 1), the first
Since the linear interpolation circuit in the case of the embodiment can make the number of coefficients used for the interpolation calculation equal to or smaller than that in the conventional case, an excellent effect can be obtained in that the capacity of the ROM containing the above-mentioned coefficients can be reduced.

(Embodiment 2) The structure of the second embodiment of the present invention will be described below with reference to FIG.

FIG. 2 is a block diagram of a linear interpolation circuit in the second embodiment of the present invention. 2, the data shift register 1, the error flag shift register 2, the flag decoder 3, the selector 4, the register 5, the ROM 7, the first switch 12, and the second switch 14 are the same as those in the configuration of FIG. .. The difference from the configuration of FIG. 1 is an arithmetic unit 13, and in the arithmetic unit 13, reference numeral 18 is a subtracter for subtracting the data temporarily held by the register 5 and output from the output data from the selector 4. Reference numeral 19 denotes a multiplier for multiplying the output data from the subtracter 18 and the coefficient A built in the ROM 7 which is determined by the control signal from the flag decoder 3. An adder 20 adds the output data from the multiplier 19 and the output data temporarily held and output by the register 5. The output data from the adder 20 is used as the output of the calculation unit 13.

With respect to the linear interpolation circuit configured as described above, the calculation method and operation will be described with reference to FIG.

FIG. 3 shows a calculation method of a linear interpolation circuit capable of linear interpolation if the number of consecutive data errors is within eight. The method of calculating the interpolation data in the case of the second embodiment is such that when the number of error data (error data number) shown in FIG.

[0039]

[Equation 6]

When the number of error data shown in FIG. 3 (b) is 8,

[0041]

[Equation 7]

It becomes When the number of error data shown in FIG. 3C is 9, the previous correct data is replaced and the replaced data (previous value hold data) is used.
Interpolation calculation is performed using the calculation method shown in FIG.

[0043]

[Equation 8]

In the case of FIG. 3B, when the input data D0 of the linear interpolation circuit is at the final stage of the data shift register 1, an output signal indicating that this data D0 is correct data is output as the error flag shift register 2 Is output to the flag decoder 3, so that the flag decoder 3
The control is output to the switch 12 and the second switch 14. By this signal, the first switch 12 causes the output data of the final stage of the data shift register 1 (data D0 in this case).
And the second switch 14 selects the output data of the first switch 12. As a result, the register 5 temporarily holds the output data of the final stage of the data shift register 1 at the next clock. The output of the entire linear interpolation circuit at this time is output data of the final stage of the data shift register 1.

Next, when the input data D1 is shifted in the next clock cycle and is at the final stage of the data shift register 1, the error flag shift register 2 flags an output signal indicating that the data D1 is error data. By outputting to the decoder 3, the flag decoder 3 outputs a control signal to the first switch 12 and the second switch 14. With this signal, the first switch 12 selects the output data of the arithmetic unit 13, and the second switch 14 selects the output data from the arithmetic unit 13. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, according to the control signal from the flag decoder 3, a coefficient A used in the multiplier 19 (coefficient A = 1 in this case) is selected from the coefficients stored in the ROM 7.
/ 9). Then, the subtracter 18 subtracts the data (data D0 in this case) temporarily held by the register 5 from the output data (data D9 in this case) of the data shift register 1 selected by the selector 4. The output data of the data shift register 1 selected by the selector 4 is always correct data after n consecutive error data. Then, the multiplier 15 multiplies the output data of the subtractor 18 by the coefficient A. Then, the adder 20 adds the output data of the multiplier 15 and the data temporarily held and output by the register 5. Therefore, the output data of the adder 20 is used as the output of the entire linear interpolation circuit.
Further, the register 5 has the first clock in the next clock cycle.
Data selected by the switch, that is, the calculation unit
The 13 output data (in this case, interpolation data D2) will be temporarily held.

Further, when the input data D2 is shifted in the clock cycle and is in the final stage of the data shift register 1, this data D2 is the same as when the input data D1 is in the final stage of the data shift register 1. When the error flag shift register 2 outputs an output signal indicating that the data is error data to the flag decoder 3, the flag decoder 3 outputs a control signal to the first switch 12 and the second switch 14. This signal causes the first switch
The second switch 14 selects the output data of the calculation unit 13, and the second switch 14
Selects the output data from the calculation unit 13. Therefore, the output of the entire linear interpolation circuit at this time is as follows. First, the ROM 7 is controlled by the control signal from the flag decoder 3.
The coefficient A used for the multiplier 19 from the coefficients built in
(Coefficient A = 1/8 in this case) is determined. And the subtractor 18
Is the data (in this case, data) temporarily held by the register 5 and output from the output data (data D9 in this case) of the data shift register 1 selected by the selector 4.
The interpolation data D1) is subtracted. Then, the multiplier 15 multiplies the output data of the subtractor 18 by the coefficient A. Then, the adder 20 adds the output data of the multiplier 15 and the data temporarily held and output by the register 5. Therefore, the output data of the adder 20 is used as the output of the entire linear interpolation circuit.
Further, the register 5 has the first clock in the next clock cycle.
Data selected by the switch, that is, the calculation unit
The 13 output data (in this case, interpolation data D1) will be held temporarily.

Thereafter, the same operation is sequentially repeated, and finally all eight consecutive error data are interpolated.

In the case of FIG. 3C, when all the data in the data shift register 1 are erroneous, the flag decoder 3 causes the first switch 12 and the second switch by the output signal of the error flag shift register 2. The control signal is output to 14. By this signal, the first switch 12 selects the data temporarily held and output by the register 5, and the second switch 14 selects the output data of the first switch 12. Therefore, the output of the entire linear interpolation circuit at this time is the data temporarily held and output by the register 5. This means that the correct data before the error is held in the previous value. Then, using this previous value hold data, interpolation is performed using the same calculation method as in the case of FIG.

As described above, by configuring the circuit of the operation unit 13, the comparison of the number of coefficients used in the interpolation operation of the linear interpolation circuit in the case of the present embodiment of the above (Table 1) and the conventional case is performed. Obviously, the linear interpolation circuit in the case of the second embodiment can make the number of coefficients used for the interpolation calculation equal to or smaller than that in the conventional case.
An excellent effect is obtained in that the capacity of the OM can be significantly reduced. In addition, the second embodiment can obtain an effect superior to that of the first embodiment.

[0050]

As described above, in the linear interpolation circuit according to the present invention, when the error of data is within n consecutive data, when the first data of the consecutive n error data is interpolated first. Performs an operation using correct data before and after the consecutive n error data, and when the second data is interpolated next, 1 is already obtained by the interpolated operation.
An operation is performed using the correct data after the nth data and the above-mentioned n consecutive error data. Similarly, the m-th item (m ≦
When performing the interpolation calculation of the data of n), the calculation is performed by using the m-1th data already obtained by the interpolation calculation and the correct data after the continuous n error data. Has been done.

With the above construction, the linear interpolation circuit of the present invention can reduce the number of coefficients used for the interpolation calculation, so that the capacity of the ROM containing the coefficients used for the interpolation calculation can be reduced, and the excellent linear interpolation circuit can be used. The interpolation circuit can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a linear interpolation circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a linear interpolation circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a calculation method of linear interpolation for explaining the operation of the linear interpolation circuit in the first embodiment, the second embodiment, and the conventional example.

FIG. 4 is a block diagram of a conventional linear interpolation circuit.

[Explanation of symbols]

 1 Data shift register 2 Error flag shift register 3 Flag decoder 4 Selector 5 Register 6, 11, 12, 14 Switch 7 ROM 8, 9, 15, 16, 19 Multiplier 10, 17, 20 Adder 18 Subtractor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeyuki Takayama 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (5)

[Claims] 1. In a linear interpolation circuit, when performing interpolation calculation of consecutive n or more error data, first, n
Using the correct two data before and after each error data,
Only the interpolation calculation of the error data adjacent to the correct data is performed, the data obtained by the above-mentioned interpolation calculation is treated as the correct data, and the interpolation calculation of the remaining consecutive n-1 error data is performed again. By using the correct two data before and after the n-1 error data, only the interpolation calculation of the error data adjacent to the correct data is performed, and then the same calculation is repeated sequentially to finally obtain n consecutive errors. A linear interpolation method characterized by interpolating all data. 2. In a linear interpolation circuit, if the number of consecutive data errors is within n, when the first data of the consecutive n error data is first interpolated, the above-mentioned consecutive n data is generated. When using the correct data before and after the error data of, and then interpolating the second data, the first data already obtained by the above interpolating operation and the continuous n data When the m-th (m ≦ n) data is similarly interpolated using the correct data after the erroneous data, the m already obtained by the above-mentioned interpolating
2. The linear interpolation method according to claim 1, wherein the -1st data and the correct data after the continuous n error data are used for the calculation. 3. A data shift register for sequentially shifting input data of the linear interpolation circuit and an error flag shift register for sequentially shifting an error flag indicating an error in the input data when configuring the linear interpolation circuit. And a flag decoder that reads the output signal from the error flag shift register and controls individual circuits,
A selector that selects one of the output data of the individual stages of the data shift register according to a control signal from the flag decoder, a register that temporarily holds the data selected by the first switch, and the flag decoder The output signal of the final stage of the data shift register is selected and input to the register by the control signal of, or the data temporarily held and output by the register is selected and fed back to be input to the register, or An arithmetic operation for performing a predetermined arithmetic operation using a first switch for selecting whether arithmetic unit output data is to be input to the register, and output data from the first switch and output data from the selector. Section and output data from the first switch according to a control signal from the flag decoder. A second switch for switching between selection and selection of the arithmetic unit output data, and the data output from the second switch is output data of the entire linear interpolation circuit. A linear interpolation circuit based on the linear interpolation method according to claim 2. 4. A first multiplier that multiplies data temporarily held and output by the register and a coefficient determined by a control signal from the flag decoder when configuring the arithmetic unit, and the selector. Output data from the first multiplier and output data from the second multiplier for multiplying the output data from the first multiplier with a coefficient determined by a control signal from the flag decoder. The arithmetic unit according to claim 3, further comprising an adder for adding, and the data output from the adder is used as output data of the arithmetic unit. 5. A subtracter for subtracting the data temporarily held and output by the register from the output data from the selector, the output data from the subtractor, and the flag decoder when configuring the arithmetic unit. Output from the adder, which includes a multiplier that multiplies with a coefficient determined by the control signal of 1), and an adder that adds the data temporarily held and output by the register and the output data from the multiplier. The arithmetic unit according to claim 3, wherein the data is output data of the arithmetic unit.