JPH0528396B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image information processing device applied to computer graphic display devices and the like.

[Conventional technology]

Conventionally, this type of image information processing device includes a display memory that stores image information to be displayed, and each address of the memory stores each image information transferred from a central processing unit (hereinafter referred to as CPU) of a computer, i.e. Some of the plurality of minimum pixel unit information forming one display screen, that is, one image information consisting of one word, are each stored, and each image is transferred from the display memory during one display period consisting of one field period or one frame period, etc. Information is read out sequentially.

In order to display one screen based on one screen's worth of image information read from the display memory on a display unit such as a CRT, each read image information is temporarily held in a shift register or the like and displayed. It is necessary to sequentially output each minimum pixel unit information in synchronization with scanning, and for this reason, computer graphic display devices equipped with this type of image information processing device usually have an address counter and strobe signal as well as a display memory. It is equipped with a control signal generation circuit that generates various control signals such as.

By the way, in a normal display memory, only read access, that is, read access, is performed during each display period including the retrace period, and write access,
In other words, since write access is prohibited, it is necessary to update the contents of the display memory by rewriting, that is, to draw, during a period other than the display period.
In this case, read access to the display memory for a relatively long time for drawing is prohibited, resulting in a long so-called waiting time.

Therefore, it was devised to reduce the above-mentioned waiting time by drawing in the display memory between displays such as the retrace period during each display period, reducing the drawing time and reducing the above-mentioned waiting time. ASCII,
Vol. 7, #8 August 1983), pages 151-152, describes an access method in which one character time is time-divided into CRT access and CPU access.

In addition, a method has been proposed in which the display memory is accessed and drawn using a read-modify-write access only during the blanking period, that is, an access method that controls writing immediately after reading. If an address other than the read-accessed address is accessed by the CPU or the like, the display cycle of the display memory is interrupted and the screen of the display section becomes disordered, so the read-modify-write access is performed only during the retrace period.

[Problem that the invention seeks to solve]

However, even if drawing is performed in the display memory during intervals between displays such as blanking periods as described above, the period during which image information can be written into the display memory is limited to a very short time between the displays. During this time, for example, it is necessary to transfer image information from the CPU to the display memory, so only a few addresses worth of image information can be transferred in one transfer, and it takes at least a period longer than one display period to finish drawing in the display memory. As the drawing period becomes longer,
During this time, there is a problem that the CPU cannot perform other processing.

Furthermore, if several display periods are required to complete the drawing in the display memory, there is a problem in that an unnecessary screen is displayed in the middle of drawing, making the display unsightly.

In addition, there is a problem in that it takes a longer drawing time to draw image information that is a composite of the image information read from each address and new image information at some or all addresses in the display memory. .

[Means for solving problems]

The present invention includes a display memory that stores image information to be displayed, and in which each address is controlled to be written immediately after each address is read by read-modify-write access during a display period; An auxiliary memory into which information is written and from which image information written in synchronization with the display memory is read after completion of writing, and a sum, product, etc. of the image information read from both memories are stored in the display memory. an arithmetic processing unit that performs logical arithmetic processing and outputs arithmetic image information based on the processing from reading to writing immediately after the reading; The image information processing apparatus is characterized by comprising an image information selection output section that outputs the image information read from the memory or the calculated image information to the display memory or the auxiliary memory.

[Effect]

Then, the auxiliary memory operates like a buffer memory for the display memory, and at this time, image information is written to the auxiliary memory regardless of the display cycle of the display memory. The image information will be transferred to the auxiliary memory.

Immediately after each address of the display memory is read, the image information read from each address, the image information read from the auxiliary memory, or the calculated image information formed by the calculation process of both image information read out. is written, and drawing in the display memory is performed at the same time as reading out the display memory. In this case, within one display period of the display memory, all or part of the address of the display memory is updated to new image information based on the image information of the auxiliary memory. , the image information in the display memory and the image information in the auxiliary memory are rewritten into image information that is a composite of the image information, and in any case, the drawing in the display memory is completed within one display period.

〔Example〕

Next, the present invention will be described in detail with reference to drawings showing one embodiment thereof.

In FIG. 1, 1 is a central processing unit of a computer, that is, a CPU, and 2 is an address counter and control signal generation circuit. The control signal generation circuit includes an address counter that outputs an address signal (referred to as an address), and a control signal generation circuit that outputs various control signals such as a write inhibit signal, that is, a write enable signal, for the display memory.

3 is an address selector which selectively selects the CPU address signal inputted from the CPU 1 via the address bus 4 and the counter address signal and control signal inputted from the generation circuit 2 via the address bus 6, 7 respectively.

Reference numerals 8a, 8b, and 8c are first to third display memories accessed by address signals from the address bus 6, which store at least one field or one frame of color image information to be displayed.
It consists of a D-RAM with a capacity to store data for each primary color. For example, when each image information is formed by 8 bits of three primary color data, the display memory 8a stores 8 bits for red, and the display memories 8b and 8c store 8 bits for green. , yellow 8 bits are stored respectively.

Reference numerals 9a, 9b, and 9c are first to fourth auxiliary memories that are accessed by address signals from the address bus 7, and are composed of D-RAMs each having a capacity equal to or less than that of each display memory 8a to 8c, and store image information in the display memory. 8a to 8c are stored separately for the three primary colors.

10a, 10b, and 10c are display side first terminals connected to the CPU 1 via a bidirectional data bus 11.
to tertiary buffers, each consisting of 3-state buffers. 12a, 12b, 12c are the first to third latches on the display side; 13a, 13b, 1
3c is the first to third arithmetic circuits connected to each latch 12a to 12c via data buses 14a, 14b, and 14c, and 15a is data interposed between the display memory 8a, buffer 10a, latch 12a, and arithmetic circuit 13a. bus, 15b is display memory 8
b, buffer 10b, latch 12b, arithmetic circuit 1
A data bus 15c is interposed between the display memory 8c, the buffer 10c, the latch 12c, and the arithmetic circuit 13c.

16a, 16b, 16c are data buses 15a~
The first to third shift registers are connected to each of the shift registers 15c and convert input parallel data into serial data, respectively, and form a display section.
The three primary color image signals formed by the conversion are sequentially output to the CRT 17.

18a, 18b, 18c are the first to third auxiliary side connected to the CPU 1 via the data bus 11.
Each buffer consists of 3 state buffers. 19a, 19b, 19c are data bus 2
Arithmetic circuits 14a~ through 0a, 20b, 20c
14c are connected to the auxiliary side first to third latches, 21a is the auxiliary memory 9a, and the arithmetic circuit 1.
3a, a data bus interposed between the buffer 18a and the latch 19a; 21b, the data bus interposed between the auxiliary memory 9b, the arithmetic circuit 13b, the buffer 18b, and the latch 19b; 21c, the auxiliary memory 9;
c, arithmetic circuit 13c, buffer 18c, latch 1
9c.

22 is a data analysis circuit to which data of the data buses 14a to 14c and data buses 20a to 20c is input, and forms an arithmetic processing section together with the arithmetic circuits 13a to 13c.
Control information is output to the arithmetic circuits 13a to 13c via the circuits b and 23c.

Note that the arithmetic circuits 13a to 13c also form an image information selection output section.

The display memories 8a to 8c receive a counter address signal from the generation circuit 2 via the address selector 3 during the display period, and based on the row address and column address in the counter address signal, each of the display memories 8a to 8c The address is accessed, and the image information for each primary color stored in each address is read out to the registers 16a to 16c, and from each register 16a to 16c, the CRT 17
Three primary color image signals based on the image information for each of the primary colors are output, and a cow screen based on the three primary color image signals is displayed on the CRT 17.

Note that during periods other than the retrace period during the display period, the buffers 10a to 10c are controlled to high impedance, and the data bus 11 and the display memories 8a to 8c are disconnected, so that the CPU 1 of the display memories 8a to 8c
Writing by is prohibited.

Also, when writing by CPU1,
During the retrace period during the display period, the display memories 8a to 8c
from CPU1 via address selector 3 to
A CPU address signal is input, each address of the display memories 8a to 8c is accessed by the row address and column address in the CPU address signal, and a buffer 1 is stored in the display memories 8a to 8c.
Image information from the CPU 1 via 0a to 10c is input for each primary color, and the display memories 8a to 8c are
Written by CPU1.

On the other hand, the auxiliary memories 9a to 9c normally receive a CPU address signal from the CPU 1 via the address selector 3, and each address is accessed by the row address and column address in the CPU address signal. 18
Image information from the CPU 1 via c is input for each primary color.

Therefore, the auxiliary memories 9a to 9c are the display memory 8.
Also during the display period of a to 8c, the display memories 8a to 8
Image information from the CPU 1 is asynchronously written to c for each primary color.

After the writing to the auxiliary memories 9a to 9c is completed, the image information in the auxiliary memories 9a to 9c or the image information obtained by combining the image information in the display memories 8a to 8c and the image information in the auxiliary memories 9a to 9c is divided into primary colors. When transferring to display memories 8a to 8c,
That is, when the image information in the auxiliary memories 9a to 9c is reflected on the display memories 8a to 8c, the auxiliary memories 9a to 9c are accessed by the counter address signal of the generation circuit 2 via the address selector 3 during the display period, and the buffer is 18a-18c
becomes high impedance and disconnects between the CPU 1 and the auxiliary memories 9a to 9c.

Therefore, by the counter address signal of the generation circuit 2, the display memories 8a to 8c and the auxiliary memories 9a to 9 are
At this time, both memories 8a to 8c and 9a to 9c are controlled to be written in immediately after each address is read by read-modify-write access.

The image information for each primary color read from each address of the display memories 8a to 8c is transferred to the latch 12a.
12c, the image information for each primary color is input to the data analysis circuit 22 and to the arithmetic circuits 13a to 13c, respectively, and similarly read from each address of the auxiliary memories 9a to 9c. ~19c, data analysis circuit 2
2 and the arithmetic circuits 13a to 13c.
are input respectively.

Furthermore, the analysis circuit 22 includes display memories 8a to 8.
calculation processing such as the sum and product of the three primary color information input simultaneously from the auxiliary memories 9a to 9c, or calculation processing such as the sum and product of the three primary color information input simultaneously from the auxiliary memories 9a to 9c; The arithmetic circuit 1 performs arithmetic processing such as the sum and product of the information on each primary color and the information on each primary color in the auxiliary memories 9a to 9c.
Control information such as bit conversion and output selection is output to 3a to 13c, respectively.

Based on the control information, each arithmetic circuit 13a
~13c converts some or all bits of the image information for each primary color inputted from the display memories 8a~8c into values of some or all bits for the image information for each primary color inputted from the auxiliary memories 9a~9c. The display memory 8 stores the first calculation image information for each primary color that has been replaced by
Second calculation image information for each primary color is formed by replacing some or all of the bit values of the image information for each primary color input from a to 8c. In addition, the first and second
In some cases, computed image information of two types is simultaneously formed.

Furthermore, when each address of the display memories 8a to 8c is written, based on the control information, each calculation circuit 13a to 13c writes the first calculation image information for each primary color that has been formed or the primary color input from the display memories 8a to 8c. Other image information or auxiliary memory 9
The image information for each primary color input from a to 9c is output to the data buses 15a to 15c, respectively, and the second calculation image information or data bus 15
One of the remaining two pieces of image information for each primary color that were not output to a to 15c is output to data buses 21a to 21c, respectively.

Therefore, each address of the display memories 8a to 8c is
During the display period in which writing is conventionally prohibited, image information for each primary color of the data buses 15a to 15c is written immediately after reading by read modify write access, and each address of the display memory 8a to 8c is written within one display period. The rewriting of is completed.

Further, image information for each primary color of the data buses 15a to 15c is stored in shift registers 16a to 16c.
During one display period while the display memories 8a to 8c are being rewritten, a color screen based on the image information being rewritten is displayed in the display memory 8 on the CRT 17.
A to 8c are displayed in the same way as when displaying a color screen based on the read image information. Note that the load clocks for each of the shift registers 16a-16c are formed by a write inhibit signal to be described later for each of the display memories 8a-8c or a separately inputted clock signal.

On the other hand, rewriting of the auxiliary memories 9a to 9c also ends in one display period, similarly to the display memories 8a to 8c.

By the way, the operation timing during the above-mentioned read-modify-write access will be explained next.

That is, the display memories 8a to 8c during read modify write access are set with a row address input period Ta and a column address input period Tb as shown in FIG.
The row address RA and column address of c in the same figure are
Capture CA sequentially and capture row address
The address based on RA and column address CA is accessed.

And row address RA, column address CA
For example, the display memory 8a accessed by
During reading based on the access, the output prohibition is canceled at Tc as shown in Figure 2 d, and at this time, for example, the red color is output from the address accessed by the row address RA and column address CA as shown in Figure 2 The image information Da of is read out,
Immediately after reading the image information Da, the red image information Db of the data bus 15a is written to the address.

Furthermore, when the image information Da is output to the data bus 15a, the latch 12a receives a latch signal as shown in FIG. 2f, and latches the image information Da as shown in FIG. and output it.

Furthermore, while the image information Da is output from the latch 12a, the control information Dc is output from the analysis circuit 22 to the arithmetic circuit 13a as shown in FIG. 2h, and the operation of the arithmetic circuit 13a based on the control information Dc , the image information Db to be written to the read address of the display memory 8a is transferred to the data bus 15a.
is output to.

Furthermore, during the period Td while the image information Db is being output, a second
As shown in FIG.
Image information Db is written to.

Note that FIGS. 2d and 2i show an output inhibit signal that inhibits reading and a write inhibit signal that inhibits writing when the logic is 1 (hereinafter referred to as "1").

The display memories 8b and 8c are also subjected to the timing control shown in FIG. 2 a to i, and the auxiliary memories 9a to 9c are timing controlled in synchronization with the display memories 8a to 8c.

By the way, the first and second arithmetic image information formed based on the arithmetic processing of the analysis circuit 22 is based on the arithmetic processing method, and some or all of the image information in the display memories 8a to 8c is stored in the auxiliary memories 9a to 9a. 9
The image information that has been changed to part or all of the image information of c, or the second image information that has changed part or all of the image information of the auxiliary memories 9a to 9c to part or all of the image information of the display memories 8a to 8c. The image information is a combination of the calculated image information or some or all of the image information in the display memories 8a to 8c and some or all of the image information in the auxiliary memories 9a to 9c.

For example, image information for each primary color is formed from 8-bit data for each primary color, and the image information is stored in the display memory 8a.
Image information Dα read out simultaneously from ~8c,
Dβ, Dγ are the data in FIG. 3a, auxiliary memory 9a~
Image information Dx, Dy, read simultaneously from 9c
When Dz is the data in b of the same figure, each information Dα, Dβ,
The value of the bit of Dγ that becomes logical 0 (hereinafter referred to as "0") at the same time, and the value of the bit of each primary color image information Dx, Dy, Dz of the same figure b read out from the auxiliary memories 9a to 9c. When the control information for exchanging and forming the first and second calculation image information is output, the first
The calculated image information is the image information Dα′, Dβ′,
Dγ', and the second calculated image information becomes the image information Dx', Dy', Dz' of b in the figure. In addition, MSB in the figure,
LSB indicates the most significant bit and the least significant bit, respectively.

The first calculated image information Dα', Dβ', and Dγ' are transferred to the display memories 8a to 8c, respectively, and the second calculated image information Dx', Dy', and Dz' are transferred to the auxiliary memories 9a to 9.
By transferring each to the display memory 8
The contents of a to 8c are the first calculation image information in Fig. 3a.
At the same time, the contents of the auxiliary memories 9a to 9c are rewritten to the second calculated image information Dx', Dy', Dz' shown in FIG. The image information becomes image information in which some of the bits are changed to the values of the bits in the auxiliary memories 9a to 9c.

This means that, for example, the image information Dx,
This corresponds to the case where the screen of the blank part in Dy and Dz is inserted.

Furthermore, when the image information is formed of 8-bit data for each primary color, and the information Dα, Dβ, and Dγ are the data shown in Figure 4 a, and the information Dx, Dy, and Dz are the data shown in Figure 4 b, the information Dx, Dy , Dz is not "0", the bits of the information Dα, Dβ, Dγ corresponding to the bits of the information data Dx, Dy, Dz are set to the corresponding bits of the information Dx, Dy, Dz. When the control information for forming the calculated image information by inserting the respective values is output, the first calculated image information becomes the calculated image information Dα'', Dβ'', and Dγ'' shown in a of FIG.

Then, when the first calculation image information Dα'', Dβ'', and Dγ'' are transferred to the display memories 8a to 8c, and the information Dx, Dy, and Dz are transferred to the auxiliary memories 9a to 9c, respectively, the display memories 8a to 8c are The contents are the first calculation image information Dα'', Dβ'', shown in Figure 4a.
Dγ'', and the contents of the auxiliary memories 9a to 9c are retained as information Dx, Dy, and Dz shown in FIG.

This can be done by, for example, deleting a part of the color screen based on the image information Dα, Dβ, Dγ of the display memories 8a to 8c, and
This corresponds to the case where a screen corresponding to the part of Dx, Dy, and Dz is inserted.

Then, by the read-modify-write access, each address of the display memories 8a to 8c is immediately loaded with the first or second calculation image information or the display memory 8a.
Since the image information read from each address of ~8c or the image information read from the same address of the auxiliary memories 9a~9c is written, the drawing in the display memories 8a~8c is
It ends in one display period consisting of one field period or one frame period.

Further, during one display period during drawing in the display memories 8a to 8c, 1 is drawn in the display memories 8a to 8c.
A color screen based on image information for a field or one frame is displayed on the CRT 17 as the display memories 8a to 8c are accessed, and in this case, the drawing is completed in one display period, so auxiliary memories 9a to 9c are provided. For example, the display memories 8a to 8c are accessed by the CPU 1 during the retrace period of the display memories 8a to 8c, and the display memories 8a to 8c are
There is no need to display an unnecessary color screen in the middle of drawing, as in the case where drawing ends in a period longer than one display period.

Moreover, at the same time as drawing in the display memories 8a to 8c,
Display memories 8a to 8c are included in auxiliary memories 9a to 9c.
For example, by drawing the first or second calculated image information that was not drawn in the display memory 8a to 8c, or the image information read from the display memories 8a to 8c, or the image information read from the auxiliary memories 9a to 9c, By drawing the image information read from the display memories 8a to 8c, it becomes possible to restore the image information in the display memories 8a to 8c to the original values again in the next one display period.

By the way, if image information that is not a repeating pattern is to be drawn in each primary color in the display memories 8a to 8c, the capacity of the auxiliary memories 9a to 9c must be equal to one frame or one field.
When image information of a repeating pattern is drawn in each primary color, the capacity of the auxiliary memories 9a to 9c can be made large enough to store one unit of image information of the repeating pattern, and the auxiliary memories 9a to 9c can be made smaller. can do. In this case, the display memory 8a
The auxiliary memories 9a to 9 are read out in synchronization with the reading of ~8c.
It is necessary to repeatedly read each address of c and to prohibit drawing in the auxiliary memories 9a to 9c.

In the above embodiment, the color screen is CRT17.
Three display memories for each primary color 8
A to 8c were installed, but for example, a black and white screen could be replaced with a CRT.
17, only one display memory is required, and in this case, only one auxiliary memory is required. Also,
Of course, the present invention can also be applied when the number of display memories 8a to 8c is two, four or more.

Furthermore, in order to perform read-modify-write access, the counter address signal of the generation circuit 2 is shared for accessing the display memories 8a to 8c and the auxiliary memories 9a to 9c. Access may be provided by a separate address generator that outputs an address signal synchronized with the counter address signal.

〔Effect of the invention〕

Therefore, according to the image information processing device of the present invention, for example, image information can be transferred from the CPU to the auxiliary memory asynchronously to the display memory during the display period of the display memory, and the calculated image information or Since the drawing of the image information read from the display memory or the image information read from the auxiliary memory is completed within one display period in any case, the drawing of the display memory can be performed at extremely high speed. For example, the CPU is used for transferring image information for a shorter time than in the past, allowing other processing to be performed during the remaining time, and unnecessary display of the screen during drawing can be prevented.

Furthermore, in this embodiment, since drawing is performed in the auxiliary memory at the same time as drawing in the display memory, the image information in the display memory can be restored to its original state by, for example, drawing the image information read from the display memory in the auxiliary memory. It can be done in a short time.

[Brief explanation of drawings]

The drawings show one embodiment of the image information processing apparatus of the present invention, in which FIG. 1 is a block diagram, FIGS. 2 a to i are timing charts for explaining operation, and FIGS. 3 a and b are explanations of one example of arithmetic processing. 4A and 4B are explanatory diagrams of other examples of arithmetic processing. 1...CPU, 2...Address counter and control signal generation circuit, 3...Address selector, 8
a, 8b, 8c...first to third display memory,
9a, 9b, 9c...first to third auxiliary memory, 10a, 10b, 10c...display side first to third buffer, 12a, 12b, 12c...display side first to third latch, 13a, 13b ,1
3c...first to third arithmetic circuits, 16a, 16
b, 16c...first to third shift registers,
17...CRT, 18a, 18b, 18c...Auxiliary side first to third buffer, 19a, 19b,
19c...Auxiliary side first to third latch, 22...
...Data analysis circuit.

Claims (1)

[Claims] 1 A display memory that stores image information to be displayed and controls each address to write immediately after each address is read by read-modify-write access during a display period, and image information is written to the display memory asynchronously. At the same time, after the writing is completed, the image information written in the display memory is read out in synchronization with the auxiliary memory, and the sum, product, etc. of the image information read out from both memories are read from the display memory. an arithmetic processing section that performs logical arithmetic processing and forms arithmetic image information based on the processing before it is controlled to write immediately after reading; An image information processing device comprising: an image information selection output unit that outputs the output image information or the calculated image information to the display memory or the auxiliary memory.