JPH05283558A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH05283558A
JPH05283558A JP4110688A JP11068892A JPH05283558A JP H05283558 A JPH05283558 A JP H05283558A JP 4110688 A JP4110688 A JP 4110688A JP 11068892 A JP11068892 A JP 11068892A JP H05283558 A JPH05283558 A JP H05283558A
Authority
JP
Japan
Prior art keywords
resin
stress
lead frame
semiconductor device
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4110688A
Other languages
Japanese (ja)
Inventor
Shohei Okazaki
祥平 岡崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4110688A priority Critical patent/JPH05283558A/en
Publication of JPH05283558A publication Critical patent/JPH05283558A/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To buffer a stress from a lead frame to sealing resin by providing stress buffer film at corners to be formed at an island and a cut edge of a stitch of the frame. CONSTITUTION:A lead frame 1 is patterned in a predetermined shape by stamping with a press machine or etching a thin plate of nickel and iron alloy, copper material, etc. Corners 1a to be formed at front, rear and side faces of an island 2 to be placed with an integrated circuit chip and further front, rear and side faces of a stitch 3 to be bonded to the chip are covered with stress buffer films 5 in a range of a resin sealing region 4. Thus, after resin sealing, a stress generated due to a difference of thermal expansion coefficients between the frame 1 and sealing resin is alleviated by the film 5, and the stress is not applied directly to the resin, and hence a semiconductor device in which a crack can be prevented and which has high reliability can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、樹脂封止型半導体装置
に関し、特に半導体装置のリードフレームに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a lead frame for a semiconductor device.

【0002】[0002]

【従来の技術】従来の樹脂封止型半導体装置のリードフ
レームは、ニッケルと鉄の合金、又は銅材等の薄板を所
定のリードフレームの形状となるような金型を用いてプ
レスによる打ち抜き方法、又は所定のリードフレームの
形状となるようなマスク材でニッケルと鉄の合金又は銅
材等の薄板を覆い、エッチング法によりリードフレーム
を溶かすことにより所定のリードフレームの形状に成形
していた。
2. Description of the Related Art A lead frame of a conventional resin-encapsulated semiconductor device is a punching method by pressing a thin plate made of an alloy of nickel and iron, a copper material or the like with a die for forming a predetermined lead frame shape. Alternatively, a thin plate made of an alloy of nickel and iron, a copper material, or the like is covered with a mask material having a predetermined lead frame shape, and the lead frame is melted by an etching method to form the predetermined lead frame shape.

【0003】プレス法又はエッチング法による樹脂封止
型半導体装置のリードフレームの集積回路チップを搭載
するアイランド部およびリード部の切断面は、集積回路
を搭載するアイランド表面に対して90°の角度を持つ
ような構造を有している。
The island portion on which the integrated circuit chip of the lead frame of the resin-sealed semiconductor device by the pressing method or the etching method and the cut surface of the lead portion are formed at an angle of 90 ° with respect to the surface of the island on which the integrated circuit is mounted. It has the structure to have.

【0004】[0004]

【発明が解決しようとする課題】この従来の樹脂封止型
リードフレームでは、樹脂封止後に半導体装置の外部の
温度が急激に上昇又は下降した場合に、リードフレーム
と封止樹脂の熱膨張率の違いにより封止樹脂に応力がか
かり、封止樹脂にクラックが入るという欠点がある。
In this conventional resin-encapsulated lead frame, when the temperature outside the semiconductor device rises or falls sharply after resin encapsulation, the coefficient of thermal expansion of the lead frame and the encapsulation resin is increased. The difference is that stress is applied to the encapsulating resin, and the encapsulating resin is cracked.

【0005】そのため、半導体装置内部へ水分が浸入す
ることによる金属部材の腐食,短絡等の問題が発生して
いた。
Therefore, there have been problems such as corrosion and short circuit of metal members due to infiltration of water into the semiconductor device.

【0006】本発明の目的は、リードフレームから封止
樹脂に加わる応力を小さくして封止樹脂にクラックが入
るのを防止した樹脂封止型半導体装置を提供することに
ある。
An object of the present invention is to provide a resin-encapsulated semiconductor device in which the stress applied from the lead frame to the encapsulating resin is reduced to prevent the encapsulating resin from cracking.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る樹脂封止型半導体装置は、応力緩衝膜
を有し、リードフレームのアイランドに搭載された集積
回路チップ及びステッチに接続されたボンディングワイ
ヤーが封止樹脂で封止された樹脂封止型半導体装置であ
って、応力緩衝膜は、アイランド及びステッチの切断端
縁に形成された角部に設けられ、リードフレームから封
止樹脂への応力を緩衝するものである。
To achieve the above object, a resin-sealed semiconductor device according to the present invention has a stress buffer film and is connected to an integrated circuit chip and a stitch mounted on an island of a lead frame. A resin-encapsulated semiconductor device in which the bonded bonding wire is encapsulated with an encapsulating resin, wherein the stress buffer film is provided at a corner formed on the cut edge of the island and the stitch and encapsulated from the lead frame. It buffers the stress on the resin.

【0008】また、前記応力緩衝膜は、アイランド及び
ステッチを除く樹脂封止領域の全域に渡って設けられた
ものである。
Further, the stress buffer film is provided over the entire resin sealing region excluding the island and the stitch.

【0009】[0009]

【作用】リードフレームの少なくとも集積回路チップ搭
載面およびその裏面と側面、さらにステッチ部のボンデ
ィングワイヤーが接続される面およびその裏面と側面に
よって形成される角にポリイミド樹脂等の応力緩衝膜を
設け、その応力緩衝膜により応力を緩衝する。
A stress buffer film such as a polyimide resin is provided on at least the surface of the lead frame on which the integrated circuit chip is mounted, the back surface and side surfaces thereof, the surface of the stitch portion where the bonding wires are connected, and the corners formed by the back and side surfaces thereof. The stress buffer film buffers the stress.

【0010】[0010]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0011】(実施例1)図1は、本発明の実施例1を
示す平面図、図2は、図1のA−A′線断面図である。
(Embodiment 1) FIG. 1 is a plan view showing Embodiment 1 of the present invention, and FIG. 2 is a sectional view taken along the line AA 'in FIG.

【0012】図において、ニッケルと鉄の合金又は銅材
等の薄板をプレスによる打ち抜き又はエッチングにより
所定の形状にパターニングしたリードフレーム1におい
て、集積回路チップが搭載されるアイランド2の表面お
よび裏面と側面、さらに集積回路チップとボンディング
されるステッチ3の表面および裏面と側面によって形成
される角1aを、樹脂封止領域4の範囲内でポリイミド
樹脂等からなる応力緩衝膜5で覆っている。
In the figure, in a lead frame 1 in which a thin plate made of an alloy of nickel and iron or a copper material is punched by a press or patterned into a predetermined shape by etching, front and back surfaces and side surfaces of an island 2 on which an integrated circuit chip is mounted. Further, the corners 1a formed by the front and back surfaces and side surfaces of the stitch 3 bonded to the integrated circuit chip are covered with a stress buffer film 5 made of polyimide resin or the like within the resin sealing region 4.

【0013】このような構成により樹脂封止後にリード
フレーム1と封止樹脂との間に熱膨張率の違いにより生
じる応力が応力緩衝膜5により緩和され、直接封止樹脂
に応力が加わることはない。
With such a structure, the stress generated by the difference in the coefficient of thermal expansion between the lead frame 1 and the sealing resin after the resin sealing is alleviated by the stress buffer film 5, and the stress is not directly applied to the sealing resin. Absent.

【0014】(実施例2)図3は、本発明の実施例2を
示す平面図、図4は、図3のB−B′線断面図である。
(Embodiment 2) FIG. 3 is a plan view showing Embodiment 2 of the present invention, and FIG. 4 is a sectional view taken along the line BB 'in FIG.

【0015】実施例1ではアイランド2およびステッチ
3の角1aと側面のみ応力緩衝膜5により被覆されてい
るだけであった。
In the first embodiment, only the corners 1a and side surfaces of the island 2 and the stitch 3 are covered with the stress buffer film 5.

【0016】本実施例では、アイランド2およびステッ
チ3を除く樹脂封止領域全域にポリイミド樹脂等からな
る応力緩衝膜5′が形成されている。
In this embodiment, a stress buffer film 5'made of polyimide resin or the like is formed over the entire resin sealing region except the island 2 and the stitch 3.

【0017】そのため、封止樹脂とリードフレームが接
触する部分が最小限となっており、リードフレームから
封止樹脂への応力が最小限となり、樹脂クラック発生の
危険を抑えることができる。
Therefore, the contact portion between the encapsulating resin and the lead frame is minimized, the stress from the lead frame to the encapsulating resin is minimized, and the risk of resin cracking can be suppressed.

【0018】[0018]

【発明の効果】以上説明したように本発明は、リードフ
レームの少なくとも集積回路チップ搭載面およびその裏
面と側面、さらにステッチ部のボンディングワイヤーが
接続される面およびその裏面と側面によって形成される
角に応力緩衝膜を形成することにより、リードフレーム
と封止樹脂の熱膨張率の違いによる封止樹脂のストレス
が応力緩衝膜により緩和され、クラックの発生を防止で
き、信頼性の高い半導体装置を提供できる。
As described above, according to the present invention, at least the surface of the lead frame on which the integrated circuit chip is mounted and its back surface and side surface, and the surface to which the bonding wire of the stitch portion is connected and its back surface and side surface are formed. By forming the stress buffer film on the core, the stress of the encapsulation resin due to the difference in the thermal expansion coefficient between the lead frame and the encapsulation resin is relieved by the stress buffer film, and the occurrence of cracks can be prevented. Can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1を示す平面図である。FIG. 1 is a plan view showing a first embodiment of the present invention.

【図2】図1のA−A′線断面図である。FIG. 2 is a sectional view taken along the line AA ′ of FIG.

【図3】本発明の実施例2を示す平面図である。FIG. 3 is a plan view showing a second embodiment of the present invention.

【図4】図3のB−B′線断面図である。FIG. 4 is a sectional view taken along line BB ′ of FIG.

【符号の説明】[Explanation of symbols]

1 リードフレーム 2 アイランド 3 ステッチ 4 樹脂封止領域 5,5′ 応力緩衝膜 1 Lead frame 2 Island 3 Stitch 4 Resin sealing area 5, 5'Stress buffer film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/50 G 9272−4M ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/50 G 9272-4M

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 応力緩衝膜を有し、リードフレームのア
イランドに搭載された集積回路チップ及びステッチに接
続されたボンディングワイヤーが封止樹脂で封止された
樹脂封止型半導体装置であって、 応力緩衝膜は、アイランド及びステッチの切断端縁に形
成された角部に設けられ、リードフレームから封止樹脂
への応力を緩衝するものであることを特徴とする樹脂封
止型半導体装置。
1. A resin-encapsulated semiconductor device having a stress buffer film, wherein an integrated circuit chip mounted on an island of a lead frame and a bonding wire connected to a stitch are encapsulated with an encapsulating resin. The resin-sealed semiconductor device, wherein the stress buffer film is provided at a corner formed on the cut edges of the island and the stitch and buffers the stress from the lead frame to the sealing resin.
【請求項2】 請求項1に記載の樹脂封止型半導体装置
であって、 前記応力緩衝膜は、アイランド及びステッチを除く樹脂
封止領域の全域に渡って設けられたものであることを特
徴とする樹脂封止型半導体装置。
2. The resin-encapsulated semiconductor device according to claim 1, wherein the stress buffer film is provided over the entire resin-encapsulated region excluding islands and stitches. And a resin-encapsulated semiconductor device.
JP4110688A 1992-04-03 1992-04-03 Resin-sealed semiconductor device Pending JPH05283558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4110688A JPH05283558A (en) 1992-04-03 1992-04-03 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4110688A JPH05283558A (en) 1992-04-03 1992-04-03 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH05283558A true JPH05283558A (en) 1993-10-29

Family

ID=14541930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4110688A Pending JPH05283558A (en) 1992-04-03 1992-04-03 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH05283558A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288566A (en) * 2007-04-20 2008-11-27 Nec Electronics Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288566A (en) * 2007-04-20 2008-11-27 Nec Electronics Corp Semiconductor device

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