JPH05283475A - Mounting method for flip chip - Google Patents
Mounting method for flip chipInfo
- Publication number
- JPH05283475A JPH05283475A JP4024492A JP4024492A JPH05283475A JP H05283475 A JPH05283475 A JP H05283475A JP 4024492 A JP4024492 A JP 4024492A JP 4024492 A JP4024492 A JP 4024492A JP H05283475 A JPH05283475 A JP H05283475A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- chip
- solder bumps
- substrate
- junction parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、裸のＩＣチップを基板
に直接フェイスダウンで接続するフリップチップの実装
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip mounting method in which a bare IC chip is directly face-down connected to a substrate.
【０００２】[0002]
【従来の技術】近年、基板の高密度化、ＩＣの高集積化
によるＩＣチップの多ピン化、実装間隔の狭ピッチ化に
伴い、樹脂封止をしていない裸のＩＣチップを直接フェ
イスダウンで接続するフリップチップ実装が注目されて
いる。このフリップチップ実装の従来のプロセスは、ま
ず図６に示すようにＩＣチップ１の電極パッド２に半田
バンプ３を接着し、電極パッド２と基板４上に形成され
たランド５とを位置合わせする。次に図７に示すように
半田バンプ３をランド５上にマウントして加熱し、リフ
ローを行なって半田バンプ３を溶融し、電極パッド２と
ランド５とを接合する。2. Description of the Related Art In recent years, a bare IC chip that is not resin-sealed is directly faced down as the number of pins of the IC chip increases and the pitch of the mounting interval becomes narrower due to the higher density of the substrate, the higher integration of the IC. Flip-chip mounting, which is connected with, is drawing attention. In the conventional flip-chip mounting process, first, as shown in FIG. 6, solder bumps 3 are bonded to the electrode pads 2 of the IC chip 1 and the electrode pads 2 and the lands 5 formed on the substrate 4 are aligned with each other. . Next, as shown in FIG. 7, the solder bumps 3 are mounted on the lands 5, heated, and reflowed to melt the solder bumps 3 to bond the electrode pads 2 and the lands 5.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
ような従来のフリップチップ実装プロセスによると、リ
フロー時に半田バンプ３が完全に溶融する温度に設定す
ると、ＩＣチップ１が自重で沈み込み、図８の左側に示
すように半田接合部が横に広がる。このときＩＣチップ
１の自重が重かったり、電極パッド２間のピッチが例え
ば８０μｍ乃至１５０μｍと狭い場合には、図８の右側
に示すように半田接合部にブリッジが生ずる。また、半
田接合部の高さも半田が横に広がるために確保できず、
例えば電極パッド２間のピッチが１５０μｍの場合２０
μｍ乃至３０μｍと、かなり薄くなる。However, according to the conventional flip chip mounting process as described above, when the temperature is set so that the solder bumps 3 are completely melted at the time of reflow, the IC chip 1 sinks under its own weight, and as shown in FIG. The solder joint expands laterally as shown on the left side of FIG. At this time, if the weight of the IC chip 1 is heavy or the pitch between the electrode pads 2 is narrow, for example, 80 μm to 150 μm, a bridge occurs at the solder joint portion as shown on the right side of FIG. Also, the height of the solder joint cannot be secured because the solder spreads laterally,
For example, when the pitch between the electrode pads 2 is 150 μm, 20
It becomes considerably thin, that is, μm to 30 μm.
【０００４】一方、ＩＣチップ１のサイズが大きい場合
には、ＩＣチップ１と基板４との熱膨張係数が異なるた
め、熱による伸縮が不整合となる。このため接合部であ
る半田バンプ３に応力が加わるので、半田接合部の高さ
は高いほうが熱サイクルに対する寿命は長くなる。従っ
て前述したように半田接合部が薄いとこの部分の信頼性
を確保することができない。逆に半田接合部の高さを確
保するために、半田が半溶融状態になるようにリフロー
温度を設定すると、ＩＣチップ１の自重による沈み込み
はある程度防止できるが、基板４に対する半田コートが
均一にならず、基板４の反りなどによる未半田部分が発
生するおそれがある。このような未半田部分の発生を防
止するためには、基板４側及びＩＣチップ１側の半田バ
ンプ３の高さを均一にしなければならず、高度の技術が
必要となる。On the other hand, when the size of the IC chip 1 is large, the expansion and contraction due to heat are mismatched because the IC chip 1 and the substrate 4 have different coefficients of thermal expansion. For this reason, stress is applied to the solder bumps 3 that are the joints, so that the higher the height of the solder joints, the longer the life for the thermal cycle. Therefore, as described above, if the solder joint portion is thin, the reliability of this portion cannot be secured. On the contrary, if the reflow temperature is set so that the solder is in a semi-molten state in order to secure the height of the solder joint portion, it is possible to prevent the IC chip 1 from sinking due to its own weight to some extent, but the solder coat on the substrate 4 is uniform. However, the unsoldered portion may be generated due to the warp of the substrate 4. In order to prevent the occurrence of such unsoldered portions, it is necessary to make the heights of the solder bumps 3 on the substrate 4 side and the IC chip 1 side uniform, and a high level technique is required.
【０００５】本発明はこのような状況に鑑みてなされた
ものであり、ＩＣチップと基板との半田接合部の高さを
確保し、接合の信頼性を向上させることのできるフリッ
プチップの実装方法を提供することを目的とする。The present invention has been made in view of such circumstances, and a flip chip mounting method capable of ensuring the height of a solder joint between an IC chip and a substrate and improving the reliability of the joint. The purpose is to provide.
【０００６】[0006]
【課題を解決するための手段】本発明のフリップチップ
の実装方法は、ＩＣチップ１に設けられた電極パッド２
を基板４に対向させ、半田バンプ３を介して電極パッド
２と基板４上に形成されたランド５とを接続するフリッ
プチップの実装方法において、基板４上に形成されたラ
ンド５にフラックス１１を塗布する第１の工程と、ＩＣ
チップ１の電極パッド２に供給された半田バンプ３をフ
ラックス１１を介してランド５に接着させる第２の工程
と、基板４を反転させ、ＩＣチップ１をフラックス１１
を介して垂下させた状態で加熱し、半田バンプ３をリフ
ローする第３の工程とを備えたことを特徴とする。According to the flip-chip mounting method of the present invention, an electrode pad 2 provided on an IC chip 1 is used.
In the flip-chip mounting method in which the electrodes 5 are opposed to the substrate 4 and the electrode pads 2 and the lands 5 formed on the substrate 4 are connected via the solder bumps 3, a flux 11 is applied to the lands 5 formed on the substrate 4. First step of coating and IC
The second step of adhering the solder bumps 3 supplied to the electrode pads 2 of the chip 1 to the lands 5 via the flux 11, and reversing the substrate 4 to set the IC chip 1 to the flux 11
And a third step of reflowing the solder bumps 3 by heating the solder bumps 3 in a suspended state.
【０００７】[0007]
【作用】上記のフリップチップの実装方法によると、Ｉ
Ｃチップ１を半田バンプ３及びフラックス１１を介して
基板４から垂下した状態でリフローするので、ＩＣチッ
プ１の自重により半田接合部が下方に引っ張られ、半田
の表面張力の限度まで半田が伸びる。従って半田が横に
広がることがなく、ランド５の間隔のピッチが小さい場
合でもブリッジの発生を防止することができる。また半
田が伸びて半田接合部の厚さが厚くなるので、熱サイク
ルに対する半田接合部の寿命を長くすることができる。
さらに半田接合部が横に広がらないので、半田が完全に
溶融する温度でリフローすることができ、上部である基
板４側の半田コートの半田量を確保することにより、未
半田の発生を防止することができる。According to the above flip-chip mounting method, I
Since the C chip 1 is reflowed in a state of being hung from the substrate 4 via the solder bumps 3 and the flux 11, the solder joint portion is pulled downward by the weight of the IC chip 1 and the solder extends to the limit of the surface tension of the solder. Therefore, the solder does not spread laterally, and it is possible to prevent the occurrence of bridges even when the pitch between the lands 5 is small. In addition, since the solder extends and the thickness of the solder joint increases, the life of the solder joint with respect to the thermal cycle can be extended.
Furthermore, since the solder joint portion does not spread laterally, reflow can be performed at a temperature at which the solder is completely melted, and the amount of solder in the solder coat on the upper side of the substrate 4 is secured to prevent unsolder from occurring. be able to.
【０００８】[0008]
【実施例】以下、本発明のフリップチップの実装方法の
一実施例を図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a flip chip mounting method according to the present invention will be described below with reference to the drawings.
【０００９】図１乃至図４に本発明の一実施例による実
装方法を示す。これらの図において、図７に示す従来例
の部分と対応する部分には同一の符号を付してあり、そ
の説明は適宜省略する。図１に示す第１の工程におい
て、基板１上に形成されたランド５上にフラックス１１
を塗布する。このフラックス１１は粘着力のある導電性
材料で構成されている。次に図２に示す第２の工程にお
いて、ＩＣチップ１の電極パッド２に供給された半田バ
ンプ３を基板４上に形成されたランド５の位置に合わ
せ、半田バンプ３とランド５とをフラックス１１により
接着する。1 to 4 show a mounting method according to an embodiment of the present invention. In these figures, parts corresponding to those of the conventional example shown in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted as appropriate. In the first step shown in FIG. 1, the flux 11 is formed on the land 5 formed on the substrate 1.
Apply. The flux 11 is made of a conductive material having an adhesive force. Next, in the second step shown in FIG. 2, the solder bumps 3 supplied to the electrode pads 2 of the IC chip 1 are aligned with the lands 5 formed on the substrate 4, and the solder bumps 3 and the lands 5 are fluxed. Bond with 11.
【００１０】次に図３に示す第３の工程において、基板
４を反転させてＩＣチップ１を半田バンプ３を介して基
板４の下部に垂下させる。そして図４に示す第４の工程
において、半田接合部を加熱して半田バンプ３のリフロ
ーを行なう。この結果ＩＣチップ１の自重により半田接
合部が下に引っ張られ、半田の表面張力限度まで半田が
伸びる。そして半田接合部の形状はつつみ型となる。Next, in a third step shown in FIG. 3, the substrate 4 is inverted and the IC chip 1 is hung below the substrate 4 via the solder bumps 3. Then, in a fourth step shown in FIG. 4, the solder joints are heated to reflow the solder bumps 3. As a result, the solder joint portion is pulled downward by the self-weight of the IC chip 1, and the solder extends to the surface tension limit of the solder. Then, the shape of the solder joint portion becomes a wrapping type.
【００１１】本実施例によれば、半田接合部がＩＣチッ
プ１の自重で下に引っ張られるので横に広がることはな
い。従ってランド５の間隔のピッチが小さい場合でも、
隣接するランド間でブリッジが発生することはない。ま
た半田が伸びて半田接合部の厚さが厚くなるので、熱サ
イクルに対する半田接合部の寿命を長くすることができ
る。さらに半田接合部が横に広がらないので、半田が完
全に溶融する温度でリフローすることができ、半田バン
プ３の高さのバラツキがあっても、半田量を適性に確保
することにより未半田の発生を防止することができる。
また半田接合部の形状が熱サイクルに対する寿命が長い
といわれているつづみ型であるので、実装の信頼性を確
保することができる。しかも半田が溶融したときに表面
張力により位置補正がなされるので、セルフアライメン
ト効果が増大する。According to this embodiment, since the solder joint portion is pulled downward by the weight of the IC chip 1, it does not spread laterally. Therefore, even if the land 5 pitch is small,
No bridge will occur between adjacent lands. In addition, since the solder extends and the thickness of the solder joint increases, the life of the solder joint with respect to the thermal cycle can be extended. Further, since the solder joint portion does not spread laterally, reflow can be performed at a temperature at which the solder is completely melted, and even if there is variation in the height of the solder bumps 3, an appropriate amount of solder can be secured to prevent unsoldered solder. Occurrence can be prevented.
In addition, since the shape of the solder joint is a staggered type, which is said to have a long life with respect to the thermal cycle, it is possible to secure the reliability of mounting. Moreover, when the solder melts, the position is corrected by the surface tension, so that the self-alignment effect is increased.
【００１２】なお、ＩＣチップ１のサイズが大きくなる
と重量が増大し、リフロー時にＩＣチップ１が基板４か
ら落下するおそれのある場合は、ダミーバンプを形成し
て接合点を多くするとよい。または図５に示すように複
数本の支柱２１が立設された治具板２２を用い、支柱２
１により基板４を支持し、基板４から垂下されたＩＣチ
ップ１と治具板２２との間に所定の間隔を設けてリフロ
ーを行ない、ＩＣチップ１の落下を防止するようにして
もよい。If the size of the IC chip 1 is increased and the IC chip 1 may drop from the substrate 4 during reflow, dummy bumps may be formed to increase the number of bonding points. Alternatively, as shown in FIG. 5, using a jig plate 22 in which a plurality of columns 21 are erected,
The substrate 4 may be supported by 1 and a reflow may be performed by providing a predetermined gap between the IC chip 1 hanging from the substrate 4 and the jig plate 22 to prevent the IC chip 1 from dropping.
【００１３】上記実施例では半田バンプ３をＩＣチップ
１の電極パッド２側に設けた場合について説明したが、
半田バンプ３を基板４のランド５側に設けてもよいし、
両側に設けてもよい。なおフラックス１１の代わりに接
着剤を用いると、セルフアライメントが不可能になるの
で好ましくない。In the above embodiment, the case where the solder bump 3 is provided on the electrode pad 2 side of the IC chip 1 has been described.
The solder bumps 3 may be provided on the land 5 side of the substrate 4,
It may be provided on both sides. It is not preferable to use an adhesive instead of the flux 11 because self-alignment becomes impossible.
【００１４】[0014]
【発明の効果】以上説明したように、本発明のフリップ
チップの実装方法によれば、ＩＣチップを下にして半田
バンプを介してフラックスにより基板に接着させてリフ
ローするようにしたので、ＩＣチップ実装時に半田バン
プが横に広がらず、厚さが厚くなるので、半田のブリッ
ジの発生を防止し、熱サイクルに対する半田接合部の寿
命を長くすることができ、実装の信頼性を向上すること
ができる。As described above, according to the flip-chip mounting method of the present invention, since the IC chip is faced down and the solder bumps are used to adhere the flux to the substrate for reflow, the IC chip is reflowed. Since the solder bumps do not spread laterally during mounting and the thickness becomes thicker, it is possible to prevent the occurrence of solder bridges, prolong the life of the solder joint part against thermal cycles, and improve the mounting reliability. it can.
【図１】本発明のフリップチップの実装方法の一実施例
の第１の工程を示す側面図である。FIG. 1 is a side view showing a first step of an embodiment of a flip chip mounting method of the present invention.
【図２】本実施例における第２の工程を示す側面図であ
る。FIG. 2 is a side view showing a second step in the present embodiment.
【図３】本実施例における第３の工程を示す側面図であ
る。FIG. 3 is a side view showing a third step in the present embodiment.
【図４】本実施例における第４の工程を示す側面図であ
る。FIG. 4 is a side view showing a fourth step in the present embodiment.
【図５】本発明の他の実施例による治具の構成を示す側
面図である。FIG. 5 is a side view showing the configuration of a jig according to another embodiment of the present invention.
【図６】従来のフリップチップの実装方法の一例のＩＣ
チップと基板との位置合わせの工程を示す示す側面図で
ある。FIG. 6 is an example of an IC of a conventional flip-chip mounting method.
It is a side view which shows the process of position alignment of a chip | tip and a board | substrate.
【図７】図６のＩＣチップの基板へのマウント工程を示
す側面図である。7 is a side view showing a step of mounting the IC chip of FIG. 6 on a substrate.
【図８】図６の半田リフロー時の状態を示す側面図であ
る。FIG. 8 is a side view showing a state during solder reflow in FIG.
１ ＩＣチップ ２ 電極パッド ３ 半田バンプ ４ 基板 ５ ランド １１ フラックス 1 IC chip 2 Electrode pad 3 Solder bump 4 Substrate 5 Land 11 Flux
───────────────────────────────────────────────────── フロントページの続き (72)発明者 田原 浩樹 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroki Tahara 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation
Claims (1)
板に対向させ、半田バンプを介して前記電極パッドと前
記基板上に形成されたランドとを接続するフリップチッ
プの実装方法において、 前記基板上に形成された前記ランドにフラックスを塗布
する第１の工程と、 前記ＩＣチップの電極パッドに供給された前記半田バン
プを前記フラックスを介して前記ランドに接着させる第
２の工程と、 前記基板を反転させ、前記ＩＣチップを前記フラックス
を介して垂下させた状態で加熱し、前記半田バンプをリ
フローする第３の工程とを備えたことを特徴とするフリ
ップチップの実装方法。1. A flip-chip mounting method in which an electrode pad provided on an IC chip is opposed to a substrate and the electrode pad and a land formed on the substrate are connected via a solder bump. A first step of applying a flux to the land formed on the substrate; a second step of adhering the solder bumps supplied to the electrode pads of the IC chip to the land through the flux; A flip chip mounting method, which comprises a third step of reversing, heating the IC chip in a suspended state via the flux, and reflowing the solder bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4024492A JP3175786B2 (en) | 1992-01-30 | 1992-01-30 | Flip chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4024492A JP3175786B2 (en) | 1992-01-30 | 1992-01-30 | Flip chip mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05283475A true JPH05283475A (en) | 1993-10-29 |
| JP3175786B2 JP3175786B2 (en) | 2001-06-11 |
Family
ID=12575301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4024492A Expired - Fee Related JP3175786B2 (en) | 1992-01-30 | 1992-01-30 | Flip chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3175786B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012164957A1 (en) * | 2011-06-02 | 2012-12-06 | パナソニック株式会社 | Electronic component mounting method, electronic component loading device and electronic component mounting system |
| US20220216071A1 (en) * | 2021-01-05 | 2022-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014109164A (en) * | 2012-12-04 | 2014-06-12 | Sumitomo Mitsui Construction Co Ltd | Apartment house |
-
1992
- 1992-01-30 JP JP4024492A patent/JP3175786B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012164957A1 (en) * | 2011-06-02 | 2012-12-06 | パナソニック株式会社 | Electronic component mounting method, electronic component loading device and electronic component mounting system |
| CN103548430A (en) * | 2011-06-02 | 2014-01-29 | 松下电器产业株式会社 | Electronic component mounting method, electronic component loading device and electronic component mounting system |
| US9609760B2 (en) | 2011-06-02 | 2017-03-28 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component mounting method |
| US20220216071A1 (en) * | 2021-01-05 | 2022-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
| US11830746B2 (en) * | 2021-01-05 | 2023-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3175786B2 (en) | 2001-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5160450B2 (en) | Method of mounting semiconductor components on a circuit board | |
| JP2842361B2 (en) | Semiconductor device | |
| US5973406A (en) | Electronic device bonding method and electronic circuit apparatus | |
| JP2907168B2 (en) | Semiconductor device and bonding structure of semiconductor device and substrate | |
| JPH05283475A (en) | Mounting method for flip chip | |
| JPH09246319A (en) | Flip chip mounting method | |
| JPH11163044A (en) | Printed wiring board and method for mounting electronic parts | |
| JPH05218134A (en) | Mounting structure for flip chip | |
| JPH09213702A (en) | Semiconductor device and method for mounting the same | |
| JPH02206138A (en) | Method of mounting flip-chip | |
| JP4200090B2 (en) | Manufacturing method of semiconductor device | |
| JPH05218135A (en) | Mounting method for flip chip | |
| JPH07273146A (en) | Mounting method for semiconductor device | |
| JPH05218136A (en) | Bonding method for flip chip | |
| JPH0243748A (en) | Packaging of integrated circuit chip | |
| JPH0357223A (en) | Semiconductor device | |
| JP3983972B2 (en) | Electronic circuit module | |
| JPH11186454A (en) | Bga type integrated circuit parts, manufacture of the parts and method for mounting the parts | |
| JP2001339151A (en) | Method for mounting electronic component with bumps | |
| JPH05235098A (en) | Flip chip bonding method | |
| JPH05121488A (en) | Bare chip mounting board | |
| JPH03268440A (en) | Mounting structure of semiconductor chip | |
| JPH0945807A (en) | Semiconductor device | |
| JPH10242632A (en) | Forming method for solder bump | |
| JP2000332060A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20010308 |
|
| LAPS | Cancellation because of no payment of annual fees |