JPH05282611A - Magnetic recording/reproducing device - Google Patents

Abstract

PURPOSE:To save a memory by constituting a timing control memory for making a recording signal of two systems and a timing control memory for making a reproducing signal column of one continueous system of one memory. CONSTITUTION:A digital RF signal of one system supplied to a signal distribution synthesization circuit 35M from a PR precoder 2 via a switch 3 is devided into the RF signals of an A channel and B channel by the circuit 35M. The signal of A channel is supplied to a memory 4 and written in the memory 4 in accordance with a clock signal supplied from a recording time writing clock generation section 5. At the time of reproducing, the RF signal of B channel is supplied to the memory 4 via a tenminal 11M and written in the memory 4 in accordance with a clock signal supplied from a reproducing time writing clock generation section 6. Thus, the signal of A channel inputted without delay and the signal of B channel inputted with delay are superposed by the circuit 35M and they are supplied to an equalizer 23 as the RF signal of one system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to magnetic recording / reproducing for simultaneously recording on two channels of a magnetic recording medium by two magnetic heads arranged close to each other and having different azimuth angles, and reproducing simultaneously from the two channels. Regarding the device.

[0002]

2. Description of the Related Art FIGS. 18 and 19 show an example of the structure on the recording side and the reproducing side of a conventional digital VTR using a stepped V _X head, that is, two magnetic heads arranged close to each other and having different azimuth angles. Indicates. First, on the recording side, the adaptive scramble circuit 10 has a plurality of M-sequence scramble circuits, and an M signal that can obtain an output with the least high frequency component and DC component with respect to the input signal from the digital signal processing unit. Select a series. The PR4 precoder 2 is a precoder for the PR4 (partial response class 4) detection method, and is 1 / (1-D
² ) The arithmetic processing of (D is a unit delay element) is performed.

Signal recording on a magnetic tape is performed by two channels (A
Channel and B channel)
4 digital RF supplied from precoder 2
It is necessary to separate the signal into two channels. Magnetic head 1
When 3A and 13B are facing each other 180 degrees apart, recording may be performed at the timing when the signal is supplied, but in the case of the stepped V _X head, one channel (for example, It is necessary to record the RF signal of the A channel) later than the RF signal of the other channel (for example, the B channel). In the conventional example of FIG. 18, a memory 4R is provided to delay the RF signal of the A channel. The A channel RF signal delayed by the memory 4R for a predetermined time is supplied to the magnetic head 13A via the recording amplifier 12A and recorded on the magnetic tape. The B channel RF signal is supplied as it is to the magnetic head 13B via the recording amplifier 12B and recorded on the magnetic tape.

On the reproducing side, magnetic heads 13A and 13
A channel and B obtained from the magnetic tape by B
The RF signals of the channels are transmitted to the A / D converters 22A and 22A via the reproduction amplifiers 21A and 21B, respectively.
It is supplied to B and converted into a digital RF signal. In the case of a stepped V _X head, the RF signal read from the B channel of the magnetic tape by the magnetic head 13B is
It is delayed by only a few degrees from the RF signal read from the A channel of the magnetic tape by the magnetic head 13A. A memory 4P is provided at the next stage of the A / D converter 22B for the B channel in order to delay the RF reproduced signal for the B channel by 180 degrees to the RF reproduced signal for the A channel and synthesize the RF signals for both channels.

B output from the A / D converter 22B
The digital RF signal of the channel is combined with the digital RF signal of the A channel delayed by the memory 4P for a predetermined time to be supplied as one system digital RF signal to the equalizer 23, where the waveform is shaped. Later, PR
4 to the detector 24. The PR4 detector 24 performs 1 + D calculation on the input signal and supplies an output indicating the calculation result to the Viterbi decoder 25. Viterbi decoder 25
Performs an operation on the input signal using the correlation and certainty of the data, decodes the data into noise-resistant data, and supplies a signal indicating the decoding result to the descramble circuit 26. The descramble circuit 26 restores the original data by returning the data rearranged by the scrambling process on the recording side to the original series, and supplies the original data to the digital signal processing unit.

Further, conventionally, on the reproducing side of a digital VTR, it has been proposed to remove a time axis fluctuation component in a reproduced signal by using a FIFO buffer.

[0007]

In the conventional digital VTR shown in FIGS. 18 and 19 described above,
Since the timing control memories 4R and 4P are provided on the recording side and the reproducing side, respectively, there is a problem that the device becomes large and the cost becomes high.

The above-described conventional digital VTR using the FIFO buffer is not considered for variable speed reproduction such as CUE and REVIEW.

The present invention has been made in view of the above circumstances, and it is a first object of the present invention to provide a small-sized and low-cost magnetic recording / reproducing apparatus capable of saving memory.

A second object of the present invention is to provide a small-sized and low-cost magnetic reproducing apparatus which can save a memory for storing a reproduced signal during variable speed reproduction.

[0011]

According to another aspect of the present invention, there is provided a magnetic recording / reproducing apparatus having two magnetic heads arranged close to each other and having different azimuth angles (for example, the magnetic head 13A of the embodiment).
And 13B), the magnetic recording and reproducing are performed by simultaneously recording on two channels (for example, the A channel and B channel of the embodiment) of the magnetic recording medium (for example, the magnetic tape 78 of the embodiment), and simultaneously reproducing from these two channels. The apparatus is a timing control memory for converting one series of recording signal sequence into two series of recording signals capable of simultaneously recording in two channels, and two series of reproducing signals obtained by simultaneous reproduction from two channels. , And a timing control memory for forming a continuous reproduction signal sequence of one series is constituted by one memory (for example, the memory 4 of the embodiment).

According to a second aspect of the present invention, there is provided a magnetic reproducing apparatus in which a magnetic recording medium (for example, the magnetic head of the embodiment) is provided by two magnetic heads (for example, the magnetic heads 13A and 13B of the embodiments) arranged close to each other and having different azimuth angles. Magnetic tape 78)
A magnetic reproducing apparatus for simultaneously reproducing from two channels (for example, A channel and B channel of the embodiment),
A timing control memory (for example, the FIFO buffer 30 of the embodiment) for converting two series of reproduced signals obtained by simultaneous reproduction from two channels into a continuous one series of reproduced signal train, and reproduction during variable speed reproduction. Level detection means for detecting a period in which the signal level is equal to or higher than a predetermined value (for example,
The level detector 42 of the embodiment and the write control means (for example, the FIFO write enable signal generation circuit 31R of the embodiment) that enables the reproduction signal to be written in the memory during the period detected by the level detection means. ) And are provided.

[0013]

In the magnetic recording / reproducing apparatus having the structure of the first aspect, at the time of recording, the recording signal of one of the two channels (for example, the A channel) is delayed by the one memory, and 2 channels can be recorded simultaneously
A series of recording signals is generated, and at the time of reproduction, the reproduction signal of the other channel (for example, B channel) of the two channels is delayed by the memory to generate a continuous series of reproduction signals. .. Therefore, the function conventionally performed by two memories can be realized by one memory, so that the memory can be saved, and the size and cost of the apparatus can be reduced.

According to another aspect of the magnetic reproducing apparatus of the present invention, the level detecting means detects a period in which the level of the reproduction signal during variable speed reproduction is equal to or higher than a predetermined value, and during this period, the reproduction signal to the memory is detected. Writing is possible. Therefore, only the high-level reproduction signal is stored in the memory, so that the memory can be saved and the device can be downsized and the cost can be reduced.

[0015]

1 and 2 show an embodiment of a magnetic recording / reproducing apparatus of the present invention in a recording state and a reproducing state, respectively. This example illustrates the present invention with a stepped V
_This is an example applied to a digital VTR using an _X head, that is, two magnetic heads arranged close to each other and having different azimuth angles. 1 and 2, the adaptive scramble circuit 1, the PR4 precoder 2, the equalizer 23, P
The R4 precoder 24, the Viterbi decoder 25, and the descrambling circuit 26 are the same as those in the conventional example shown in FIGS. 18 and 19 and described above, and therefore the description thereof is omitted here.

The recording side input terminal 3E of the switch 3 has a PR
4 is connected to the output terminal of the precoder 2, the reproduction side output terminal 3D of the switch 3 is connected to the input terminal of the equalizer 23, and the common terminal 3C of the switch 3 is the signal distribution / synthesis circuit 3
It is connected to the terminal C of the SM. Signal distribution / synthesis circuit 3S
M is a series of recordings R supplied to the terminal C during recording.
The F signal is distributed to the recording RF signal for A channel and the recording RF signal for B channel, and output to terminals M and N, respectively. Further, the signal distribution / synthesis circuit 3SM synthesizes the reproduction RF signal for B channel and the reproduction RF signal for A channel, which are respectively supplied to the terminals M and N, into one series of reproduction RF signals at the time of reproduction, and outputs them to the terminal C. To do.

The terminal M of the signal distribution / synthesis circuit 3SM is connected to the data input / output terminal D1 of the memory 4. The memory 4 is composed of, for example, a FIFO buffer. The write clock input terminal W of the memory 4 is connected to the output terminal 7C of the write clock switch 7. The input terminals 7R and 7P of the write clock switch 7 are respectively
It is connected to the output terminal of the write-in clock clock generator 5 and the output terminal of the write-in write clock generator 6.
The write clock generator for recording 5 is composed of a highly accurate reference clock generator such as a crystal oscillator. The write clock generator 6 for reproduction uses the magnetic head 13A or 13 during reproduction.
It reproduces the bit clock of the reproduction signal obtained from B and outputs it as a reproduction-time write clock, and the reproduction-time write clock includes jitter.

The read clock input terminal R of the memory 4 is
It is connected to the output terminal 10C of the read clock switcher 10. The input terminals 10R and 10P of the read clock switch 10 are connected to the output terminal of the read clock generator 8 for recording and the output terminal of the read clock generator 9 for playback, respectively. The recording read clock generator 8 and the reproducing read clock generator 9 are composed of a highly accurate reference clock generator such as a crystal oscillator. By configuring the write-in-reproduction-clock generator 6 and the read-out-read-clock generator 9 as described above, the time axis fluctuation in the reproduced signal can be removed by writing and reading the reproduced signal in the memory 4. ..

The input / output terminal D2 of the memory 4 is connected to the terminal 11M of the recording / reproducing switching device 11. The terminal N of the signal distribution / synthesis circuit 3SM is the terminal 11 of the recording / reproducing switching device 11.
It is connected to N.

At the time of recording, the terminal 1 of the recording / reproducing switching device 11
1A and 11B are connected to the input terminals of recording amplifiers 12A and 12B, respectively. The output terminals of the recording amplifiers 12A and 12B are respectively connected to the magnetic head 13A.
And 13B. Further, at the time of recording, the terminals 11M and 11N of the recording / reproducing switch 11 are connected to the terminals 11A and 11B, respectively.

At the time of reproduction, the terminal 1 of the recording / reproduction switching device 11
1A and 11B are the A / D converters 22 respectively.
It is connected to the output terminals of A and 22B. The input terminals of the A / D converters 22A and 22B are connected to the output terminals of the reproduction amplifiers 21A and 21B, respectively. The input terminals of the reproduction amplifiers 21A and 21B are connected to the magnetic heads 13A and 13B, respectively. Also, at the time of reproduction, the terminal 11 of the recording / reproduction switching device 11
M and 11N are terminals 11B and 11A, respectively.
Connected to.

As shown in FIG. 5, the magnetic heads 13A and 13B are attached to the rotary drum 76 in a form in which the magnetic heads 13A and 13B are integrated. A magnetic tape (not shown) is obliquely wound around the peripheral surface of the drum 76 at a winding angle slightly larger than 180 degrees or slightly smaller than 180 degrees. And the magnetic head 1
3A and 13B simultaneously scan the magnetic tape.

The magnetic heads 13A and 13B have different gap extension directions (referred to as azimuth angles). For example, as shown in FIG.
An azimuth angle of ± 20 degrees is set between A and 13B. Due to this difference in azimuth angle,
A recording pattern as shown in FIG. 7 is formed. In FIG. 7, adjacent tracks TA and TB of the magnetic tape are
It is formed by magnetic heads 13A and 13B having different azimuth angles. Therefore, during reproduction, the amount of crosstalk between adjacent tracks TA and TB can be reduced due to azimuth loss.

FIG. 8 shows a more specific structure in the case where the magnetic heads 13A and 13B have the integral structure (so-called double azimuth head or V _X head) as described above. For example, the magnetic heads 13A and 13B having an integral structure are attached to the upper drum 76 rotated at a high speed of 150 rps (NTSC system), and the lower drum 77 is fixed. Therefore, on the magnetic tape 78, one field of data is divided into five tracks and recorded. This segment method can reduce the error in track linearity. Winding angle θ of magnetic tape 78
Is, for example, 166 degrees, and the diameter of the drum 76 is 1
It is 6.5 mm.

When performing simultaneous recording using the V _X head,
Normally, the magnetic tape 78 vibrates due to the eccentricity of the rotating portion of the upper drum 76, and an error in the linearity of the track occurs. As shown in FIG. 9 (a), the magnetic tape 78 is pressed down, and as shown in FIG. 9 (b),
The magnetic tape 78 is pulled upward, which vibrates the magnetic tape 78 and deteriorates the linearity of the track. However, the amount of linearity error can be reduced by performing simultaneous recording using the V _X head, as compared with a pair of magnetic heads which are arranged 180 degrees apart and face each other. Further, V _X head, since the inter-head distance is small, there is an advantage that it is possible to perform the bearing more precise adjustments. Magnetic head 13A having such a V _X head configuration
With 13B, recording and reproduction with a narrow width can be performed.

FIG. 3 is a time chart showing the recording signal train of each part of the embodiment of the magnetic recording / reproducing apparatus shown in FIG. The operation of the embodiment shown in FIG. 1 will be described below with reference to FIG. During recording, terminals 3E and 3 of switch 3
C is connected, terminals 7R and 7C of the write clock switch 7 are connected, and terminal 1 of the read clock switch 10 is connected.
0R and 10C are connected, the terminals 11M and 11A of the recording / reproducing switching device 11 are connected, and the recording / reproducing switching device 11 is connected.
11N and 11B are connected.

The 1-system digital RF signal supplied from the PR4 precoder 2 to the signal distribution / synthesis circuit 3SM via the terminals 3E and 3C of the switch 3 is processed by the signal synthesis / distribution circuit 3SM. Separated into signals. The RF signal of the A channel is supplied to the memory 4 via the terminals M and D1 and is written in the memory 4 in accordance with the recording time write clock signal supplied from the recording time write clock generator 5. Memory 4
The RF signal of the A channel written in (1) is read according to the recording read clock signal supplied from the recording read clock generator 8. Therefore, the A channel RF
The signal is delayed by a predetermined time, and the recording / reproducing switching device 1
1 is supplied to the terminal 11M. Signal distribution / synthesis circuit 3SM
The B channel RF signal separated by is directly supplied to the terminal 11N of the recording / reproducing switch 11 without being delayed.

The A-channel RF signal delayed as described above is supplied to the magnetic head 13A via the terminal 11A of the recording / reproducing switch 11 and the recording amplifier 12A, recorded on the magnetic tape, and delayed. B was not
The RF signal of the channel is supplied to the terminal 11 of the recording / reproducing switching device 11.
It is supplied to the magnetic head 13 via B and the recording amplifier 12B and recorded on the magnetic tape. Therefore, A and B
The RF signal of the channel is simultaneously recorded on the magnetic tape.

FIG. 4 is a time chart showing a reproduction signal train of each part of the embodiment of the magnetic recording / reproducing apparatus shown in FIG. The operation of the embodiment shown in FIG. 2 will be described below with reference to FIG. During playback, terminals 3C and 3 of switch 3
D is connected, terminals 7P and 7C of the write clock switch 7 are connected, and terminal 1 of the read clock switch 10 is connected.
0P and 10C are connected, the terminals 11A and 11N of the recording / reproducing switching device 11 are connected, and the recording / reproducing switching device 11 is connected.
11B and 11M are connected.

At the time of reproduction, the A channel and B channel RF signals obtained from the magnetic tape by the magnetic heads 13A and 13B are supplied to the A / D converters 22A and 22B through the reproduction amplifiers 21A and 21B, respectively, and digitally supplied. It is converted into an RF signal. The RF signal of the A channel is supplied to the signal distribution / synthesis circuit 3SM via the terminal N via the terminals 11A and 11N of the recording / reproducing switch 11 without being delayed.

The B channel RF signal is transferred to the memory 4 via the terminals 11B and 11M of the recording / reproducing switch 11.
And is written to the memory 4 in accordance with the reproduction write clock signal supplied from the reproduction write clock generator 6. The B channel RF signal written in the memory 4 is read according to the reproduction read clock signal supplied from the reproduction read clock generator 9. Therefore, the B channel RF signal is delayed by a predetermined time and supplied to the signal distribution / synthesis circuit 3SM via the terminal D1 and the terminal 11M.

The signal synthesizing circuit 3SM synthesizes or superimposes the A channel RF signal input without delay as described above and the B channel RF signal input with delay to input 1 The RF signal of the system is supplied to the equalizer 23 via the terminals 3C and 3D of the switch 3. After the equalizer 23, the PR4 detector 24,
The operations of the Viterbi decoder 25 and the descramble circuit 26 are the same as those of the conventional example shown in FIGS.

According to the embodiments shown in FIGS. 1 and 2, the timing control or delay memory for converting one series of recording signal sequence into two series of recording signals which can be simultaneously recorded in two channels, and two Since the timing control, that is, the delay memory for converting the two series of reproduced signals obtained by the simultaneous reproduction from one channel into the continuous one series of reproduced signal sequence is configured by one memory, the conventional two memories are used. Since the fulfilled function can be realized by one memory, the memory can be saved and the device can be downsized and the cost can be reduced.

In the above embodiment, the recording magnetic head and the reproducing magnetic head are constituted by the same head, but they may be constituted by separate heads.

FIG. 10 shows the configuration of an embodiment of the magnetic reproducing apparatus of the present invention. This embodiment illustrates the present invention as a digital V
This is an example applied to TR. In FIG. 10, magnetic heads 13A and 13B, reproduction amplifiers 21A and 21B,
2 and A / D converters 22A and 22B are shown in FIG.
Is the same as the embodiment described above.

R of the A and B channels obtained from the magnetic tape by the magnetic heads 13A and 13B.
The F signal is supplied to the A / D converters 22A and 22B via the reproduction amplifiers 21A and 21B, respectively, and is converted into a digital RF signal. A channel R
The F signal is supplied to the FIFO buffer 30A, and while the write enable signal ("H") is being output from the write control circuit 31A, a write clock generator (FIG. 2) similar to the write clock 6 generator during reproduction shown in FIG. It is written into the FIFO buffer 30A according to the write clock signal output from (not shown).

A written in the FIFO buffer 30A
As for the RF signal of the channel, while the read enable signal (“H”) is being output from the read control circuit 32A, FIG.
Is read from the FIFO buffer 30A according to a read clock signal output from a read clock generator (not shown) similar to the read clock generator 9 during reproduction.

The B-channel RF signal is supplied to the FIFO buffer 30B, and while the write enable signal ("H") is being output from the write control circuit 31B, it is similar to the write-in-reproduction clock generator 6 of FIG. It is written in the FIFO buffer 30B according to the write clock signal output from the write clock generator (not shown).

B written in the FIFO buffer 30B
As for the RF signal of the channel, while the read enable signal (“H”) is being output from the read control circuit 32B, FIG.
Is read from the FIFO buffer 30B according to a read clock signal output from a read clock generator (not shown) similar to the read clock generator 9 during reproduction. The RF signals of the A and B channels read from the FIFO buffers 30A and 30B are combined,
Is supplied to the equalizer 23.

The write control circuits 31A and 31B use the drum 1 rotation signal, that is, the RF switching pulse SWP.
In response to this, at the change point, the write reset signal is generated and the generation of the write enable signal is started.

The read control circuits 32A and 321B are
The drum 1 delayed for a predetermined time by the delay circuit 33
Upon receiving the rotation signal, that is, the RF switching pulse SWP, the read reset signal is generated and the read enable signal is generated at the change point.

The FIFO buffer 30A receives from the write control circuit 31A and the read control circuit 32A, respectively.
When the write reset signal and the read reset signal are received, the write address pointer and the read address pointer are reset to 0. The FIFO buffer 30B is
When receiving the write reset signal and the read reset signal from the write control circuit 31B and the read control circuit 32B, respectively, the write address pointer and the read address pointer are reset to 0.

FIG. 11 shows the FI of the embodiment shown in FIG.
The write operation of the FIFO buffers 30A and 30B is shown, and FIG. 12 shows the read operation of the FIFO buffers 30A and 30B of the embodiment shown in FIG. Less than,
The operation of the embodiment of FIG. 10 will be described with reference to FIGS. 11 and 12. R of A channel and B channel obtained from the magnetic tape by the magnetic heads 13A and 13B
The F signal is supplied to the A / D converters 22A and 22B via the reproduction amplifiers 21A and 21B, respectively, and is converted into a digital RF signal. A channel R
The F signal is supplied to the FIFO buffer 30A, and the RF signal of the B channel is supplied to the FIFO buffer 30B.

When the drum 1 rotation signal, that is, the RF switching pulse SWP changes, the write control circuits 31A and 31B generate the write reset signal and the write enable signal, respectively.
As a result, the A channel RF signal is sequentially written in the FIFO buffer 30A, and the B channel RF signal is
The data is sequentially written in the FIFO buffer 30B.

After that, after a lapse of time set by the delay circuit 33, the read control circuits 32A and 321B are
In response to the delayed drum 1 rotation signal, that is, the changing point of the RF switching pulse SWP, a read reset signal is generated and a read enable signal is generated. As a result, the A channel RF signal is sequentially read from the FIFO buffer 30A, and
The RF signal of the channel is sequentially read from the FIFO buffer 30B. FIFO buffers 30A and 30B
The RF signals of the A and B channels read from are combined into a single-system RF signal as shown in FIG.

According to the embodiment of FIG. 10, at the changing point of the drum 1 rotation signal, that is, the RF switching pulse,
Since the write address and the read address of the FIFO buffers 30A and 30B are reset, the read address does not overtake the write address, so that stable operation can be realized.

FIG. 13 shows the configuration of another embodiment of the magnetic reproducing apparatus of the present invention. This embodiment takes into consideration variable speed reproduction such as CUE and REVIEW of a digital VTR using a V _X head.

In FIG. 13, magnetic heads 13A and 1A obtained from a magnetic tape wound around a drum 76.
3B supplies the A channel and B channel RF signals to the A / D converters 22A and 22B via the reproduction amplifiers 21A and 21B, respectively, and converts them into digital RF signals.

When the A channel is selected by the control device (not shown), the terminals 41A and 41C of the switch 41 are connected, and the RF signal of the A channel is supplied to the FIFO buffer 30 via the switch 41. ..
Further, when the B channel is selected by the control device (not shown), the terminals 41B and 41B of the switch 41 are connected.
C is connected, and the RF signal of B channel is sent to the switch 4
1 to the FIFO buffer 30.

The level detector 42 detects a period in which the level of the reproduced RF signal of the A channel or B channel is equal to or higher than a predetermined value, and outputs a signal indicating this period to the FIFO enable signal generating circuit 31E.

The drum 1 rotation signal generating circuit 44 is a drum rotation detector 43 such as PG attached to the drum 76.
And outputs a drum 1 rotation signal, that is, a PF switching pulse SWP to the FIFO write enable signal generation circuit 31E, the FIFO write reset signal generation circuit 31R, and the delay circuit 33.

FIFO write enable signal generation circuit 3
1E outputs the write enable signal of the FIFO buffer 30 during a period in which the level of the reproduction RF signal detected by the level detector 42 is equal to or higher than a predetermined value, starting from the change point of the drum 1 rotation signal SWP.

FIFO write reset signal generation circuit 31
The R receives the drum 1 rotation signal, that is, the RF switching pulse SWP, and outputs a write reset signal to the FIFO buffer 30 at the change point.

FIFO read enable signal generation circuit 3
2E is a drum 1 rotation signal delayed by the delay circuit 33 for a predetermined time, that is, an RF switching pulse SW.
Upon receiving P, the generation of the read enable signal is started at the change point.

FIFO read reset signal generation circuit 32
R is a drum 1 rotation signal delayed by the delay circuit 33 for a predetermined time, that is, an RF switching pulse SWP.
In response to this, a read reset signal is generated at the change point.

The FIFO buffer 30 receives the write reset signal and the read reset signal from the FIFO write reset signal generation circuit 31R and the FIFO read reset signal generation circuit 32R, respectively, and resets the write address pointer and the read address pointer to 0. ..

The reproduction RF signal supplied from the terminal 41C to the FIFO buffer 30 is written in the same manner as the reproduction write clock 6 generator in FIG. 2 while the write enable signal is being output from the FIFO write enable signal generating circuit 31E. The data is written in the FIFO buffer 30 according to the write clock signal output from the clock generator (not shown).

The reproduction RF signal written in the FIFO buffer 30 is transferred to the FIFO read enable signal generating circuit 3
While the read enable signal is being output from 2E, it is read from the FIFO buffer 30 according to a read clock signal output from a read clock generator (not shown) similar to the read clock generator 9 during reproduction of FIG.

FIG. 14 shows an example of the movements of the two magnetic heads 13A and 13B which are close to each other during the normal reproduction of the embodiment of FIG. 13 and the reproduction signals of the two adjacent channels, that is, the A and B channels. FIG. 15 shows two magnetic heads 1 which are close to each other during variable speed reproduction in the embodiment of FIG.
An example of the movements of 3A and 13B, the reproduction signals of two adjacent channels, that is, the A and B channels, and the write enable signal is shown. As shown in FIG. 15, during variable speed reproduction, the magnetic heads 13A and 13B cross tracks, that is, between channels, so that the reproduction RF signal becomes an abacus ball shape. During variable speed reproduction, the level detector 42 detects the period during which the reproduction RF signal is above a predetermined level (see FIG. 15B), and only during this period the FI
If the write enable signal is supplied from the FO write enable creation circuit 31E to the FIFO buffer 30 (see FIG. 15).
(See (c)), the storage capacity of the FIFO buffer 30 can be reduced.

FIG. 16 shows an example of the reproduction signal, enable signal and reset signal during the CUE operation of the embodiment of FIG. 13, and FIG. 17 is the REVIE of the embodiment of FIG.
An example of a reproduction signal enable signal and a reset signal at the time of W operation is shown. During variable speed reproduction such as CUE and REVIEW, the rotation of the drum 76 is corrected in order to keep the data rate constant, so the interval of the RF switching pulse is different from that during normal reproduction. In the embodiment of FIG. 13, the write enable signal, the write reset signal, the read enable signal, and the read reset signal are sent to the FIFO buffer 30 based on the drum 1 rotation signal, that is, the RF switching pulse SWP.
Since it is output to, accurate and stable write and read operations can be performed.

By adjusting the storage capacity of the FIFO buffer 30 to the maximum data amount (for one rotation of the drum) during variable speed reproduction, stable operation can be ensured. For example, the data amount when the drum rotation speed is 150 Hz is about 120,000 bits, and the data amount when the drum rotation speed is 70 Hz is about 300,000 b.
Its. In this case, a FIFO buffer with a storage capacity of 300 Kbits may be prepared.

[0062]

According to the magnetic recording / reproducing apparatus of the first aspect,
1 series of recorded signal train can be recorded simultaneously on 2 channels 2
A timing control memory for converting a series of recorded signals and a timing control memory for converting two series of reproduced signals obtained by simultaneous reproduction from two channels into one continuous reproduced signal sequence Since the memory is configured by one memory, the function conventionally performed by two memories can be realized by one memory, so that the memory can be saved, and the device can be downsized and the cost can be reduced.

According to the magnetic reproducing apparatus of the second aspect, the period during which the level of the reproduced signal during variable speed reproduction is equal to or higher than the predetermined value is detected, and the reproduced signal can be written in the memory during this period. Since only the high-level reproduction signal is stored in the memory, the memory can be saved, and the device can be downsized and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a magnetic recording / reproducing apparatus according to an embodiment of the present invention in a recording state.

FIG. 2 is a block diagram showing a magnetic recording / reproducing apparatus according to an embodiment of the present invention in a reproducing state.

FIG. 3 is a time chart showing a recording signal sequence of each part of the embodiment of the magnetic recording / reproducing apparatus shown in FIG.

FIG. 4 is a time chart showing a reproduction signal sequence of each part of the embodiment of the magnetic recording / reproducing apparatus shown in FIG.

5 is an explanatory diagram showing an example of a head arrangement of the magnetic recording / reproducing apparatus shown in FIGS. 1 and 2. FIG.

6 is an explanatory diagram showing an example of the azimuth of the head of the magnetic recording / reproducing apparatus shown in FIGS. 1 and 2. FIG.

FIG. 7 is an explanatory diagram showing an example of a recording pattern of a head of the magnetic recording / reproducing apparatus shown in FIGS. 1 and 2.

8 is a plan view and a side view showing an example of a head and a tape of the magnetic recording / reproducing apparatus shown in FIGS. 1 and 2. FIG.

FIG. 9 is an explanatory diagram showing that tape vibration occurs due to eccentricity of a drum.

FIG. 10 is a block diagram showing the configuration of an embodiment of the magnetic reproducing apparatus of the present invention.

FIG. 11 is a time chart showing the write operation of the FIFO buffers 30A and 30B of the embodiment shown in FIG.

12 is a time chart showing the read operation of the FIFO buffers 30A and 30B of the embodiment shown in FIG.

FIG. 13 is a block diagram showing the configuration of another embodiment of the magnetic reproducing apparatus of the present invention.

FIG. 14 is an explanatory diagram showing an example of movements of two heads that are close to each other during normal reproduction and reproduction signals of two channels that are close to each other in the embodiment of FIG.

FIG. 15 is an explanatory diagram showing an example of movements of two heads in close proximity, reproduction signals of two adjacent channels, and a write enable signal during variable speed reproduction in the embodiment of FIG.

FIG. 16 is an explanatory diagram showing an example of a reproduction signal, an enable signal, and a reset signal during the CUE operation of the embodiment of FIG.

FIG. 17 is an explanatory diagram showing an example of a reproduction signal enable signal and a reset signal during the REVIEW operation of the embodiment of FIG.

FIG. 18 is a block diagram showing an example of the configuration on the recording side of a digital VTR that uses a conventional stepped V _X head.

FIG. 19 is a block diagram showing an example of the configuration on the reproducing side of a digital VTR using a conventional stepped V _X head.

[Explanation of symbols]

 4 memory 5 write clock generator for recording 6 write clock generator for playback 7 write clock switch 8 read clock generator for recording 9 read clock generator for playback 10 read clock switch 11 recording / playback switch 12A, 12B recording amplifier 13A, 13B Magnetic head 21A, 21B Reproducing amplifier 22A, 22B A / D converter 30, 30A, 30B FIFO buffer 31A, 31B Write control circuit 31E FIFO write enable signal creating circuit 31R FIFO write reset signal creating circuit 32A, 32B Read control circuit 32E FIFO read enable signal generation circuit 32R FIFO read reset signal generation circuit 33 Delay circuit 44 Drum 1 rotation signal generation circuit

Claims (2)

[Claims] 1. A magnetic recording / reproducing apparatus for simultaneously recording in two channels of a magnetic recording medium by two magnetic heads arranged close to each other and having different azimuth angles, and reproducing simultaneously from the two channels. A timing control memory for converting a recording signal sequence into two series of recording signals that can be simultaneously recorded in the two channels, and two series of reproducing signals obtained by simultaneous reproduction from the two channels, in one continuous series. A magnetic recording / reproducing apparatus characterized in that a timing control memory for forming a reproduction signal sequence is constituted by one memory. 2. A magnetic reproducing apparatus for reproducing simultaneously from two channels of a magnetic recording medium by two magnetic heads arranged close to each other and having different azimuth angles, and two series obtained by simultaneous reproduction from the two channels. A timing control memory for converting the reproduced signal of FIG. 1 into a continuous series of reproduced signal sequence, level detection means for detecting a period during which the level of the reproduced signal during variable speed reproduction is equal to or more than a predetermined value, and the level detection Write control means for enabling writing of the reproduction signal to the memory during the period detected by the means.