JPH0528049A - Microcomputer - Google Patents

Abstract

PURPOSE:To prevent the reading of the entire program and data in a built-in ROM even under a memory expansion mode. CONSTITUTION:This microcomputer is provided with a built-in ROM consecutive reference detection circuit 12 detecting whether or not the consecutive reference for a built-in flash EEPROM 3 by the only instruction of the same program counter value based on a program counter value from a program counter 10, an instruction code from an instruction register 11, and an internal address bus 5 in a CPU 2. When the built-in ROM consecutive reference detection circuit 12 detects more than the prescribed number of consecutive reference for the built-in ROM, it outputs a signal actuating this to a deletion circuit 13 of the built-in flash EEPROM 3, and deletes the contents of the built-in flash EEPROM 3 by the deletion circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a built-in ROM and an external memory, and having a memory expansion mode in which both the built-in ROM and the external memory can be used as a program memory.

[0002]

2. Description of the Related Art A microcomputer is known in which an external memory is provided in addition to a built-in ROM in order to increase the memory capacity, and both of them can be used as a program memory by setting a memory expansion mode.

FIG. 4 is a block diagram showing a conventional electric batch erasing type flash EEPROM built-in microcomputer having a memory expansion mode. In FIG. 4, 1 is a microcomputer, 6 is an external memory, and 7 is an external device. ing. The microcomputer 1 includes a CPU 2 and a built-in flash EEPROM 3, and an internal data bus 4 and
Connected to each other through the internal address bus 5,
The external memory 6 and the external device 7 are also connected through the external data bus 8 and the external address bus 9.

The operation of such a conventional microcomputer with a built-in ROM will be described. The CPU 2 can set three operation modes, a write mode, a read mode and a microcomputer mode. In the write mode, the function of the CPU2 is stopped by the control of the external device 7 and the external data bus 8 and the internal data bus 4 are passed to the memory area of the built-in flash EEPROM3 corresponding to the address designated through the external address bus 9 and the internal address bus 5. The given data is to be written.

The read mode is the built-in flash EEPR.
This is a mode for verifying the data written in OM3. Similarly, the function of CPU2 is stopped by the control of external device 7, and the built-in flash corresponding to the address specified through external address bus 9 and internal address bus 5. EE
Data can be read out from the memory area of PROM3 through the internal data bus 4 and the external data bus 8.

Further, the microcomputer mode is a mode for causing the microcomputer 1 to perform a normal operation, and the microcomputer 1 executes the program stored in the built-in flash EEPROM 3. By the way, in the microcomputer, the read mode is not disclosed to a third party, and even if an address is given from the external device 7 through the external address bus 9 and the internal address bus 5 in the microcomputer mode, the contents stored in the built-in flash EEPROM 3 are stored. For confidentiality, it is designed so that data cannot be read.

[0007]

In the case where the memory expansion mode is provided as described above, for example, when the CPU 2 executes a transfer instruction held in a predetermined address corresponding area in the external memory 6, the transfer source address If the address of the built-in flash EEPROM3 is specified as and the address of the external memory 6 is specified as the transfer destination address, the stored data in the built-in flash EEPROM3 can be taken out to the external memory 6 even in the microcomputer mode. Become.

A built-in flash EEPROM is used as a transfer source address of a transfer instruction held at a predetermined address of the external memory 6.
Specify the start address of OM3, specify the specified address of the external memory 6 as the transfer destination address, and use CP to loop.
It is possible to transfer all the data in the built-in flash EEPROM 3 to the external memory 6 by making U2 repeatedly update the transfer instruction and incrementing the transfer source address and the transfer destination address each time it is executed.

In the microcomputer with the built-in flash EEPROM 3 provided with such a memory expansion mode, even if the read mode is not disclosed to a third party, the built-in flash EEPROM can be read by the program held in the external memory.
There is a problem that the contents of the built-in flash EEPROM3 can be read by referencing the data of 3 as an operand, making it difficult to keep secret.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a microcomputer capable of preventing reading of data stored in a built-in ROM.

[0011]

In a microcomputer according to the present invention, an electrically rewritable ROM,
In a microcomputer provided with another memory used as a program memory in the memory expansion mode set by the CPU, a continuous reference detection circuit for detecting continuous reference of the ROM only by an instruction of the same program counter value, and the continuous reference It is activated based on a detection signal from a detection circuit and erases the contents of the ROM. In the microcomputer according to the second aspect of the present invention, an address determination unit that determines whether the address from the CPU is an address in the ROM, and determines whether the instruction from the CPU is an instruction that involves the reference of the ROM. Is provided to store the instruction counter and the program counter value, and the CPU is executing the instruction with reference to the ROM based on the output of the address determiner and the instruction determiner, and the address in the ROM A first register that updates and holds the program counter value that is already held when it is output to the program counter value of the instruction that is being executed, and a second register that holds the program counter value before updating in the first register A register, a comparator for comparing the program counter values held by the first and second registers, and the number of continuous reference times is counted based on the comparison result of the comparator. Or a counter for resetting and outputting a detection signal to the means for erasing the contents of the ROM when the count value exceeds a predetermined value. In the microcomputer according to the third aspect of the present invention, a continuous reference detection circuit for detecting continuous reference of ROM only by an instruction of the same program counter value, a sense amplifier circuit for detecting data output of ROM, and the continuous reference. And a means for stopping the operation of the sense amplifier circuit when the detection circuit detects the continuous reference.

[0012]

According to the present invention, in the memory expansion mode in which the ROM and other memories are used as the program memory, when the continuous reference detection circuit detects the continuous reference only by the instruction of the same program counter value, the erasing means is activated and the ROM is activated. Erase the contents of and prevent its reading. Further, according to the present invention, the address determination unit and the instruction determination unit determine whether or not the address of the ROM and whether or not the instruction involves the reference of the ROM,
When the instruction that is the address of the ROM and that also refers to the ROM is executed, the program counter value held in the first register is updated every time the instruction that refers to the ROM is executed, and this is updated to the second register. The comparator compares the previous program counter value held in the counter with the comparator, and the counter counts the reference count based on the comparison result of the comparator, and the continuous reference detection is performed. Furthermore, in the third invention,
When the continuous reference detection circuit detects the continuous reference, the operation of the sense amplifier circuit is stopped and further continuous reference is disabled.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. (Embodiment 1) FIG. 1 is a block diagram of a microcomputer according to the present invention, in which 1 is a microcomputer,
2 is a CPU, 3 is a flash EEPROM of electrical batch erase type,
Reference numeral 12 shows a built-in ROM continuous reference detection circuit. These CP
U2, Flash EEPROM3 and built-in ROM continuous reference detection circuit
12 are directly connected to each other, and are also connected to each other through an internal address bus 5 and an internal data bus 4.

The CPU 2 has a program counter 10 and an instruction register 11. The program counter 10 outputs the program counter value, and the instruction register 11 outputs the instruction code to the internal ROM continuous reference detection circuit 12. Has become. The built-in ROM continuous reference detection circuit 12 outputs a detection signal to the flash EEPROM 3 when a predetermined condition is satisfied, based on the input program counter value and instruction code, and the specified address input through the address bus 5.
Is output to the erasing circuit 13. flash
When a detection signal is input to the erasing circuit 13 of the EEPROM 3, the erasing circuit 13 is activated to erase the stored contents of the flash EEPROM 3 and prevent further reading of the stored contents.

FIG. 2 is a block diagram showing a specific structure of the internal ROM continuous reference detecting circuit 12, in which 21 is an address judging section to which an address from the internal address bus 5 is inputted, 22.
Indicates an instruction code judging section to which an instruction code is inputted from the instruction register 11. The address determination unit 21 uses the built-in flash for the address fetched through the internal address bus 5.
The instruction code determination unit 22 determines whether the address is in the EEPROM3, and the instruction code determination unit 22 determines the instruction code being executed by the CPU2 in the instruction register 11
, And determine whether the instruction code is an instruction that involves referencing the stored data in flash EEPROM3,
A signal corresponding to each is output to the AND gate 23.

The address determination unit 21 has an address flash
As a result of determining whether the address is in the EEPROM3, if the address is in the flash EEPROM3, for example, a signal "1" is output, and otherwise, a signal "0" is output,
On the other hand, the instruction code determination unit 22 has an instruction code of flash EEPROM.
As a result of determining whether the instruction involves referring to the data stored in OM3, for example, if the instruction involves referencing, signal "1"
In other cases, the signal "0" is output. This ensures that the address
Address in OM3, and instruction code flash
If the instruction involves referring to the data stored in the EEPROM 3, the AND gate 23 to the comparator 24 and the first switch 26
Signal is output to.

When the signal (comparison start signal) from the AND gate 23 is input to the comparator 24, the program counter values held therein are input from the first register 27 and the second register 29, respectively, and the comparison is performed. It is supposed to start. The comparator 24 compares the program counter value of the instruction being executed by the CPU 2 input from the first register 27 with the program counter value previously executed by the CPU 2 input from the second register 29, and the comparison is completed. Then, a signal (comparison end signal) is output to the second switch 28, and when the results of comparison match, a count-up signal to the counter 25,
When they do not match, a reset signal is output to the counter 25, respectively.

The first switch 26 is turned on each time a signal from the AND gate 23 is input, and the CPU 2 causes the program counter value of the instruction currently being executed by the CPU 2 to be input to the first register 27, and the program already held therein. Replace with the count value,
The second switch 28 is turned on each time a comparison end signal is input from the comparator 24, and the program counter value held in the first register 27 is input to the second register 29. As a result, the first register 27 holds the program counter value of the instruction currently being executed by the CPU 2 input through the first switch 26, and the second register
The register 29 holds the program counter value of the instruction previously executed by the CPU 2.

Next, the operation of the microcomputer according to the present invention will be described. Built-in ROM continuous reference detection circuit 12
Is an address through the internal address bus 5, an instruction code from the instruction register 11, and a program counter.
The program counter value is fetched from 10 respectively. The address determination unit 21 determines whether or not the address is an address in the built-in flash EEPROM 3, and the instruction code determination unit 22 determines whether or not the instruction is an instruction accompanied by reference to the data in the built-in flash EEPROM 3. When the address is an address in the built-in flash EEPROM3 and the instruction code is an instruction accompanied by data reference in the built-in flash EEPROM3, a predetermined signal is output from the AND gate 23 to the comparator 24 and the first switch 26. To be done.

The first switch 26 is turned on, and the program count value of the instruction being executed by the CPU 2 is stored in the first register 23. Comparator 24 is the first register 27, the second register
The current program count value and the previous program count value are fetched from 29, respectively, and compared with each other. If they match, a count-up signal is output to the counter 25, and if they do not match, a reset signal is output. When the comparison is completed, the comparator 24 outputs the comparison end signal to the second switch 28. The comparison end signal outputs "1" when the comparison by the comparator 24 is completed, and outputs "0" otherwise. The second switch 28 is turned on when the signal is "1" and turned off when the signal is "0", and when the comparison is completed, the second switch 28 is turned on and the value stored in the first register 27 is It will be stored in the second register 29.

The counter 25 increments the count value by the count-up signal and is reset by the reset signal. When the count value exceeds a predetermined value, in other words, when a digit overflows, a detection signal is output to the erasing circuit 13 of the built-in flash EEPROM 3, and the erasing circuit 13 is activated to erase the entire contents of the built-in flash EEPROM 3. For example, if the counter 25 is an 8-bit counter, CPU2
For the instruction with the same program counter value, if the built-in flash EEPROM3 is referred to 256 times continuously, the built-in flash EE
All contents of PROM3 will be erased.

(Embodiment 2) FIG. 3 is a block diagram showing another embodiment of the present invention. In Embodiment 2, the detection signal from the internal ROM continuous reference detection circuit 12 is the internal flash EEPR.
The data output stored in OM3 is detected and input to the sense amplifier circuit 33 which outputs it to the internal data bus 4. Other configurations are substantially the same as those shown in FIGS. 1 and 2, and corresponding parts are designated by the same reference numerals.

As described above, in the second embodiment, the built-in flash EE is issued by the instruction of the same program counter value as described above.
When the built-in ROM continuous reference detection circuit 12 detects that the PROM3 has been continuously referred to a predetermined number of times, the operation of the sense amplifier circuit 33 is stopped, and thereafter, the correct data cannot be read from the built-in flash EEPROM3. In the second embodiment, the built-in flash EEPROM3 has been described, but it goes without saying that it can be applied to all the ROMs such as the mask ROM and EPROM.

[0024]

As described above, according to the present invention, even if the memory expansion mode can be set, the reading of all programs and data stored in the built-in ROM can be prevented, and the program and data can be saved. The present invention has excellent effects such as improved confidentiality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a microcomputer according to the present invention.

FIG. 2 is a block diagram of a built-in ROM continuous reference detection circuit used in the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional microcomputer with a built-in ROM.

[Explanation of symbols]

2 CPU 3 Built-in flash EEPROM 4 Internal data bus 5 Internal address bus 10 Program counter 11 Instruction register 12 Built-in ROM continuous reference detection circuit 13 Erase circuit 21 Address judgment section 22 Instruction code judgment section 23 AND GATE 24 comparator 25 counter 26 First switch 27 First register 28 Second switch 29 Second register 33 Sense amplifier circuit

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[Procedure amendment]

[Submission date] February 7, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

In a microcomputer according to the present invention, an electrically rewritable ROM,
In a microcomputer provided with another memory used as a program memory in the memory expansion mode set by the CPU, a continuous reference detection circuit for detecting continuous reference of the ROM only by an instruction of the same program counter value, and the continuous reference It is activated based on a detection signal from a detection circuit and erases the contents of the ROM. In the microcomputer according to the second aspect of the present invention, an address determination unit that determines whether the address from the CPU is an address in the ROM, and the instruction from the CPU involves the reference of the memory. An instruction determination unit for determining whether or not a program counter value is stored, and the CPU is executing an instruction involving memory reference based on the output of the address determination unit and the instruction determination unit. A first register that updates and holds the program counter value that is already held when the address in the ROM is output to the program counter value of the instruction that is being executed, and a program counter value before updating in the first register Based on the comparison result of the comparator, which compares the second register held by the second register and the program counter value held by the first and second registers, the continuous reference count is counted. A counter for outputting a detection signal to the means for erasing the contents of the ROM when the count value exceeds a predetermined value.
In the microcomputer according to the third aspect of the present invention,
If the continuous reference detection circuit that detects the continuous reference of the ROM only by the instruction of the same program counter value, the sense amplifier circuit that detects the data output of the ROM, and the continuous reference detection circuit detects the continuous reference, Means for stopping the operation of the sense amplifier circuit.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012]

According to the present invention, the erasing means is activated when the continuous reference detection circuit detects the continuous reference of the ROM only by the instruction of the same program counter value in the memory expansion mode in which the ROM and other memories are used as the program memory. hand
Erases the contents of ROM and blocks its reading. In the present invention also address determination unit, whether the address of the instruction judgment unit ROM, determines whether the instruction or not with reference to the memory, the address of the ROM, moreover instruction involving memory references In some cases, the program counter value held in the first register is updated each time an instruction involving ROM reference is executed, and this value is compared with the previous program counter value held in the second register. Then, the counter counts the reference number based on the comparison result of the comparator, and the continuous reference detection is performed. Further, in the third invention, when the continuous reference detection circuit detects a continuous reference,
The operation of the sense amplifier circuit is stopped and further continuous reference becomes impossible.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

FIG. 2 is a block diagram showing a specific structure of the internal ROM continuous reference detecting circuit 12, in which 21 is an address judging section to which an address from the internal address bus 5 is inputted, 22.
Indicates an instruction code judging section to which an instruction code is inputted from the instruction register 11. The address determination unit 21 uses the built-in flash for the address fetched through the internal address bus 5.
The instruction code determination unit 22 determines whether the address is in the EEPROM3, and the instruction code determination unit 22 determines the instruction code being executed by the CPU2 in the instruction register 11
Are read from the AND gate 23, and it is determined whether or not the instruction code is an instruction accompanied by a memory reference , and a signal corresponding to each is output to the AND gate 23.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

The address determination unit 21 has an address flash
As a result of determining whether the address is in the EEPROM3, if the address is in the flash EEPROM3, for example, a signal "1" is output, and otherwise, a signal "0" is output,
On the other hand, the instruction code determination unit 22 outputs a signal "1" if the instruction code is an instruction accompanied by a memory reference and outputs a signal "1" if the instruction is an instruction accompanied by a reference, and outputs a signal "0" otherwise. It is supposed to do. This ensures that the address is in the internal flash EEPROM3,
If the instruction code is an instruction accompanied by a memory reference , the AND gate 23 to the comparator 24 and the first switch 26
Signal is output to.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

Next, the operation of the microcomputer according to the present invention will be described. Built-in ROM continuous reference detection circuit 12
Is an address through the internal address bus 5, an instruction code from the instruction register 11, and a program counter.
The program counter value is fetched from 10 respectively. The address determination unit 21 determines whether or not the address is an address in the built-in flash EEPROM 3, and the instruction code determination unit 22 determines whether or not the instruction code is an instruction involving memory reference .
When the address is the address in the built-in flash EEPROM 3 and the instruction code is an instruction accompanied by a memory reference , a predetermined signal from the AND gate 23 gives a predetermined signal to the comparator 24, the first
Output to the switch 26 of.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

The first switch 26 is turned on, and the program counter value of the instruction being executed by the CPU 2 is stored in the first register 23. Comparator 24 is the first register 27, the second register
Each current program counter value from the 29, the last of the programming
The ram counter value is fetched and compared, and if they match, a count-up signal is output to the counter 25, and if they do not match, a reset signal is output. When the comparison is completed, the comparator 24 outputs the comparison end signal to the second switch 28. The comparison end signal outputs "1" when the comparison by the comparator 24 is completed, and outputs "0" otherwise. The second switch 28 is turned on when the signal is "1" and turned off when the signal is "0", and when the comparison is completed, the second switch 28 is turned on and the value stored in the first register 27 is It will be stored in the second register 29.

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Claims (3)

[Claims] 1. A microcomputer comprising an electrically rewritable ROM and another memory used as a program memory in a memory expansion mode set by a CPU, wherein the ROM is provided only by an instruction of the same program counter value. A microcomputer comprising: a continuous reference detection circuit for detecting a continuous reference; and a means which is activated on the basis of a detection signal from the continuous reference detection circuit and erases the contents of the ROM. 2. An address determination unit for determining whether or not an address from the CPU is an address in the ROM, and an instruction from the CPU
An instruction determination unit that determines whether or not the instruction involves referring to ROM,
It is provided to store the program counter value, and when the CPU is executing an instruction with reference to ROM based on the output of the address determination unit and the instruction determination unit, and when the address in the ROM is output, A first register for updating the held program counter value to the program counter value of the instruction being executed; a second register for holding the unupdated program counter value in the first register; A comparator that compares the program counter value held in the second register with the comparator, that counts the number of consecutive references based on the comparison result of the comparator, or resets and outputs a detection signal to the ROM when the count value exceeds a predetermined value. 2. The microcomputer according to claim 1, further comprising a counter for outputting the contents to a means for erasing the contents. 3. A microcomputer provided with R0M, another memory, and a CPU capable of setting an extended mode in which both R0M and the other memory are used as a program memory, ROM having only the same program counter value instruction. Continuous reference detection circuit for detecting the continuous reference of, a sense amplifier circuit for detecting the data output of the ROM, and means for stopping the operation of the sense amplifier circuit when the continuous reference detection circuit detects the continuous reference. A microcomputer comprising: