JPH0527874A - Reset circuit - Google Patents

Abstract

PURPOSE:To prevent a reset signal from being outputted by mistake when power supply voltage lowers temporarily at the time of starting load, etc. CONSTITUTION:When power supply voltage lowers lower than the set reference voltage, a reset circuit 1 outputs a reset signal. The reference voltage is the output voltage of a voltage dividing circuit 3 and the source drain of an electric field-effect transistor Q is connected to the both ends of one of a resistor R2 of the circuit 3. When load which makes power supply voltage lower temporarily is controlled by a processor 2, the electric field-effect transistor Q is temporarily turned on by the control signal of a processor 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit which outputs a reset signal to reset a processor when the power supply voltage drops below a set reference voltage.

[0002]

2. Description of the Related Art Generally, a processor used for controlling a load in a programmable controller or various devices cannot guarantee the operation when the power supply voltage drops below a predetermined value. Therefore, as shown in FIG. 3, when the power supply voltage becomes equal to or lower than the set reference voltage, the reset circuit 1 that outputs the reset signal RS is connected to the processor 2
, And when the power supply voltage drops below the reference voltage,
The processor 2 is reset.

That is, the reset circuit 1 is provided with a voltage dividing circuit 3 composed of a pair of resistors R ₁ and R ₂ connected in series for dividing the power supply voltage, and the output voltage of the voltage dividing circuit 3 is a reset signal formed by an integrated circuit. The reference voltage is stabilized and set to a reference voltage inside the generation circuit 4, and the reference voltage and the reset signal generation circuit 4
When the power supply voltage becomes equal to or lower than the reference voltage, the reset signal RS is transmitted. A clock signal CK is input to the reset signal generation circuit 4 in order to synchronize with the processor 2.

[0004]

By the way, when the load controlled by the processor 2 is a motor or the like, an inrush current flows at the time of startup, so that the power supply voltage is temporarily lowered. The power supply circuit of the processor 2 is normally configured to hold the voltage and guarantee the operation against such a temporary decrease of the power supply voltage, but the reset circuit 1 has a decrease in the power supply voltage. There is a problem that a reset signal is output in response to.

An object of the present invention is to solve the above problems, and to provide a reset circuit which prevents a reset signal from being erroneously output even if the power supply voltage is temporarily reduced at the time of starting a load. Is to

[0006]

In order to achieve the above object, the present invention provides a reset circuit that resets a processor by outputting a reset signal when the power supply voltage drops below a set reference voltage. When the processor controls the load to be temporarily reduced, the reference voltage switching means for lowering the reference voltage relative to the power supply voltage is provided during the period when the voltage is reduced by the load.

[0007]

According to the above configuration, when the processor controls a load that temporarily reduces the power supply voltage, the reference voltage is lowered relative to the power supply voltage during the period when the power supply voltage is temporarily reduced. Since the reference voltage switching means is provided in the, the reset signal may be erroneously output when controlling a load, such as a motor, that temporarily reduces the power supply voltage due to the inrush current flowing at startup. It can be prevented.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, as compared with the conventional configuration shown in FIG. 3, a source-drain of a field effect transistor Q, which is a switching element, is connected between both ends of one resistor R ₂ of a voltage dividing circuit 3. The difference is that you did. To the gate of the field effect transistor Q, a control signal which becomes H level when a control signal for temporarily controlling the load that lowers the power supply voltage is generated is input. Such a signal can be easily obtained from the interface to which the load is connected.

According to the above structure, when the field effect transistor Q is turned on, both ends of the resistor R ₂ are short-circuited, so that the reference voltage input to the reset signal generating circuit 4 becomes 0V. That is, the output voltage of the voltage dividing circuit 3 is 0
When the voltage becomes V, the reference voltage obtained based on the output voltage of the voltage dividing circuit 3 also becomes 0 V, the reference voltage becomes relatively low with respect to the power supply voltage, and the reset signal cannot be generated. In this way, the field effect transistor Q
The voltage dividing circuit 3 constitutes the reference voltage switching means. By providing such a reference voltage switching means, as shown in FIG. 2A, as shown in FIG. 2B, during the period in which the power supply voltage is temporarily reduced due to the inrush current to the load or the like, as shown in FIG. When the field effect transistor Q is turned on, the reset signal is not generated during this period and the processor 2 is prevented from being reset accidentally. Further, the field effect transistor Q is turned on for a fixed time, and when the voltage lowering time exceeds the set time, the field effect transistor Q is turned off and the reference voltage rises. ,
A reset signal will be generated.

Other configurations and operations are similar to those of the conventional configuration shown in FIG. It should be noted that when the power supply voltage is temporarily reduced, the reference voltage may be relatively reduced with respect to the power supply voltage which is the comparison voltage, and therefore the configuration is not limited to the above-described embodiment, and the power supply is not limited. The voltage obtained by dividing the voltage may be compared with the reference voltage, and the voltage division ratio may be switched when the power supply voltage temporarily drops.

[0011]

As described above, according to the present invention, when the processor controls a load that temporarily reduces the power supply voltage, the reference voltage is set relative to the power supply voltage during the period when the power supply voltage is temporarily reduced. Since the reference voltage switching means is provided to lower the voltage, the reset signal is erroneously output when controlling a load, such as a motor, that temporarily reduces the power supply voltage due to the inrush current flowing at startup. This has the advantage that it can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment.

FIG. 2 is an explanatory diagram of the operation of the embodiment.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1 reset circuit 2 processor 3 voltage dividing circuit 4 reset signal generating circuit Q field effect transistor

Claims (1)

Claim: What is claimed is: 1. In a reset circuit that outputs a reset signal to reset the processor when the power supply voltage drops below a set reference voltage, the processor controls a load that temporarily reduces the power supply voltage. In this case, the reset circuit comprises a reference voltage switching means for lowering the reference voltage relative to the power supply voltage during the period when the voltage is reduced by the load.