JPH0527726A - Video input hard copy device - Google Patents

Abstract

PURPOSE:To provide a color video printer which automatically set input conditions of a video signal. CONSTITUTION:A computer 17 or 101 generates a test signal for entire-surface maximum brightness, a sequence generating circuit 45 and a mechanism control circuit 65 measures the horizontal scanning period and the number of horizontal scanning lines of the test signal, and temporary input conditions are found by arithmetic from the value. Under the input conditions, a test video signal is inputted to an image memory 60, an image area and a non-image area are measured from the input data, and the input conditions are calculated from the values. Since the input conditions can automatically be found, video signals of different standards can easily be switched and inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for making a hard copy of a video input signal, and more particularly to a video input hard copy apparatus suitable for making a hard copy when the video input signal has various specifications.

[0002]

2. Description of the Related Art As a method for printing an image displayed on a display by a thermal transfer video printer,
JP-A-57-65081 and JP-A-58-2122
No. 87, the video signal input to the display is taken out and input to the video input interface, where the brightness of each pixel is converted into a digital signal, and the thermal head of the thermal head is converted according to the digital amount. It is known that the amount of ink transferred is controlled by changing the amount of heat generated by a resistor to create an image.
In this case, the specifications of the video signal system, the number of display pixels, the period of showing the image signal and the period of showing the synchronizing signal are different depending on the manufacturer, and there are various specifications between the same type of display systems. I was dealing with it by manually setting the input conditions of the video input interface so that

[0003]

In the conventional apparatus in which the setting value of the input condition is manually changed according to the specifications of the input video signal, the setting of the input condition, the printing and the judgment of the result are repeated many times. There was a problem such as wasting paper, and setting time was long and annoying.

An object of the present invention is to automatically obtain and set input conditions of a video signal, to enable switching input of a plurality of video signals, and to easily print the input video signal at a designated position. Providing a video input hard copy device.

[0005]

SUMMARY OF THE INVENTION The above-mentioned object is to take an input video signal, digitize it in a state where an input condition corresponding to the specifications of the input video signal is set and digitize it as image data to the image memory. Input interface means for storing, recording mechanism section, and halftone control means for converting image data stored in the image memory or image data inputted digitally from outside into an input signal to the recording mechanism section. And a mechanism control unit having a function of setting the input information in the input interface unit and an operation control function of the recording mechanism unit, in the interface unit, an input video signal is created. The display error of the image created by the image creating means that is the signal created by the image creating means. And when the test signal generated to distinguish them hidden area is entered, it provided the number of scanning lines measuring means for measuring the number of horizontal scanning lines of said test signal,
The mechanism control means uses the number of horizontal scanning lines of the test signal measured by the scanning line number measuring means when all image data in the display area and non-display area of the test signal is a display area. The input condition is obtained and set in the input interface means, and in the set state, the test signal is input to the image memory by the input interface means, and subsequently the image data of the test signal input to the image memory is input. The size of the display area and the non-display area is checked to detect the input condition for the image creating device from the detected size and set in the input interface means, thus creating in the image creating device. Achieved by controlling the captured image data into the image memory, and also creates the input video signal The image creating apparatus is provided with a specification storing means for storing specifications of a video signal created by the apparatus, and the mechanism controlling means first reads the specifications from the specification storing means to obtain the input condition when capturing the video signal. This is achieved by setting the input condition in the input interface means and controlling so that the image data created by the image creating apparatus can be loaded into the image memory.

[0006]

The input condition of the input video signal can be automatically obtained by using the test signal capable of distinguishing the display area from the non-display area, and the necessary input condition can be prepared in advance on the image forming means side. , By inputting it, the input condition can be set immediately, so the operation is extremely easy and can be done in a short time. Further, since the number of horizontal pixels and the number of vertical pixels are obtained in the input conditions, it becomes easy to accurately record an image at a specified position on a recording paper having a specified size.

[0007]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a thermal transfer color printer.
The video signal created in step 1 and displayed on the display 1 is branched by the signal distributor 50, and the video signal created by the computer 101 and displayed on the display 104 is branched by the signal distributor 50 and branched by the multiplexer 53. One of them is selected and input to the thermal transfer color printer 18 for printing. Here, the image created by the computer 17 is an RGB separate video signal, and an R image signal 6 indicating R (red) of the color image signal, a G image signal 5 indicating G (green), and a B image signal B.
It is composed of a B image signal 4 indicating (blue), a horizontal synchronizing signal 3, and a vertical synchronizing signal 2. The RGB separate video signal 102 created by the computer 101 is also configured in the same manner. Note that the input video signal includes a composite video signal in which an image signal and a synchronizing signal are integrated. In this case, the horizontal and vertical synchronizing signals 3 and 2 are included in any of the image signals 4 to 6. Has been. Amplifiers 7, 8, 9, 1 provided in the video signal distributor 50
Reference numerals 3 and 14 denote buffer amplifiers that prevent the branched video signal from being attenuated. The multiplexer 53 selects an input according to the select signal 47, and this signal 47 can also be commanded by the digital signal input interface 38 from the computer 17 or 101.

The thermal transfer color printer 18 comprises a recording control section 19 and a recording mechanism section 80. Recording control unit 1
Reference numeral 9 includes an input interface section including a digital signal input interface 38 and a video signal input interface 20, an image memory 60, a halftone control circuit 61, a mechanism control circuit 65, a display / operation switch 62, and a power source 66. The circuit is connected to a bus 59 composed of image signals and control signals. On the other hand, since the recording mechanism section 80 is not directly related to the present invention, the recording control section 1
Only the portion directly related to 9 is shown with a reference numeral, and the thermal head 85 for drawing on the recording paper, this head 85
It has a mode motor 81 for pressing on the recording paper at the time of drawing, a drum motor 92 for conveying the recording paper, and the like.

Hereinafter, more detailed configurations and functions of each unit and details of a video signal to be handled will be sequentially described. First, when the above-mentioned thermal transfer color video printer 18 prints a digital signal 39 created by the computer 17 or 101 and digitized, the signal 39 is fetched by the digital signal input interface 38 and stored in the image memory 60, or Or direct halftone control circuit 6
Enter 1 and print. When the image signals generated by the computers 17 and 101 are input as video signals, the video signals are digitized by the video input interface 20 and stored in the image memory 60. Selection of these video signal inputs is controlled by the mechanism control circuit 65 according to a command from the display / operation switch 62. Halftone control circuit 6
1 is a logical operation of R, G, and B image data stored in the image memory 60, Y = B inversion, M = G inversion, C = R
To output the head control signal 69 consisting of input data for heating the thermal head 85 and energizing pulse. The input data specifies the dots that generate heat, and the energizing pulse controls the heat generation time.

When the mechanism control circuit 65 receives a print command from the computers 17 and 101 via the display / operation switch 62 or the digital interface 38, the ink color detection sensor 94 of the recording mechanism section 80 and various sensors (not shown). Head control signal from the halftone control circuit 61 applied to the thermal head 85 by program-controlling the mode motor 81 and the drum motor 92 by the mode motor drive signal 72 and the drum motor drive signal 70 according to the detection signal 71 of FIG. Control is performed so that printing with a constant voltage from the power source 69 and the power source 66 is performed correctly.

Next, details of the video input interface 20 will be described. FIG. 2 shows the waveforms of the respective signals 2 to 6 that make up the video signal handled by this device. The horizontal standard is
A horizontal sync pulse width 110 indicating a blanking period of the horizontal scanning line,
A horizontal back porch 111 showing a left black frame of the screen, a horizontal data display period 112 showing a display period of an image, a horizontal front porch 113 showing a black frame on the right side of the screen, and a horizontal scanning period T _H showing a period of a horizontal synchronizing signal. . The vertical standard is a vertical sync pulse width of 1 indicating the blanking period of a vertical scanning line.
15, a vertical back porch 116 showing the upper black frame of the screen,
It is represented by a vertical data display period 117 indicating an image display period, a vertical front porch 118 indicating a lower black frame of the screen, and a vertical scanning period 119 indicating a period of a vertical synchronizing signal. These standards are not unified, and differ depending on the model.

FIG. 3 shows the configuration of the PLL circuit 34. In this embodiment, the PLL circuit 34 can be operated in a wide frequency range.
Three voltage controlled oscillators (VC
O) 132 to 134 are provided, and any one of them can be selected by the selector 135 by the selector signal 49. This selected output is taken out as the divided clock 51, divided by the divider 136, and the PLL horizontal synchronizing signal 52 is obtained.
Becomes This division ratio is set by the horizontal division value 48. Then, the input horizontal synchronizing signal 31 and PLL horizontal synchronizing signal 52 are compared by the phase comparator 130, the phase difference is integrated by the low pass filter 131, and the oscillation frequency of the voltage controlled oscillator is variably controlled. By this feedback control, the input horizontal synchronizing signal 31 and the PLL horizontal synchronizing signal 52 operate so as to be synchronized.

FIG. 4 shows the configuration of the sequence generation circuit 45. It stores horizontal and vertical memory addresses for storing image data in the image memory, R, G, B memory addresses, and A / D conversion. It has a function of generating a sampling clock and measuring the horizontal scanning period and the number of horizontal scanning lines of the video signal, which is a feature of the present invention. FIG. 5 is a time chart showing the operation of the sequence generation circuit 45. The operation will be described below with reference to FIGS. 4 and 5.

First, the counters 142 and 148 are reset while the PLL horizontal synchronizing signal 52 is at H level, and the output signals 143 and 149 are zero. A horizontal blank prime number setting value 75 and a horizontal pixel number setting value 74 are input to the comparators 144 and 150 from the mechanism control circuit 65, and the output signals 14 of the comparators 144 and 150 are input.
5, 151 becomes a mismatch signal and opens the gate 140,
The gate 146 is closed. PLL horizontal sync signal 52
When L becomes L level, both the counters 142 and 148 are in the counting state, but since the gate 140 is opened as described above, the divided clock 51 is counted by the counter 142, and the count value is the horizontal blank pixel number setting value. 7
5, the output signal 145 of the comparator 144 becomes a coincidence signal, the gate 140 is closed, and the counter 1
42 stops counting. At the same time, the gate 146 is opened by the coincidence signal of the comparator 144, and the counter 148 starts counting with the divided clock 51. If the output signal 149 matches the horizontal pixel number setting value 74, the output signal 151 of the comparator 150 becomes a match signal, and the gate 1
46 is closed and the counter 148 stops counting. Here, the output signal 36 of the gate 146 is a signal that outputs the divided clock 51 as it is during the period other than the horizontal blank period, which is the sampling clock 3 for A / D conversion.
6 and the memory write signal 42. The output signal 149 of the counter 148 is output as a horizontal memory address signal in the memory address signal 41.

Next, the operation of counting memory addresses in the vertical direction will be described. The vertical blank pixel number set value 77 and the vertical pixel number set value 76 are input to the comparators 159 and 165 from the mechanism control circuit 65, and the vertical blank pixel number set value 77 and the vertical blank pixel number set value 77 are input in the same manner as the above horizontal address counting.
After counting the number of PLL horizontal synchronization signal pulses equal to the number of times by the counter 157, the number of PLL horizontal synchronization signal pulses equal to the vertical pixel number setting value 76 is counted by the counter 16
Count at 3. Thus, the output signal 164 of the counter 163 is output as the vertical memory address signal of the memory address signals 41.

Next, the counting operation of the R, G and B memory addresses will be described. The mechanism control circuit 6 is provided in the comparator 176.
5, the RGB count value 40 is set. While the gate control signal 37 which is the output of the gate 170 is at the H level as shown in FIG. 5, the image select signal 35 which is the output of the counter 174 is zero. Input command switch 4
When the video input start signal 78 from 4 is input to the gate 170, the gate control signal 37 becomes L level in synchronization with the input vertical synchronizing signal 32. As a result, the gate 172 is opened, and the input vertical synchronizing signal 32 starts counting by the counter 174. The output signal 35 of the counter 174 is RGB
If the count value 40 matches, the output signal of the comparator 176 becomes a match signal, the gates 170 and 172 are both closed, and the gate control signal 37 becomes H level. While the control signal 37 is at the H level, the bus interface 16
7 is closed, and the output of the memory write signal 42 and the memory address signal 41 to the bus 59 is stopped. Further, since the control signal 37 becomes H level, the counter 174
Are reset, the output signal of the comparator 176 becomes a mismatch signal, and the state returns to the initial state.

Next, the operation of measuring the number of horizontal scanning lines V _L and the horizontal scanning period count value N _H , which are the functions added in the present invention, will be described. The counter 120 is reset to zero when the input vertical synchronizing signal 32 is at the H level, and the input horizontal synchronizing signal 31 is counted when the input vertical synchronizing signal 32 changes from the H level to the L level. When the vertical synchronizing signal 32 rises from the L level to the H level, the count value 121 of the counter 120 is latched by the latch 122, and this value gives the horizontal scanning line number VL. On the other hand, when the horizontal synchronizing signal 31 is at H level, the counter 126 is reset to zero, and when it becomes L level, the oscillator 12
The output pulse 125 of the cycle TC of 4 is counted. The latch 128 outputs the count value 127 of the counter 126 when the horizontal synchronizing signal 31 rises from the L level to the H level.
28, which is the horizontal scanning cycle count value NH
give. Signals 273 and 274 in FIG. 5 indicate the operations of the horizontal counter 126 and the vertical counter 120, and both count in the shaded portions. The horizontal scanning line number VL and the horizontal scanning period count value NH thus measured are input to the mechanism control circuit 65 via the bus interface 178. The counter 14
8 and 163, the horizontal initial value 152 and the vertical initial value 163 can be set as the initial values.

The configuration of the video signal, the PLL circuit 34, and the sequence generation circuit 45 have been described above with respect to the video input interface 20. Next, the interface 20 will be described.
The operation of will be described. First, the synchronization signal selection switch 4 of FIG.
6 by the sync selector 30 composite composite signal 2
8 or 29 or one of the separate sync signals 57 and 58 is selected, the horizontal sync signal 31 and the vertical sync signal 32 are input to the sequence generation circuit 45, and the horizontal sync signal 31 is input to the PLL circuit 34. Here, in the case of a composite video signal, it is assumed that the G image signal 55 includes a sync signal, which is separated by the sync separation circuit 27 and input to the selector 30 as composite sync signals 28 and 29. Next, the input switch 44 is used to start the input start signal 7
8 is generated, and the sequence generation circuit 45 is instructed to input the video signal. The selection of the synchronization signal and the input start signal 78 can also be instructed from the computers 17 and 101 via the digital input interface 38. The sequence generation circuit 45 generates the image select signal 35 as described above, and the image selector 21 first selects and outputs the R image signal 56 according to the value of the signal 35. This output is digitalized by the A / D converter 23 by the sampling clock 36 from the sequence generation circuit 45, and further output from the bus interface 25 as image data 26 to the bus 59 by the gate control signal 37. Similarly, G and B image signals are sequentially selected by the selector 21, digitized, and output to the bus 59. The sequence generation circuit 45 creates the sampling clock 36 from the divided clock 51 and outputs the sampling clock 3
Each time 6 is generated, the memory address signal 41 and the memory write signal 42 for storing the image data 26 in the image memory 60 are generated as described above, whereby R,
The G and B image signals are stored in the image memory 60. The video signal is input in this way, but in the above description, the pixel number setting values 74 to 77 in FIG. 4, the select signal 49 in FIG. 3, the frequency division ratio of the frequency divider 136, etc. are given. I decided. However, since these change depending on the specifications of the video signal, it is necessary to reset the specifications each time the specifications change. In the present embodiment, this is set as follows.

FIG. 6 is a flow chart showing a process for making the above setting, and this process is executed by the mechanism control circuit 65. When the input start command 78 is input (step 201), it is determined whether or not the input condition is already stored in the memory in the mechanism control circuit 65 (step 202). The test video signal generated by the computer 17 or 101, which is a generation device, is displayed on the display. An example of this test video signal is shown in FIG. 7, where the horizontal back porch 111 and horizontal front porch 113 are at black level 1.
81, the horizontal data display period 112 is all white level 1
80 signals. The state of the image data when the test video signal is A / D converted and loaded into the image memory 60 is that the white level data area 186 is divided into the black level data area 185 as shown in FIG. .
MVBn in the figure is the number of vertical pixel blanks in the memory, M
Vn represents the number of memory vertical pixels, MHBn represents the number of memory horizontal blank pixels, and MHn represents the number of memory horizontal pixels. Next, the selector 2 is used to capture this test video signal.
1, 30 are set, the cycle TH of the horizontal synchronizing signal is measured by the sequence generating circuit 45 described with reference to FIG. 4, and stored in the memory (step 204). In this step, since the output pulse of the oscillator 124 included in one cycle of the horizontal synchronizing signal 31 of the input test video signal is counted by the counter 126 to be N _H , the pulse output cycle of the oscillator 124 is T 1.
When _C (constant known) it is possible to obtain the T _H with _{T H = T C · N H} . In the next step 205, the horizontal scanning line number VL counted by the counter 120 of the sequence generation circuit 45 is stored in the memory. The number of horizontal scanning lines V _L
Since it is necessary to increase the basic frequency f of the voltage-controlled oscillator of the PLL circuit 34 as the value of V is larger, the value of the basic frequency f to be set for V _{L is} set in advance as shown in FIG. Signal 49 is defined to select the oscillator with the closest fundamental frequency in step 206. For example, if VL = 1050 to 1080, the fundamental frequency is 110M.
Hz, VL = 790-850, the fundamental frequency is 64M
The signal 49 for selecting the Hz oscillator is determined, stored in the memory, and output. In the next step 207, a temporary horizontal frequency division value n = TH × f is calculated, stored as the horizontal frequency division value 48 of the frequency divider 136 of the PLL circuit, and output. In step 208, the number of horizontal pixels Hn = VL + 256 is obtained, and this number of horizontal pixels is set as a provisional horizontal pixel number set value 74. In step 209, the number of vertical pixels Vn = the number of horizontal scanning lines VL is obtained, and this vertical pixel is set. The number is set as a provisional vertical pixel number setting value 76. Here, Hn and Vn used in step 208
The relationship of _VL is predetermined as shown in FIG.
It is stored in the mechanism control circuit 65 together with the relationship of FIG.
The relationship shown in FIG. 10 may be Hn = _VL . Next, in step 210, the horizontal blank pixel number setting value 75 of the comparator 144 of FIG. 4 is set to 0, and in step 211, the vertical blank pixel number setting value 77 of the comparator 159 is set to 0. With the above, the PLL circuit 34 and the sequence generation circuit 45
Since various tentative settings of R are performed, the RGB count value 40 of the comparator 176 is set to 1 in step 212 and R
The input operation of the image signal is executed, and the R image data of the test video signal is loaded into the image memory 60. During this capture, the set values 75 and 77 for the number of horizontal and vertical blank pixels are set to 0.
Therefore, the entire data of FIG. 8 is loaded into the memory 60 as R image data. Therefore, the next step 2
In step 13, the R image data in the image memory is checked, and the number of horizontal blank pixels MHBn and the number of horizontal pixels MHn are obtained by counting the number of pixels in the horizontal direction at the white level and the black level and stored. Further, in step 214, similarly, the number of vertical blank pixels MVBn and the number of vertical pixels MVn are obtained and stored in the memory. Further, the vertical blank pixel number VBn and the vertical pixel number Vn are respectively equal to the above-mentioned MVBn and MVn obtained from the R image data of FIG. Set as. The vertical pixel number Vn is Vn = VL-MVB
It may be obtained by n. In the next step 215, the horizontal pixel number Hn = Vn + 256 is obtained from the vertical pixel number Vn obtained in step 214 and the relationship shown in FIG. 10, and is stored in the memory and set as the horizontal pixel number set value 74 of the comparator 150. . In step 216, the MH obtained in step 213
The frequency divider 1 calculates N = Hn × n / MHn from n, n obtained in step 207, and Hn obtained in step 208.
It is set as a horizontal frequency division value 48 of 36 and stored in the memory. In addition, this frequency division value N is calculated as HBn in step 217.
It may be + Hn. In step 217, the number of horizontal blank pixels HBn = Hn × MHBn / MHn from Hn, MHBn, and MHn obtained in steps 208 and 213.
Is set as a horizontal blank pixel number setting value 75 and stored in the memory. This completes the setting of each set value. If each set value is stored in step 202, these values are stored in step 218, that is, the fundamental frequency f of the oscillator, the frequency division value N, the horizontal blank pixel number HBn, the horizontal pixel number Hn, and the vertical blank pixel number. VBn,
The vertical pixel number Vn is set in the PLL circuit 34 and the sequence generation circuit 45. In this way, the image to be printed is displayed on the display in step 219, and the input start command 78 is issued in step 220, and the respective image data of R, G, B are taken into the image memory 60 as described above.

As described above, according to this embodiment, various setting values according to the specifications of the input video signal can be automatically determined, so that the input operation can be performed easily and in a short time. There is an effect that video signals of different standards displayed on a plurality of displays can be switched and input by a multiplexer. Moreover, there is no need to print at the time of setting the input conditions, so printing costs are not required.

Next, the operation of the video input interface 20 when a test video signal different from that shown in FIG. 8 is used will be described. FIGS. 11 and 12 show different test video signal configurations, and FIGS. 13 and 14 show the state of the image data when these are loaded into the image memory 60. The test video signal of FIG. 11 is a signal which has a white level 180 of the highest brightness on the entire display screen and displays vertical parallel lines of a black level 181 in a range narrower than the display screen. However, in the portion close to the vertical synchronizing pulse, the entire horizontal display period 112 is the white level 180 of the highest brightness, and in the middle portion, the horizontal display period 112 is almost the white level 180 and two black levels 181 are inserted therein. There is. A predetermined number of pixels may be provided between the two black levels 181. As shown in FIG. 13, the state of the image data when the test video signal is A / D converted and taken into the image memory 60 is shown in FIG. Will be inserted.
For this image data, the memory vertical blank pixel number MVBn, the memory vertical pixel number MVn, the memory horizontal blank pixel number MHBn, and the memory horizontal pixel number MHn are determined in the same manner as in FIG. 8, and in addition to this, the memory vertical test pixel number MVTn.
(Number of pixels in vertical line) and memory horizontal test pixel number MH
Tn (the number of horizontal pixels between two vertical lines) is determined.

The test image signal of FIG. 12 is the signal of FIG. 11 in which the two black levels 181 during one horizontal display period are all black levels 181. As shown in FIG. 14, the state of the image data when captured in 60 is an area 332 in which the space between two vertical lines of the black level in FIG. 13 is filled with the black level.
Will have. With respect to this test signal, the memory vertical test pixel number MVTn and the memory horizontal test pixel number MHTn can be defined in exactly the same manner as in FIG.

The input condition setting when the test video signal of FIG. 11 or 12 is used is executed by changing the following points in the flowchart of FIG. First, in step 213, from the R image data in the image memory, the mechanism control circuit 65 measures and stores the horizontal test pixel number MHTn in addition to the horizontal blank pixel number MHBn and the horizontal pixel number MHn. Similarly, in step 214, R in the image memory is
In addition to the vertical blank pixel number MVBn and the vertical pixel number MVn from the image data, the vertical test pixel number MVTn is also measured and stored in the memory. The vertical blank pixel number setting value 77 and the vertical pixel number setting value 76 are the same as those in FIG. Step two
At 15, the number of horizontal pixels is calculated by the calculation of Hn = MHn × MVTn / MHTn and stored in the memory. Also this Hn
Is set as the horizontal pixel number setting value 74. If the black level image in the image data is composed of a predetermined number A of horizontal pixels, the number of horizontal pixels can be calculated from the measured number of horizontal pixels MHTn by Hn = MHn × A / MHTn.

As described above, the test video signal of FIG. 11 or FIG. 12 is a signal for displaying the maximum number of pixels and is not only a signal capable of distinguishing image data from non-image data, but also the number of pixels in the horizontal direction is known. Since there are two black level lines or black level areas, the number of pixels in the vertical and horizontal directions of image data and the number of pixels in the vertical and horizontal directions of non-image data can be easily calculated.

Next, the printing operation in this embodiment will be described. FIG. 15 shows a data format in which the image data 281 captured in the storage surface 280 of the image memory 60 is transferred to the thermal head and printed on the recording paper 294. The horizontal direction of the storage surface 280 is the horizontal direction and the vertical direction is the vertical direction. The direction is called the vertical direction, the horizontal direction of the recording paper 294 is called the main scanning direction, and the vertical direction is called the sub-scanning direction. Memory surface 28
0 has a size of (total number of horizontal pixels of memory 282) × (total number of vertical pixels of memory 284), and image data 281 has a size of (horizontal pixel number Hn) × (vertical pixel number Vn).
Further, the line memory 286 for fetching the data of the storage surface 280 for one line and transferring it to the register 292 of the thermal head has a length of the line memory total pixel number Hmax, the number of blank pixel Hsp1, the horizontal offset value Hoff,
The horizontal pixel number Hn and the blank pixel number Hsp2.
The data in the register 292 of the thermal head is composed of the number of horizontal blank pixels Hw = (Hmax-Hn) / 2 + Hoff, the number of horizontal pixels Hn, and the number of blank pixels Hsp2. The recording paper 294 has a length Lmax in the vertical direction, and there is a blank line number Vw between it and the printing area 293. The number of vertical pixels in the printing area is Vn. The number of blank lines Vw is Vw =
Voff is represented by (Lmax-Vn) / 2 + Voff.
Is a line offset value (constant).

FIG. 16 is a flow chart showing the printing operation, and this processing is executed by the mechanism control circuit 65. First, when the print start command is confirmed in step 231, the horizontal offset value Hoff is input and stored in the memory in step 232, and the print position of the image is moved in the main scanning direction by this amount. In step 233, the line offset value Voff is input and stored in the memory, and the image print position is moved in the sub-scanning direction by this amount. Next, in step 234, the number of horizontal blank pixels in the main scanning direction Hw = (Hm
ax−Hn) / 2 + Hoff is calculated, and step 235 is performed.
And the number of blank lines in the sub-scanning direction Vw = (Lmax-Vn)
/ 2 + Voff is calculated and both are stored in the memory. Next, at step 236, the recording paper is supplied and wound around the drum. The preparation is completed here, and the printing operation for each color is started. First, in step 237, Y ink is set at the printing position, and in step 238, the thermal head is pressed against the ink paper, and the recording paper is fed by the Vw line without heating the thermal head (upper margin). In step 239, the data for one line (Hn pieces) of the B image data is converted into Y = (inversion of the logical operation B) and transferred to the line memory, and in step 240, HW white data are added to the data rear part of the line memory. Is added (the right end margin), and in step 241, the data in the line memory is transferred to the head and recorded on the recording paper. The above steps 239 to 241 are executed line by line and printed, and when the Vn lines are completed, step 2
If the confirmation is made at 42, the printing of the B image data is completed, and the process moves to the printing of the next G image data. This is step 24
3 to 248, and then the printing of the R image data is executed in steps 249 to 254. These G,
In the case of the R image, the operation is exactly the same as that of the B image data, and only the colors handled are different. When printing of three colors is completed, the thermal head is separated from the ink paper in step 255 (see FIG.
Driving of the mode motor 81), the recording paper is discharged, and the processing is ended. As described above, since the horizontal pixel number Hn and the vertical pixel number Vn when the video signal is captured in the image memory are stored, if the recording paper size and the printing position are specified, the image offset value is calculated. Therefore, the image can be recorded at an arbitrary position.

FIG. 17 shows another example of the printing operation. Image data 28 is stored in the storage surface 280 of the image memory 60.
This is a case where the storage position of 1 is determined according to the printing position. The size of the storage surface 280 and the size of the image data 281 are indicated by the same symbols as in FIG.
The image data 281 is arranged with the number of horizontal margin pixels 311, 312 and the number of vertical margin pixels 313, 315.
Then, white data is stored in advance in the storage surface 280. The total number of pixels Hmax of the line memory 286 and the shift register 292 of the thermal head is the same as the total number of horizontal pixels 282 of the image memory, and one line of data on the storage surface 280 can be taken in. The printing area 293 of the recording paper 294 corresponds to the entire storage surface 280, and the image data 281 is printed in the printing area 293 at the same position as the storage surface 280. In this way, the horizontal memory address counter 14 of the sequence generation circuit 45 is
8 and the vertical memory address counter 163 are preset with offset values 152 and 153 (corresponding to the margins 311 and 313 in FIG. 17, respectively) to store the video signal in the storage surface 280 of the image memory. The print position can be specified by. Then, the entire storage surface 280 may be printed on the entire printing area.

FIG. 18 shows another input method of the present invention, which is the specification of the video signal described in FIG. 2, that is, RG.
Distinction between B separate video signal and RGB composite video signal, horizontal sync pulse width, horizontal back porch, horizontal display period, horizontal front porch, horizontal sync cycle, sampling clock frequency, number of horizontal pixels, vertical sync pulse width, vertical back porch , Vertical data display period, vertical front porch, vertical scanning period, vertical pixel number, etc.
It is stored in advance in the ROM 336 in the display or the computer 335 (the display 1 or 104 or the computers 17 and 101 in FIG. 1) that constitutes the image forming apparatus, and the mechanism control circuit 65 outputs the address signal 337 and outputs it from the bus 59. To the ROM 336, and the video signal specifications 338 are input to the interface 339 and the bus 59.
The video signal is input to the mechanism control circuit 65 via the device, the input condition is obtained from this specification, various settings are made, and the video signal is input to the image memory. In this case, of course, the measuring circuits for V _L and N _{H in} FIG. 4 are unnecessary. According to this embodiment, since the input condition of the video signal can be known from the display or the computer, the circuit configuration becomes simple. Further, there is no need to input the test video signal to obtain the input condition, so that the input can be performed accurately and in a short time.

FIG. 19 shows another input method of the present invention, in which a test video signal output from a computer can be output according to a command from a printer. When the command signal 354 for the test is input from the mechanism control circuit 65 via the interface 355, the video signal generation circuit 353 in the computer 345 of the image forming apparatus inputs the contents of the test video memory 349, and the D / A It is converted and output as a video signal 352. By this, the image specification can be measured, calculated, and the input condition to the interface circuit 20 can be set, and then the video signal generated from the video memory 346 is output. According to this embodiment, the target video signal and the test video signal can be switched and output by the command from the mechanism control circuit 65.
There is an effect that the setting of the input condition of the video signal can be automated.

In each of the above embodiments, the thermal transfer color printer is targeted, but the present invention can be applied to a thermal transfer monochrome printer, a thermal printer, a laser printer, a silver salt photographic printer, an ink jet printer, a wire dot printer and the like. Applicable. In addition, the video signals are of the RGB composite system and the RGB separate system.
It is obvious that the C method, SECAM method, PAL method, or the like may be used.

[0031]

According to the present invention, since the input condition setting value when a video signal is input from the video input interface can be automatically obtained, it is not necessary to repeat test printing and adjustment for setting. Both cost and time can be saved significantly, and video signals of different standards from multiple displays can be switched easily by a multiplexer, and can be input easily. Furthermore, printing at specified positions on recording paper is easy. The effect is that it can be done.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of an apparatus of the present invention.

FIG. 2 is a configuration diagram of a video signal.

FIG. 3 is a diagram showing a configuration example of a PLL circuit.

FIG. 4 is a diagram showing a configuration example of a sequence generation circuit.

FIG. 5 is a timing chart showing the operation of the sequence generation circuit.

FIG. 6 is a flowchart of a video signal input process.

FIG. 7 is a diagram showing an example of a test video signal.

8 is a diagram showing a state of image data in an image memory when the signal of FIG. 7 is input.

FIG. 9 is a diagram showing the relationship between the number of horizontal scanning lines and the frequency f of the voltage controlled oscillator.

FIG. 10 is a diagram showing a relationship between the number of vertical pixels and the number of horizontal pixels.

FIG. 11 is a diagram showing another example of a test video signal.

FIG. 12 is a diagram showing another example of a test video signal.

13 is a diagram showing a state of the image memory when the test video signal of FIG. 11 is input.

14 is a diagram showing a state of the image memory when the test video signal of FIG. 12 is input.

FIG. 15 is a diagram showing an example of the relationship between image data and print positions.

FIG. 16 is a print operation flowchart.

FIG. 17 is a diagram showing an example of the relationship between image data and print positions.

FIG. 18 is a configuration diagram when a video signal specification is read from a ROM.

FIG. 19 is a configuration diagram when a test video signal is read by a command from a printer.

[Explanation of symbols]

17 Computer 18 Thermal transfer color printer 20 video input interface 21 Image signal selector 27 Sync separation circuit 30 Sync signal selector 31 Horizontal sync signal 32 Vertical sync signal 34 PLL circuit 38 Digital Input Interface 45 Sequence generation circuit 60 image memory 61 Halftone control circuit 62 Display / operation switch 65 Mechanism control circuit 66 power 80 Recording mechanism

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number for FI Technical location H04N 9/79 H 9185-5C (72) Inventor Katsumi Watanabe 502 Kandachi-cho, Tsuchiura-shi, Ibaraki Co., Ltd. (72) Inventor Hiroshi Nakamura 1014 Inada, Katsuta City, Ibaraki Hitachi Ltd. Tokai Plant, Hitachi Ltd.

Claims (10)

[Claims] 1. An image memory, input interface means for capturing the input video signal in a state where input conditions corresponding to the specifications of the input video signal are set, digitizing the input video signal, and storing it as image data in the image memory, and a recording mechanism. Section, halftone control means for converting image data stored in the image memory or image data digitally input from the outside into an input signal to the recording mechanism section, and the input interface of the input information. A video input hard copy device having a mechanism control means having a function of setting to the means and an operation control function of the recording mechanism section. 2. An image memory, an input interface means for capturing the input video signal in a state where input conditions corresponding to the specifications of the input video signal are set, digitizing the input video signal, and storing it as image data in the image memory, and a recording mechanism. Section, halftone control means for converting image data stored in the image memory or image data digitally input from the outside into an input signal to the recording mechanism section, and the input interface of the input information. In a video input hardcopy device having a mechanism control means having a function of setting to the means and an operation control function of the recording mechanism part, the interface means is provided with a signal created by an image creating means for creating an input video signal. Therefore, the display area and the non-display area of the image created by the image creating means can be distinguished. A scanning line number measuring means for measuring the number of horizontal scanning lines of the test signal when the test signal created as described above is input is provided, and the mechanism control means is configured to perform the test measured by the scanning line number measuring means. By using the number of horizontal scanning lines of the signal, the input condition when all the image data of the display area and the non-display area of the test signal is determined to be the display area is set in the input interface means, and in the set state The test signal is input to the image memory by the input interface means, and then the image data of the test signal input to the image memory is examined to detect the sizes of the display area and the non-display area, and the detection is performed. The input condition for the image creating means is obtained from the size and set in the input interface means. Video input hard copy apparatus characterized by controlling so as to capture the image data to the image memory. 3. An image memory, an input interface means for capturing the input video signal in a state where input conditions corresponding to the specifications of the input video signal are set, digitizing the input video signal, and storing it as image data in the image memory, and a recording mechanism. Section, halftone control means for converting image data stored in the image memory or image data digitally input from the outside into an input signal to the recording mechanism section, and the input interface of the input information. In a video input hardcopy device including a mechanism control unit having a function of setting the recording unit and controlling the operation of the recording mechanism unit, the specification of the video signal generated by the image generation device that generates the input video signal is specified. A specification storing means for storing the stored specifications is provided, and the mechanism controlling means first sets the above specifications when the video signal is taken in. It is characterized in that the input condition is read out from the storage means, the input condition is set in the input interface means, and the image data created by the image creating apparatus is controlled so as to be fetched into the image memory. Video input hard copy device. 4. The display area of the test signal is white,
The non-display area is black image data, and the mechanism control means sets the number of vertical pixels and the number of vertical blank pixels in the input condition to the number of pixels in the vertical direction of the white display area and the black non-display area. Assuming that they are equal to each other, the number of horizontal pixels is a value calculated from the number of vertical pixels by a predetermined relationship, and the number of horizontal blank pixels is the ratio of the number of horizontal pixels of the white display area to the calculated number of horizontal pixels of the black pixel. 3. The video input hardcopy device according to claim 2, wherein the value is calculated as a value obtained by multiplying the number of horizontal pixels in the non-display area. 5. The test signal includes only a quadrilateral black area having a black non-display area, a white display area and a side parallel to a side of the display area, or two vertical lines of the quadrangle. Image data having black test data, wherein the mechanism control means sets the number of vertical pixels and the number of vertical blank pixels in the input condition to the number of pixels in the vertical direction of the white display area and the black non-display area. And the horizontal pixel count is a value obtained by multiplying the horizontal pixel count of the display area by the ratio of the vertical pixel count and the horizontal pixel count of the test data, and the horizontal blank pixel count is calculated as the horizontal pixel count. The video input hardware code according to claim 2, wherein a ratio of the number of horizontal pixels of the white display area to the number of pixels is calculated as a value obtained by multiplying the number of horizontal pixels of the black non-display area. Pea device. 6. The image creating apparatus creates the test signal in advance and stores the test signal in its own apparatus, and the mechanism control means,
6. A test signal stored in the image forming apparatus is fetched prior to inputting a video signal to obtain an input condition, and the condition is set in the input interface. Video input hardcopy device according to claim 1. 7. The input interface means selects a plurality of voltage controlled oscillators having different fundamental frequencies from each other and outputs one of the voltage controlled oscillators as a divided clock having a frequency equal to the sampling frequency of a pixel. A selector, a frequency divider that divides the selector output to produce a horizontal synchronizing signal output, a phase comparator that compares the frequency of the divider output with the horizontal synchronizing signal of the input video signal, and the phase comparator The low frequency component of the output of the comparator is taken out and the phase synchronizing means including the low pass filter for outputting the control voltage of the oscillation frequency of the voltage controlled oscillator is provided, and the horizontal scanning cycle of the test signal is measured in the input interface means. A horizontal period measuring means is provided, and the mechanism controlling means uses the predetermined relationship to determine the horizontal period measured by the scanning line number measuring means. One of the voltage-controlled oscillators is selected from the number of scanning lines, and the product of the basic frequency of the selected voltage-controlled oscillator and the horizontal period measured by the horizontal period measuring means is set to the division period as a provisional division value. Then, the input interface means is caused to fetch the test signal into the image memory, and at the time of fetching the image data, a value obtained by multiplying the provisional frequency division value by the ratio used for calculation of the number of horizontal blank pixels is used. 6. The video input hardcopy device according to claim 4, wherein the division ratio is set as a division ratio of the frequency divider. 8. An input selector for selecting one of the video signals output from a plurality of image forming means and inputting it to the input interface means is added. A video input hardcopy device according to any one of 6 or 7. 9. The mechanism control means, when an output position of an input video signal on a recording paper and an output command are given,
Transferring the video signal captured in the image memory to a buffer in the recording mechanism so as to match the given output position, and controlling the signal in the buffer to be output on the recording paper at the same position. Claim 2 or 3 or 4 or 5 or 6 or 7 or 8
A video input hardcopy device according to one of: 10. The mechanism control means, when an output position of an input video signal on a recording paper and an output command are given, so that the input video signal matches the given output position of the image memory. One of claims 2 or 3 or 4 or 5 or 6 or 7 or 8, wherein the recording mechanism is controlled so that the recording mechanism takes in the recording surface and outputs it on the recording paper in the same positional relationship. Video input hardcopy device described in.