JPH05275813A - Manufacture of crystal improved compound semiconductor device - Google Patents

Abstract

PURPOSE:To improve crystal property and obtain good flatness of interface by execut ing thermal treatment, under the reducing atmosphere including hydrogen, to a semicon ductor device comprising a semiconductor film which has been formed by growth of a compound semiconductor including at least III group and V group by the vacuum deposition under the substrate temperature preset to a constant value or less. CONSTITUTION:High quality crystal growth can be obtained through the growth by keeping the number of flying molecules ratio of V group and III group to 2.5 or less (preferably, 2 or less) in the first process where a film is formed by the method, for example, represented by MBE(melecular beam epitaxial growth method) under the vacuum condition keeping a substrate temperature to 500 deg.C or lower. During this crystal growth, a diameter of island having a step difference of one atom layer becomes small and effectively flat interface can be formed for exciton within the quantum well or for carrier in the proximity to the interface. Thereafter, when temperature is increased exceeding the substrate temperature during the growth under the reducing atmosphere, crystal defect due to a low temperature growth can be recovered. Moreover, defect in the crystal can be reduced by feeding a current to a semiconductor film which has grown under a low temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a steep and flat compound semiconductor hetero-interface, particularly a quantum well structure composed of two flat compound semiconductor hetero-interfaces, a substrate or a laminated formation on the substrate. A semiconductor device including layers such as GaAs, AlGaAs, Si, and ZnSe in the formed crystal laminated film at a substrate temperature (crystal growth temperature) of 500 ° C. or lower; The present invention relates to a method of manufacturing a compound semiconductor device having an improved crystal.

[0002]

2. Description of the Related Art Conventionally, a molecular beam epitaxial growth method (M
BE: Molecular Beam Epitaxy)
Group V compound semiconductors (eg, GaAs and AlGaA)
In producing the heterojunction of (s), a group III (eg, A
l) It is widely known that an interface having a steep composition profile in the direction perpendicular to the substrate surface can be easily formed by controlling the supply of molecules.

MB of this type of III-V compound semiconductor
Crystal growth by the E method is generally two-dimensional or three-dimensional growth from a growth nucleus, and a hetero interface is formed at an arbitrary timing by opening and closing a shutter that controls the supply of group III molecules. At this heterointerface, there is at least one atomic layer step in a plane parallel to the substrate plane. As is well known, the existence of the step is AlGaAs / Ga
A plurality of peaks appear in photoluminescence from the quantum well structure of As and the quantum well structure of GaAs / AlAs, and the energy interval of these peaks makes the thickness of the quantum well 1
It is known to be the same as the difference in the binding energy in the quantum well when only the atomic layer is changed. For example, Jpn. J.
Appl. Phys. 24, l417 (1985) reported that the interface becomes flat due to the temporary interruption of crystal growth at the hetero interface.

In addition, MEE (Migration Enhanced Epitax)
Crystal growth by the y) method is also known. For example, Jpn. J.
Appl. Phys. 25, 868 (1986) has reported that a crystal excellent in crystallinity and interface flatness can be obtained by the MEE method in which Ga and As are alternately grown one atomic layer at a time.

The following techniques are also known. First of all, the molecular beam epitaxy growth method (MB
It is known that the threshold current density of the semiconductor laser manufactured by E) increases when the crystal growth temperature (substrate temperature) is relatively low (for example, Appl.Phys.Lett.V).
ol.36, p118, 1980, WTTsang et al.). An example of the above semiconductor laser is shown in FIG.

In FIG. 13, 201 is a substrate, n-.
GaAs, 202 is a buffer layer of 0.5 μm thick S
i-doped GaAs layer, 203 is a Si-doped Al _0.3 Ga _0.7 As layer having a thickness of 1.5 μm, 204 is an active layer made of undoped GaAs having a thickness of 0.1 μm, and 205 is a Be-doped Al _0.3 Ga _0.7 As layer having a thickness of 1.5 μm. , 206 is 0.5μ
Be-doped GaAs layer which is a contact layer of m thickness, 20
7 is a Cr / Au alloy electrode deposited on the contact layer 206, and 208 is AuGe / Ni / A deposited on the back surface of the substrate 201 after thinning the substrate 201 to about 100 μm.
u electrode. As shown in FIG. 14, in the semiconductor laser having the above laminated structure, the threshold current density J _th (kA / cm ² ) depends on the substrate temperature (° C). For example, stripe width 10
In the case of a laser having a cavity length of 0 μm and a cavity length of 300 μm, the threshold current density J _th decreases near the substrate temperature of 650 ° C., that is, the characteristics of the laser are improved. On the other hand, the substrate temperature is 30
In the vicinity of 0 ° C, the threshold current density J _th rises to 14 kA / cm ² or more, and the limit value usable as a semiconductor laser is about 3 kA.
Far exceeds / cm ² . That is, it can be seen that the characteristics of the laser deteriorate in the low temperature region.

By the way, in recent years, an integrated circuit (OEIC) of an optical device and an electric / electronic device has been attracting attention as an important technique for realizing improvement of reliability, reduction of manufacturing cost, miniaturization and the like (for example, J. Vac.Sci.Technol.B2
(2), 259,1984; Very low threshold current GaAs-AlGaA
s GRIN-SCH lasers grown by MBE for OEIC applicatio
ns). The production of this OEIC has a problem due to the difference in crystal growth temperature (substrate temperature) between the optical device and the electric / electronic device. For example, if the substrate temperature is higher than the appropriate temperature, mutual diffusion of constituent elements and impurities of the electronic device occurs, and it is difficult to produce an ideal doping profile (distribution) or an ideal structure. Specifically, optical devices are typically fabricated at 600 ° C and above (700 ° C today).
It is produced even at about C), but it is 500 ° for electronic devices.
Since it is manufactured around C, when manufacturing OEIC,
The difference in the proper substrate temperature between the optical device and the electronic device is 20.
There was a problem of reaching 0 ° C. Therefore, the electronic device must be manufactured after the optical device is manufactured,
When performing a plurality of epitaxial growths having different structures, it has been a great obstacle to the smooth progress of the manufacturing process.

FIG. 15 shows the diffusion of Sn-doped GaAs as an example of epitaxial growth when integrating a plurality of devices having different structures as described above. In this diffusion example, the correlation characteristic between the diffusion layer depth and the impurity concentration when the growth temperature is already 550 ° C. (shown by a chain line 183 in the figure) shows an ideal doping shape (shown by a solid line 182 in the figure). Far away from.

As described above, low-temperature growth is a very important technique in the semiconductor process, and particularly low-temperature growth of a semiconductor laser, which is the center of an optical device, is important for integration of optical devices and electric devices. ..

Secondly, it has been hitherto attracting particular attention in relation to a heterojunction having a lattice mismatch, as follows.
Heteroepitaxial growth in which a substance different from the substrate is grown is known. For example, it is known to grow a thin film of a III-V group compound semiconductor such as GaAs on a Si substrate to form a heterojunction. Ga on Si substrate
If a thin film of As or the like can be grown, a large-area and inexpensive substrate can be obtained. Therefore, for example, fabrication of high-efficiency solar cells, realization of OEIC by monolithicization of Si and GaAs, high-speed GaAs · I on a large-area substrate
C and HEMT (High Electron Mobility Transistor)
-Opening the way for technological development such as IC fabrication, improvement of heat dissipation of power devices and semiconductor lasers (Si has a higher thermal conductivity than GaAs, so heat dissipation is promoted).

By the way, since the lattice mismatch of Si and GaAs is 4% and the coefficient of thermal expansion is different, it is difficult to produce the above-mentioned heterojunction by the conventional crystal growth method.
Therefore, a method for alleviating the above lattice mismatch has been proposed. For example, GaAs / Ge / with Ge as an intermediate layer
A two-step growth method (GaAs / GaAs) in which a structure of Si is produced, an amorphous thin GaAs is grown at a low temperature after cleaning a Si substrate at a high temperature, and then a growth temperature is raised to a normal temperature to grow GaAs. -AlGaA
s superlattice / Si structure), a method of using a strained superlattice for the intermediate layer (AlGaAs / superlattice / Si structure)
Are known. In these methods, MBE or metalorganic vapor phase epitaxy (MOCVD) is adopted as the crystal growth method, and in each case, a GaAs single crystal is obtained. Using GaAs on the Si substrate thus manufactured, a field effect transistor (FET), a solar cell,
Various devices such as semiconductor lasers have been prototyped. or,
Although the characteristics are inferior to those produced on a GaAs substrate, it is also reported that a GaAs / AlGaAs double heterojunction laser can be produced on a Si substrate and oscillated at room temperature.

FIG. 16 shows an example thereof. As shown in the figure, an atmospheric pressure MOCVD apparatus is used, and (100) 2 degrees o
An n-type Si substrate 171 of ff is used, and a GaP layer 172 is formed on the Si substrate 171 at 900 ° C. by 0.1 μm.
GaP / GaAsP strained superlattice (20nm / 20nm ×
5) 173 is formed at 750 ° C, and further GaAsP / G
An aAs strained superlattice (20 nm / 20 nm × 5) 173 is formed. On top of this superlattice (SLS) 173, n-Ga
As174 (thickness 2 μm, impurity concentration 2 × 10 ¹⁸ c
m ^-3 ), a lower cladding layer of n-Al _x Ga _1-x As1
75 (thickness 0.08 μm), undoped G that is an active layer
aAs176 (thickness 0.08 μm), p-Al _x Ga _1-x As177 (thickness 0.65 μm, which is the upper clad layer)
Impurity concentration 1.3 × 10 ¹⁸ cm ⁻³ ), p-GaAs 17
8 (thickness 0.65 μm, 1.3 × 10 ¹⁸ cm ⁻³ ) are grown in this order. AuZn / Au180 is used as an electrode on the uppermost layer (p side) of this laminated structure, and AuGe / is used on the lowermost layer (n side).
Au181 was vapor-deposited to manufacture a semiconductor laser having a stripe width of 10 μm and a cavity length of about 300 μm.

FIG. 17 shows the characteristics of the semiconductor laser manufactured as described above. In FIG. 17A, the conventional Ga is used.
FIG. 17 shows the characteristics of the laser manufactured on the As substrate.
(B) shows the characteristics of the laser produced on the Si substrate.

As can be seen from the characteristic curve shown, Ga
Double heterojunction (DH) lasers on As substrates are
It oscillates only in the mode, but in the laser on the Si substrate, TE
It oscillates in + TM mode and TM mode. This difference in oscillation mode means that Si and GaAs have different thermal expansion coefficients, so that the GaAs layer grown on the Si substrate is under stress (about 10
^It is believed that this is because the light hole level and the heavy hole level are separated by receiving ⁹ dyn / cm ² ).

As described above, although the laser on the Si substrate has excellent characteristics, the GaAs layer grown on the Si substrate has an etch pit of 1 × 10 ⁶ / cm ² and the lifetime of the laser. From the viewpoint of the above, there is a problem that the etch pit value is much larger than the desired value (1 × 10 ³ / cm ² ), and since a GaAs laser is produced by high temperature growth at 700 ° C., a large stress is generated due to a difference in thermal expansion coefficient between Si and GaAs. However, there is a problem that the laser characteristics such as TM mode oscillation are adversely affected.

As described above, the stress due to the difference in lattice constant between Si and GaAs, the stress due to the difference in thermal expansion coefficient, etc. have not been completely improved yet, and the above-mentioned problems that greatly affect the life of the laser are also solved. Without resolution, Si
It is considered difficult to put a semiconductor laser manufactured on a substrate into practical use.

Thirdly, conventionally, a technique for compounding semiconductor materials has been developed. For example, in order to develop a flat panel color display, a technique for manufacturing a light emitting device by integrating semiconductor materials corresponding to the three primary colors of light on the same substrate has been studied. As the semiconductor material, AlGaAs for red, GaP for yellow,
There is ZnSe for blue, and GaAs is generally used as the substrate.
There is.

However, AlGaAs and GaP are GaAs
And the lattice constants match, and light emitting diodes and semiconductor lasers using these semiconductor materials have been put to practical use, but devices using ZnSe have not yet been put to practical use. The technical reason is that it is difficult to dope ZnSe, and the growth temperatures of ZnSe and GaAs are very different. Generally, the optimum growth temperature is ZnS.
e is 250 ° C to 350 ° C, and GaAs is 50 ° C.
It is 0 ° C or higher. For example, good quality G on ZnSe film
When trying to grow an aAs film, Ga, As, Zn,
The mutual diffusion of Se occurs, and an n-junction and a p-junction that obstruct the current are formed at the interface between GaAs and ZnSe. Therefore, in the conventional crystal growth method, ZnSe is normally grown on a GaAs substrate at 250 ° C to 350 ° C.

18 and 19, Z is formed on a GaAs substrate.
An example of a conventional growth method for growing nSe will be shown. FIG.
, N-Zn is formed on the n-GaAs substrate 151.
Grow Se152. The growth temperature at this time is 300
Since the temperature is ° C, crystal growth proceeds smoothly. However, as shown in FIG. 18, the growth temperature is raised to 500 ° C. and n-ZnSe is increased.
When an n-GaAs 153 is grown on the 152, the ZnSe layer 152 is transformed into the n-GaAs 153.
n is diffused. As a result, a part of the GaAs 153 becomes a p-type GaAs region. Similarly, Ga diffuses from the GaAs layer 153 into the ZnSe 152 and ZnSe1
Ga diffuses into 52 and an n region is formed in ZnSe 152. That is, the GaAs substrate and the GaAs layer 15
An npn junction will be formed between 3 and the above.

As described above, when ZnSe and GaAs are grown on the GaAs substrate, ZnSe and GaAs are grown.
There is a problem that a device having diode characteristics can be formed due to a large difference in growth temperature between ZnSe and ZnSe.
This is a major obstacle to the realization of devices. Alternatively, if GaAs is grown at a low temperature without raising the growth temperature, crystal defects will increase.

In order to manufacture an efficient light emitting device, a material having a band gap different from that of ZnSe is required. As its material, GaAs with the same lattice constant
It is optimal to use the AlGaAs type or AlGaAs type. Therefore,
It is essential to develop a technique for growing GaAs or the like on the ZnSe layer at a low growth temperature. The technique is an important technique for integrating a light emitting device including a ZnSe layer, Ga, ZnSe, GaP, and the like, and generally for II-V group crystal growth having a low growth temperature.

[0022]

However, in the growth interruption method for planarizing the interface, it is necessary to interrupt the crystal growth at the same time as the supply of group III atoms for forming one atomic layer. Even if the timing is slightly deviated, the diameter of an island having a step difference of one atomic layer can be made larger than the exciton radius, but the island always remains. An example thereof is shown in FIG. 2B, which is shown in comparison with the embodiment.

Further, the MEE method for obtaining a crystal excellent in crystallinity and interface flatness has a problem that it is not suitable for mass production because the crystal growth rate is extremely slow.

Another problem is that the above-described semiconductor film grown at low temperature has relatively many crystal defects and is inferior to the film grown at a normal growth temperature.

Therefore, the present invention has an improved crystal for producing a crystal laminated film of a material different from the substrate material by low temperature growth with high quality so as to eliminate mutual diffusion and suppress stress due to a difference in thermal expansion coefficient. An object is to provide a method for manufacturing a compound semiconductor device.

It is another object of the present invention to provide a method for manufacturing a semiconductor device having excellent crystallinity and interface flatness under low temperature growth.

As the background of the present invention, first of all, low temperature growth is an important technique in the semiconductor process, and particularly, a technique for manufacturing a semiconductor laser which is the center of an optical device by low temperature growth is important. , Its technical development is a very important issue in integrating optical devices and electronic devices. Secondly, the development of a crystal improvement method for improving the stress caused by the lattice mismatch and the difference in the coefficient of thermal expansion to produce a high quality compound semiconductor on the Si substrate is also an important issue.
The crystal improvement method of the present invention is expected to realize a good-quality semiconductor laser. Thirdly, in the field of light emitting devices, development of devices using ZnSe is required, and for the production of highly efficient light emitting devices, GaAs or AlGaAs systems with matching lattice constants are optimal. Development of a technique for growing GaAs or the like on the layer by low temperature growth is required. Further, there is also a demand for manufacturing a semiconductor device including an epitaxial film having excellent crystallinity and interface flatness. The present invention solves these problems.

[0028]

The gist of the present invention for achieving the above object is, for example, formation of a compound semiconductor containing at least a group III and a group V by vacuum vapor deposition at a substrate temperature of 500 ° C. or lower. The method for producing a compound semiconductor device includes the step of heat-treating a semiconductor device including the above semiconductor film in a reducing atmosphere containing hydrogen or the like.

The gist of the present invention to achieve the above object is that the crystal laminated film formed on the substrate is formed of a plurality of materials of different groups based on the periodic table and the crystal growth temperature is 50.
A crystal improving method for a compound semiconductor device, in which a crystal laminated film is produced at 0 ° C. or lower, is a crystal improving method for improving luminous efficiency and the like by passing an electric current through the crystal laminated film.

More specifically, the compound semiconductor contains at least Group III and Group V, the reducing atmosphere is an atmosphere containing hydrogen, and the semiconductor film has a flux of the number of flying molecules of Group V and Group III. The ratio (the number of flying molecules of group V with high vapor pressure divided by the number of flying molecules of group III with low vapor pressure) is kept at 2.5 or less, or vacuum deposition is performed by molecular beam epitaxial growth method. The heat treatment atmosphere is kept at 100% hydrogen, the heat treatment temperature is in the range of 500 ° C. to 800 ° C., the heat treatment time is in the range of 10 minutes to 120 minutes, and the semiconductor film is at least The semiconductor film contains arsenic and gallium, the semiconductor film contains aluminum, and the crystal is improved by applying a current to the crystal laminated film at a temperature lower than the growth temperature. The crystal laminated film is produced with a flux ratio of the number of flying molecules of 2.5 or less, the crystal laminated film does not include an active layer, and the crystal laminated film is formed closer to the substrate than the active region.

[0031]

According to the present invention having the above-described structure, the substrate temperature during the growth of the compound semiconductor hetero interface is set to 500 ° C. or lower, and the diameter of the island having the step difference of one atomic layer is made small, so that the inside of the quantum well is reduced. An exciton or a carrier near the interface is effectively formed as a flat interface. Subsequently, a heat treatment can recover from the crystal defects caused by the low temperature growth. As a result, a semiconductor device including an epitaxial film having excellent crystallinity and interface flatness is manufactured.

Specifically, in the first step of forming a film in a vacuum at a substrate temperature of 500 ° C. or lower, for example, by a vapor deposition method represented by the MBE method, the number of flying molecules of group V and group III A high-quality crystal growth can be obtained by keeping the ratio of 2.5 to 2.5 or less (preferably 2 or less) (for details, refer to the specification of Japanese Patent Application No. 2-313438). During this crystal growth, the diameter of the island having a step difference of one atomic layer becomes small, and an exciton in the quantum well or a flat interface is effectively created for carriers near the interface.

Then, when the temperature is raised above the substrate temperature during growth in a reducing atmosphere, the crystal defects can be recovered. At this time, if the heat treatment temperature is too high or the treatment time is too long, side effects such as collapse of the quantum well structure, diffusion of dopants, and detachment of As atoms from the surface occur. Heat treatment at 500 ℃ ~ 800 ℃ at 10
Side effects do not occur or are negligible when run between minutes and 120 minutes.

Further, defects in the crystal can be reduced by passing a current through the semiconductor film grown at a low temperature.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of a first embodiment of a process for manufacturing a III-V group compound semiconductor device to which the present invention is applied, which is a GaAs / A having an effectively flat interface.
1 shows a process of manufacturing a quantum well of 1GaAs. FIG. 2 is an explanatory diagram showing the structure of the quantum well of this embodiment (FIG. 2A) in comparison with the conventional example (FIG. 2B).

As shown in FIG. 3, the n-GaAs substrate 11
0.5 μ of undoped GaAs buffer layer 12 on top of
A barrier layer 13 of Al _0.3 Ga _0.7 As is formed on the buffer layer 12 of 1.5 μm, and an undoped GaAs quantum well layer 14 of 8 nm is formed on the barrier layer 13. Further, an undoped Al _0.3 Ga _0.7 As barrier layer 15 of 1.5 μm is formed on the quantum well layer 14, and an undoped GaAs cap layer 16 is formed of 0.2 μm on the barrier layer 15.
m, respectively.

In this embodiment, first, the substrate temperature is set to 400 ° C. by the MBE method and the V / III flux ratio γ.
(The number of incoming molecules of group V with high vapor pressure is
(Value divided by the number of flying molecules of the group) so that γ = 1. 1 for the Al _0.3 Ga _0.7 As layer, γ = 1.57 for the GaAs quantum well layer 14 ( See step 1 of FIG. 1). Quantum well 14 manufactured in this way
Is excited with an Ar laser having a wavelength of 514.5 nm and the photoluminescence at 77K is observed. Then, the full width at half maximum is 3.5 meV, and the thermal energy (6.6
It can be seen that a flat interface narrower than meV) was formed. Also, comparing the emission intensity with that grown at a high substrate temperature (625 ° C.), it is found that it is about ⅛ of that, and contains many non-radiative recombination centers due to low temperature growth.

Then, 700 ° in a hydrogen flow of 1 atm.
When the heat treatment of C is performed for 0.5 hours (see step 2 in FIG. 1),
The crystal defects are annealed to reduce the non-radiative recombination centers. That is, the emission intensity is eight times as high as that at high temperature growth. At this time, the steepness of the quantum well interface is not lost, and the full width at half maximum of photoluminescence does not change.

In this embodiment, in order to adjust the As pressure during the heat treatment, a GaAs wafer was used as another As source to arrange the face to face (face to face). Is not particularly necessary. Also, other A
The heat treatment may be performed in a capless state without using the s source.

Next, a second embodiment of the present invention will be described. FIG. 4 shows a semiconductor laser (GR
FIG. 5 is an explanatory diagram of a process of manufacturing an IN-SCH-SQW laser diode), and FIG. 5 is an explanatory diagram of a structure of a semiconductor laser.

As shown in FIG. 5, an n-GaAs substrate 21
On top of it, a Si-doped GaAs buffer layer 22 of 0.5 is formed.
μm, Si-doped GaAs on the buffer layer 22
A multiple quantum well (MQW) buffer layer 23 consisting of 10 layers each having a thickness of 10 nm and Si-doped Al _0.5 Ga _{0.5 As 4} nm is repeatedly formed on the MQW buffer layer 23.
Doped Al _0.5 Ga _0.5 As clad layer 24 is 1.5μ
m, respectively.

Further, on the clad layer 24, 2000
Å Thick optical confinement region Si-doped Al _y Ga _1-y A
s25 is formed, and the Al content y thereof changes gradually from 0.5 and decreases to 0.3 near the active layer 26.

Single quantum well (SQW) 26 which is an active layer
Is composed of an undoped Al _0.3 Ga _{0.7 As} 10 nm barrier layer, an undoped GaAs 6 nm well layer, and an undoped Al _0.3 Ga _{0.7 As} 10 nm barrier layer. On this single quantum well 26, 2000 Å of Be-doped Al _z Ga ₁ -z As 27, which is the upper optical confinement region, is formed. The Al content z at this time also changes gently, and in contrast to the lower optical confinement layer 25, 0.3 to 0.5.
Rise to. Further, a Be-doped Al _0.5 Ga _0.5 As clad layer 28 is formed to a thickness of 1.5 μm on the upper optical confinement layer 27, and a Be-doped GaAs cap layer 29 is formed to a thickness of 0.5 μm thereon.

In this embodiment, first, the substrate temperature is set to 425 ° C. by the MBE method, and the group V / group III flux ratio is set to A.
A film was formed on the 1 _0.5 Ga _0.5 As layer so that γ = 1.1 (see step 1 in FIG. 4). GaA of the active layer 26
The group V / group III flux ratio when the s layer grows is
It becomes 2.2. Then, the formed laser wafer was placed in a hydrogen flow of 1 atm and heat treatment was performed at 700 ° C. for 1 hour (see step 2 in FIG. 4). As a result, the effect of recovery from crystal defects appeared in the change in laser oscillation threshold current density. For example, in the case of processing into a broad area stripe laser having a width of 100 μm and a cavity length of 400 μm, the oscillation threshold current density before heat treatment is 1.5 kA / cm ^2.
However, it decreased to 0.53 kA / cm ² after the heat treatment.

Whether or not each layer is doped does not affect the process and results of this embodiment.

Next, the third embodiment will be described. FIG. 6 is an explanatory diagram showing the structure of a high electron transfer transistor (HEMT).

In FIG. 6, reference numeral 31 is a semi-insulating GaAs substrate, and 32 is an undoped Ga which becomes an active layer region having a thickness of 1 μm.
As, 33 is a spacer layer of 100 Å of Al _x Ga _1-x
As, 34 is 1 μm thick Si-doped Al _x Ga _1-x As,
Reference numeral 35 is a source, 36 is a gate, 37 is a drain, 39 is isolation, and 40 is undoped GaAs of a buffer layer deposited on the substrate 31. In this example, the Al content x of the layers 33 and 34 was set to 0.25. Further, 38 is a two-dimensional electron gas.

A feature of the device fabrication with the above structure is that the flux ratio γ during film growth is maintained at 2.0 or less, and As ₄ (a molecular one in which 4 atoms are collected)
The pressure was 1 × 10 ⁻⁵ Torr. Thus, the V / III flux ratio γ is 1.4 for AlGaAs and GaAs
It became 1.9. As a result, a good quality compound semiconductor crystal was obtained even when grown at a low temperature. In particular, the two-dimensional electron gas 38 is composed of the active layer 32 of undoped GaAs and Al _x Ga.
Exists near the interface between the _1-x As spacer layers 33,
This interface can be made effectively flat.

The device thus manufactured is
When the heat treatment was carried out at 600 ° C. for 1 hour in the hydrogen flow at atmospheric pressure, the carrier mobility was significantly improved.

In the above-mentioned first to third embodiments, Al is used.
Although a GaAs-based material is mainly used, other than this, for example, a hetero interface composed of a combination of GaP / AlGaP / GaInAs may be used. Even when these materials are used, the same effect as that of the above-mentioned embodiment is obtained.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a sectional view of a single quantum well (SQW) laser manufactured by the crystal improvement method to which the present invention is applied.

As shown, a Si-doped GaAs buffer layer 52 is formed on an n-GaAs substrate 51, and Si-doped Al _0.5 Ga _{0.5 As} 53 is formed on the buffer layer 52.
Are formed with a thickness of 1.5 μm. Further, on the buffer layer 52, a lower light confinement layer 54, an active layer 55, an upper light confinement layer 56, and a layer 5 of doped Al _0.5 Ga _0.5 As.
7. The cap layer 58 is formed and laminated in this order.

The lower optical confinement region 54 is 2000 Å thick undoped Al _y Ga _1-y As,
The Al content y changes from 0.5 to graded and decreases to 0.3 near the active layer 55. The active layer 55 is 7
It is 0 Å thick undoped GaAs, the upper optical confinement region 56 is 2000 Å undoped Al _z Ga _{1 -z} As, and the Al content z is
It rises from 0.3 near the active layer 55 as opposed to the lower light confinement layer 54 to 0.5. Layer 57 is 1.5 μm thick and cap layer 58 is 0.5 μm Be-doped GaAs.

After the layers are laminated, the substrate 51 is placed on the substrate 100.
It is thinned to about μm, and Cr / Au59 is used as the p-side electrode.
And AuGe / Ni / Au60 as the n-side electrode, respectively, and processed to form an SQ having a ridge-shaped waveguide.
A W laser was produced.

A current was passed through the SQW laser manufactured in this manner at an ambient temperature of 70 ° C. FIG. 8 shows a temporal change in the threshold current density during the energization. In FIG. 8, the horizontal axis 61 is the energization time, and the vertical axis 62 is the threshold current (mA) of the SQW laser. As shown in the figure, there is a tendency that the threshold current decreases as the energization time elapses and becomes saturated after a certain time. As a result of energization, the threshold value of the SQW laser was 2/3 of that of the non-energized one.
Depending on the conditions, it may be halved, but once the threshold becomes stable and constant, it will not change thereafter.

Incidentally, it is desirable to energize the SQW laser in a state where laser oscillation is not performed as much as possible. This is because when laser oscillation is performed, the end face may be deteriorated by the laser light. Further, the crystal improvement does not affect the optical output of the laser and largely depends on the energization amount and the ambient temperature.

Here, one example of how the crystal improvement depends on the amount of electricity and the ambient temperature is shown. FIG. 9A shows the relationship between the ambient temperature and the improved current amount when the supply current amount is constant, and FIG. 9B shows the relation between the supply current amount and the improved current amount when the ambient temperature is constant. The relationship with the current amount is shown respectively. As can be seen from the figure, the higher the ambient temperature, the greater the amount of current that decreases, and the greater the amount of supplied current, the greater the improvement rate.When energizing at the same level, the ambient temperature is raised and laser power is generated without energizing. The improvement is greater and the end surface deterioration is less.

Next, a fifth embodiment of the present invention will be described. FIG. 10 is a sectional view of a semiconductor laser having a multiple quantum well (MQW) structure in an active layer.

In the figure, 71 is a substrate of 0.5 μm.
Thick p-GaAs, 72 is a buffer layer of 0.5 μm
Be-doped GaAs, 73 is a cladding layer 1.5
μm thick Be-doped Al _0.5 Ga _0.5 As, 74 is an optical confinement layer 200 nm thick Be-doped Al _x Ga _1-x A
s and 75 are non-doped GaAs and Al _0.3 which are active layers.
It has a five-layer structure of Ga _0.7 As. The active layer 75 further includes an upper optical confinement layer 76, a doped Al _0.5 Ga _0.5 As layer.
Layer 77 and cap layer 78 are formed and laminated in this order. The Al composition of the light confinement layer 74 is 0.5 at the interface with the cladding layer 73 and 0.3 at the interface with the active layer 75.

In the active layer 75, first, non-doped Ga is used.
As is formed in a layer with a thickness of 6 nm, and non-doped A is formed on the layer.
l _0.3 Ga _0.7 As is formed in a 10 nm thick layer. Then, a layer of non-doped GaAs and non-doped Al _0.3 Ga
_{The 0.7} As layer is laminated five times to form the active layer 75.

76 is an upper optical confinement layer, 200 nm
The thick Si-doped Al _x Ga _1-x As, 77 is a cladding layer having a thickness of 1.5 μm Si-doped Al _0.5 Ga _0.5 As, 7
8 is a contact layer of 0.5 μm thick Si-doped Ga
It is As. The Al composition of the clad layer 77 is equal to that of the active layer 75.
It is 0.3 at the interface with and is 0.5 at the interface with the upper cladding layer 77. 79 is AuGe / A which is an n-side electrode
u is 80, and Cr / Au is a p-side electrode.

Also in the MQW laser having the above-mentioned structure, the effect of crystal improvement due to energization can be seen. Specifically, 70 ° C
Ambient temperature for about 10 hours, the threshold value is 2/3
Could be about. Further, the same phenomenon result as above was confirmed for the normal double hetero (DH) structure in which the active layer has a thickness of about 0.1 μm, and the method of crystal improvement by energization can be applied to a low-temperature grown semiconductor laser. Was demonstrated.

The crystal improvement method of this embodiment can also be applied to a low-temperature grown light emitting diode or the like. In optical communication etc.,
Integration of semiconductor devices is an important technology for realizing high-speed communication. In the process of integrating semiconductor devices,
The technique of low temperature growth is important for the process, but by combining it with the crystal improvement method of this example, a consistent process can be realized at a low temperature of 500 ° C. or lower.
Furthermore, if optimization is performed, an integrated process at a low temperature of about 350 ° C can be realized.

By such a low temperature growth technique and the crystal improvement method by energization of the present invention, AlGaAs is formed on the Si substrate.
A system laser can be made. An example of the fabrication will be described below.

In FIG. 11, the substrate temperature 3 is set on the Si substrate 82.
It is explanatory drawing of the growth method which makes Si dope GaAs83 grow at 50 degreeC. The defect density of the Si-doped GaAs 83 was 1 × 10 ⁵ cm ^-2 . Compared to the conventional one, an improvement of two digits or more was achieved, but this improvement was due to the relaxation of stress due to the difference in thermal expansion coefficient.

FIG. 12 is a sectional view of the semiconductor laser of the sixth embodiment. The above-mentioned stress relaxation method is used for manufacturing this semiconductor laser. The semiconductor laser was produced on a Si substrate, and the Al content of the clad layer was 0.5.

In FIG. 12, 91 is a (001) plane n-type Si substrate, 92 is a 0.5 μm thick Si-doped GaAs,
93 is a 2.0 μm thick Si-doped Al _0.5 Ga _0.5 As,
94 is 500 Å thick Si-doped Al _x G
a _1-x As optical confinement layer (x is reduced from 0.5 to 0.3), 95 is 70 Å thick undoped G
Active layer of aAs, 96 is B of 500 angstroms thick
The upper optical confinement layer of e-doped Al _y Ga _1-y As (y is increased from 0.3 to 0.5), 97 is 1.5 μm thick B
e-doped Al _0.5 Ga _0.5 As upper cladding layer, 98 Be-doped GaAs cap layer, 99 p-type electrode, 1
00 is an n-type electrode.

The MBE method is adopted as the growth method, and GaA
Growth rate of s95 is 0.7 μm / h, substrate temperature is 350
The substrate rotation speed was 12 rpm. The As pressure was controlled so that the flux ratio of each layer was maintained at 2 or less. As a result, the threshold current density was ² kA / cm ² . Furthermore, 6
The threshold value was improved to 1 kA / cm ² when electricity was applied for about 10 hours at an ambient temperature of 0 ° C.

As in this example, a good quality film can be formed even at low temperature growth by energizing the GaAs when it is grown on the Si substrate.

In this embodiment, the structure of the active layer is S
Not only QW but also MQW structure and thickness without quantum effect.
About 1 GaAs or the like may be used. Further, although the MBE method is adopted in the present embodiment, a part of the layers of the semiconductor device may be formed by the MEE method (Migration Enhanced Epitaxy) (For details of the MEE method, see Japanese Journal of Applied Physics, for example. Vol.28, No.
2, February, 1989, pp.200-209).

In the MBE method, the semiconductor constituent materials are continuously supplied, and in the MEE method, the materials such as Ga, Al, As are supplied alternately or in groups III and V. The MEE method is a low-temperature process and has high quality (high crystallization).
Although 1GaAs and GaAs can be obtained, there is a problem that the growth rate is slow because the materials are alternately supplied, but this can be overcome by combining the low flux ratio growth of this growth method.

Here, an example of a growth method partially adopting the MEE method will be described. In the fifth embodiment (FIG. 10), Al _0.4 Ga _0.6 of the lower optical confinement layer was formed by the MEE method.
As 74, MQW layer 75, Al _0.4 G of upper confinement layer
a _0.6 As76 is grown. A and Ga as a pair
The substrate was alternately irradiated with s. The composition ratio was determined by the amount of flux. In this example, the threshold current density is 1.5 kA / cm
² is obtained, to obtain a threshold value of 800A / cm ² by energization.

As other materials, II-VI type materials can be applied. For example, ZnSe, CdTe and the like are materials that require low temperature growth, but GaAs and AlGaAs systems have a problem that the crystal quality deteriorates at low temperature growth, but a good quality crystal is obtained by energizing. be able to. That is, the low temperature growth material and III-V typified by GaAs are obtained by the crystal improvement method by energization.
A composite with a group compound semiconductor system can be realized.

[0074]

As described above in detail, according to the present invention, the substrate temperature during the growth of the compound semiconductor hetero interface is 500 ° C.
The diameter of an island having a step difference of one atomic layer is reduced as follows. Therefore, a flat interface can be effectively produced for the excitons in the quantum well or carriers near the interface.
By subsequent heat treatment, crystal defects caused by low temperature growth can be recovered, so that a semiconductor device having excellent crystallinity and interface flatness can be manufactured.

Further, according to the present invention, since the crystal is improved by forming the crystal laminated film by low temperature growth and passing an electric current through the grown crystal laminated film, a low temperature consistent process of the semiconductor device can be realized. , ZnSe, CdTe
Of low temperature materials such as Si and Ga on Si substrate
Crystal growth of a strained material system represented by As production can be realized.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is an explanatory view showing the structure of the quantum well of the first embodiment in comparison with the conventional example.

FIG. 3 is an explanatory diagram of the structure of the semiconductor laser of the first embodiment.

FIG. 4 is an explanatory view of the manufacturing process of the second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a structure of a semiconductor laser according to a second embodiment.

FIG. 6 is an explanatory diagram of a HEMT structure according to a third embodiment.

FIG. 7 is a sectional view of a fourth embodiment of the present invention.

FIG. 8 is a graph showing the change over time of the threshold current density.

FIG. 9 is an explanatory diagram of characteristics of an energization amount, an ambient temperature, and a current change amount.

FIG. 10 is a sectional view of a fifth embodiment of the present invention.

FIG. 11 is an explanatory diagram of a Si-doped GaAs growth method.

FIG. 12 is a sectional view of a sixth embodiment of the present invention.

FIG. 13 is a sectional view of a semiconductor laser manufactured by a conventional growth method.

FIG. 14 is a graph showing characteristics of a laser manufactured by a conventional growth method.

FIG. 15 is a graph showing diffusion characteristics of Sn-doped GaAs.

FIG. 16 is a cross-sectional view of a double heterojunction laser manufactured by a conventional growth method.

FIG. 17 is a graph showing characteristics of a laser manufactured by a conventional growth method.

FIG. 18 is an explanatory diagram of a conventional growth method for growing ZnSe on a GaAs substrate.

FIG. 19 is an explanatory diagram of a conventional growth method for growing ZnSe on a GaAs substrate.

[Explanation of symbols]

 11,21,51 n-GaAs substrate 12 undoped GaAs buffer
Layer 13,15 Undoped Al_0.3Ga_0.7A
s barrier layer 14,26 undoped GaAs quantum well
Layer 16 GaAs cap layer 22 n-GaAs buffer layer 23 n-MQW buffer layer 24 n-Al_0.5Ga_0.5Askura
Dead layer 25 n-Al_yGa_1-yAs light closed
Packing layer 27 p-Al_zGa_1-zAs light closed
Packing layer 28 p-Al_0.5Ga_0.5Askura
Dead layer 29 p-GaAs cap layer 31 Semi-insulating GaAs substrate 32 High-purity GaAs layer 33 Al_0.25Ga_0.75As Space
Layer 34 n-Al_0.25Ga_0.75As
Pacer layer 35 Source 36 Gate 37 Drain 38 Two-dimensional electron gas 39 Isolation 52 Si-doped GaAs buffer
Layer 53 Si-doped Al_0.5Ga_0.5A
s clad layer 54 undoped Al_yGa_1-yAs
Lower optical confinement layer 55 Undoped GaAs active layer 56 Undoped Al_zGa_1-zAs
Upper optical confinement layer 57 Be-doped Al_0.5Ga_0.5A
s clad layer 58,98 Be-doped GaAs cap
Layer 59,60,79,80,99,100
Electrode 61 Conduction time 62 Threshold current 71 p-GaAs substrate 72 Be-doped GaAs buffer
Layer 73 Be-doped Al_0.5Ga_0.5A
s Clad layer 74 Be-doped Al_xGa_1-xAs
Light confinement layer 75 Undoped MQW active layer 76 Si-doped Al_xGa_1-xAs
Light confinement layer 77 Si-doped Al_0.5Ga_0.5A
s Clad layer 78 Si-doped contact layer 82, 91 Si substrate 83 Si-doped Ga As layer 92 Si-doped GaAs buffer
Layer 93 Si-doped Al_0.5Ga_0.5A
s clad layer 94 Si-doped Al_xGa_1-xAs
Optical confinement layer 95 Undoped GaAs active layer 96 Be-doped Al_yGa_1-yAs
Light confinement layer 97 Be-doped Al_0.5Ga_0.5A
s clad layer

Claims (15)

[Claims] 1. A crystal-improving process comprising a step of heat-treating a semiconductor device including a semiconductor film formed by growing a compound semiconductor by vacuum deposition at a substrate temperature of 500 ° C. or lower in a reducing atmosphere. Manufacturing method of compound semiconductor device. 2. The method for manufacturing a compound semiconductor device according to claim 1, wherein the compound semiconductor contains at least a group III and a group V. 3. The method of manufacturing a compound semiconductor device according to claim 1, wherein the reducing atmosphere is an atmosphere containing hydrogen. 4. The ratio of the number of flying molecules of the group V and the group III of the semiconductor film (a value obtained by dividing the number of flying molecules of the group V having a high vapor pressure by the number of flying molecules of the group III having a low vapor pressure). The method for producing a compound semiconductor device according to claim 1, wherein the compound semiconductor device is grown while being kept at 0.5 or less. 5. The method for manufacturing a compound semiconductor device according to claim 1, wherein the vacuum vapor deposition is performed by a molecular beam epitaxial growth method. 6. The method of manufacturing a compound semiconductor device according to claim 1, wherein the atmosphere of the heat treatment is kept at 100% hydrogen. 7. The heat treatment temperature is 500 ° C. to 800 ° C.
The method for producing a compound semiconductor device according to claim 1, wherein the temperature is in the range of ° C. 8. The method of manufacturing a compound semiconductor device according to claim 1, wherein the heat treatment time is in the range of 10 minutes to 120 minutes. 9. The method of manufacturing a compound semiconductor device according to claim 2, wherein the semiconductor film contains at least arsenic and gallium. 10. The method for manufacturing a compound semiconductor device according to claim 1, wherein the semiconductor film contains aluminum. 11. A compound semiconductor in which a crystal laminated film formed on a substrate is made of a plurality of materials of different groups based on the periodic table, and the crystal laminated film is produced at a crystal growth temperature of 500 ° C. or less. A method for manufacturing a compound-semiconductor device with improved crystal, characterized in that crystal is improved by applying an electric current to the crystal laminated film. 12. The method of manufacturing a compound semiconductor device according to claim 11, wherein the crystal is improved by passing an electric current through the crystal laminated film at a temperature lower than a growth temperature. 13. The compound semiconductor device is V / II.
The method for manufacturing a compound semiconductor device according to claim 11, wherein the compound semiconductor device is formed of Group I. 14. The crystal laminated film is produced with a ratio of the number of flying molecules (a value obtained by dividing the number of flying molecules of a group having a high vapor pressure by the number of flying molecules of a group having a low vapor pressure) of 2.5 or less, The method of manufacturing a compound semiconductor device according to claim 11, wherein the crystal laminated film does not include an active layer, and the crystal laminated film is formed closer to the substrate than the active region. 15. A compound semiconductor in which a crystal laminated film formed on a substrate is formed of materials of different groups based on the periodic table, and the crystal laminated film is produced at a crystal growth temperature of 500 ° C. or lower. A method for manufacturing a compound semiconductor device, comprising a step of reducing crystal defects caused by a low growth temperature in the method for manufacturing a device.