JPH05275653A - Manufacture of rom semiconductor memory device - Google Patents

Abstract

PURPOSE:To lessen the process of manufacturing a ROM semiconductor memory device in turnaround time by a method wherein a ROM code write process is positioned as late as possible. CONSTITUTION:After an aluminum wiring 29 is formed, a first interlayer insulation film 27 of a matrix transistor part is selectively etched to make an opening, and phosphorus is thermally diffused using a second interlayer insulating film 30 in the opening as the its diffusion source to transform the matrix transistor into a depression type.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ROM semiconductor memory device, and more particularly to a method of manufacturing an N-channel transistor vertical-stack NAND type ROM semiconductor memory device (vertical-stack NAND type ROM). Is.

[0002]

2. Description of the Related Art FIG. 9 shows an N-channel transistor vertically stacked NAND type ROM semiconductor memory device (vertically stacked NAND type R
It is a partial circuit diagram of (OM). In the figure, a portion surrounded by a broken line is an N-channel matrix transistor Q _M , and the enhancement type or the depletion type is switched by a ROM coding mask. The on / off of the matrix transistor Q _M is controlled by the word line WL. A plurality of matrix transistors Q _M and vertical stack, the both ends, P-channel transistor Q _P for precharging, the N-channel transistor Q _N are provided. And P
The connection node a between the channel transistor Q _P and the matrix transistor Q _M is input to the sense amplifier SA, and the output Vout is taken out.

The operation of the vertically stacked NAND type ROM described above is as follows.
This is done as follows. First, all the word lines WL are set to the high level, and the clock * φ _P is lowered to the low level to perform precharge. This allows
The node a is charged to the power supply potential Vdd. After that, the precharge is completed by raising the clock φ _P to the high level. Then, one word line selected by the address decoder (not shown) falls to the low level. As a result, when the matrix transistor Q _M is the enhancement type, it is turned off, so that the node a holds the state of being charged to Vdd by the node capacitance, and “0” is output from Vout. On the other hand, when the matrix transistor Q _M is of the depletion type, it remains in the ON state, so that the node a is connected to the ground potential V through the matrix transistor Q _M in a vertical stack.
It is discharged to ss and "1" is output from Vout.

10 to 12 are vertical products N according to the conventional example.
FIG. 9 is a process cross-sectional view showing the method of manufacturing the matrix portion of the AND-type ROM. Hereinafter, description will be given in the order of the drawings. FIG. 10: First, the element isolation insulating film (2) and the gate insulating film (3) are formed on the P-type silicon substrate (1) in advance, and the device stands by. Then, when the ROM code is designated, based on the ROM code, information indicating which matrix transistor Q _M is the depletion type is patterned R
Create an OM coding mask. Next, this RO
A photolithography process is performed using the M coding mask. As a result, a resist pattern (4) is formed in which the channel region of the depletion type matrix transistor Q _M is selectively opened. Then, phosphorus ions ( ⁺ P ³¹ ) are applied to the resist pattern (4).
Ion implantation is performed from the opening portion of to form an N ⁻ type channel diffusion layer (5) on the surface of the P type silicon substrate (1).

FIG. 11: The resist pattern (4) is removed. Then, a gate electrode (6) made of polysilicon is formed at a predetermined position. FIG. 12: N ⁺ type source diffusion layer (7) and drain diffusion layer by implanting arsenic ions ( ⁺ As ⁷⁵ ) into the surface of the P type silicon substrate (1) using the gate electrode (6) as a mask. (8) is formed. by this,
The matrix transistor Q _M selected according to the ROM code is formed in the depletion type, and the other matrix transistors Q _M are formed in the enhancement type.

FIG. 13: An interlayer insulating film (9) such as a BPSG film is formed on the entire surface of the wafer by using the LPCVD method. Figure 14: Vertically stacked end matrix transistors Q
_M source diffusion layer (7) or drain diffusion layer (8)
The upper interlayer insulating film (9) is selectively etched to form a contact hole (10). Then, an aluminum wiring (11) is formed on the contact hole (10) and the interlayer insulating film (9).

FIG. 15: A protective film (12) such as a Si ₃ N ₄ film is formed to complete a vertically stacked NAND type ROM.

[0008]

However, in the above-described manufacturing method, the step for writing the ROM is performed in the ion implantation step before the formation of the gate electrode (6), so that the number of manufacturing steps until completion is large. Many, therefore RO
It had the drawback of a long turn around time (TAT) from the time it took to complete the order.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to shorten the TAT by delaying the step for writing ROM to the step as late as possible.

[0010]

According to the present invention, after the aluminum wiring (29) is formed, the first interlayer insulating film (27) in the matrix transistor Q _M portion is selectively etched to form an opening. The main content is to make the matrix transistor Q _M a depletion type by thermally diffusing phosphorus using the second interlayer insulating film (30) embedded in the substrate as a diffusion source.

[0011]

According to the above-mentioned means, the process for writing the ROM code can be postponed after the formation of the aluminum wiring (29), so that the number of manufacturing steps thereafter is smaller than that of the conventional example, and the TAT is greatly shortened. Can be converted.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 to 8 are process cross-sectional views showing a method of manufacturing a matrix portion of a vertically stacked NAND type ROM according to an embodiment of the present invention. Hereinafter, description will be given in the order of the drawings. FIG. 1: A device isolation film (22) is formed on a low-concentration P-type silicon substrate (21) by a selective oxidation method, and then a gate insulating film (23) having a film thickness of about 300 Å is formed by a thermal oxidation method. Vertical stack RO from above the gate insulating film (23)
Boron ion ⁺ B on the entire surface that becomes the matrix part of M
¹¹ is, for example, the injection amount 1 × 10 ¹² / cm ² , the acceleration energy −
Ions are implanted under the condition of 70 KeV to adjust the threshold voltage of the enhancement type matrix transistor Q _M.

FIG. 2: A gate electrode (24) made of polysilicon is formed on the gate insulating film (23), and the gate electrode (24) is used as a mask to form arsenic ions ( ⁺ As).
⁷⁵ ) is ion-implanted into the surface of the P-type silicon substrate (21) under the conditions of, for example, an implantation amount of 5 × 10 ¹⁵ / cm ² and an acceleration energy of −80 KeV to form an N ⁺ -type with a junction depth of about 0.3 μm. A source diffusion layer (25) and a drain diffusion layer (26) are formed.

FIG. 3: Film thickness of about 8000 made of BPSG or the like
The first interlayer insulating film (27) of Å is formed by applying the LPCVD method. Figure 4: Vertically stacked end matrix transistor Q _M
Source diffusion layer (25) or drain diffusion layer (2)
6) The upper first interlayer insulating film (27) is selectively etched to form a contact hole (28). Then, an aluminum wiring (29) is formed on the contact hole (28 and the first interlayer insulating film (27). Then, in the state where this step is completed, the ROM code is instructed and the ROM coding mask is completed. Wait until you do.

FIG. 5: When a ROM code is designated, a ROM coding mask is created based on this. RO
The M coding mask is a pattern of information indicating which matrix transistor Q _{M is} to be the depletion type, and is composed of a rectangular region including the gate region of the matrix transistor Q _M. And
Using this ROM coding mask, the first interlayer insulating film (27) is selectively etched and opened. As a result, the gate electrode (24) of the matrix transistor Q _M selected according to the ROM code and the portions of the source diffusion layer (25) and the drain diffusion layer (26) on the side in contact with the gate electrode (24) are exposed. ..

FIG. 6: A second interlayer insulating film (30) containing impurities at a high concentration is formed by LPCVD on the entire surface of the wafer including the opening of the first interlayer insulating film (27) formed in the above step. Deposited to a film thickness of 10000Å. The opening portion is filled with a second interlayer insulating film (30).

As the second interlayer insulating film (30),
A PSG film (ring lath film) containing 7 wt% to 10 wt% of phosphorus is used. While depositing the second interlayer insulating film (30) by this LPCVD method, phosphorus is thermally diffused into the substrate (21) from the exposed portions of the source diffusion layer (25) and the drain diffusion layer (26). To be done. Accordingly, phosphorus is diffused also into the channel region of the matrix transistor Q _M , so that the distance between the source diffusion layer (25) and the drain diffusion layer (26) is narrowed, and the threshold voltage of the matrix transistor Q _M is reduced due to the short channel effect. Decreases and approaches a depletion type.

Then, phosphorus is further diffused by adding necessary heat treatment, and the source diffusion layer (25) and the drain diffusion layer (26) are short-circuited. As a result, the matrix transistor Q _M becomes a depletion type which is always on. If the effective channel length of the matrix transistor Q _M is as small as about 1 μm, 800
It is possible to obtain a depletion type by heat treatment at a relatively low temperature of ℃ to 900 ℃.

FIG. 7: The second interlayer insulating film (30) is removed by an etch-back method except for the portion buried in the opening of the first interlayer insulating film (27) to flatten the surface. .. FIG. 8: According to the above-described manufacturing method of the present invention in which the protection film (31) made of a Si ₃ N ₄ film is formed to complete the vertically stacked NAND type ROM, the step for writing the ROM code is performed by the aluminum wiring (29). ) Can be carried down after forming, the number of manufacturing steps after that is less than the conventional example,
Therefore, TAT can be significantly shortened.

Although the surface flatness is deteriorated, the protective film (31) made of the Si ₃ N ₄ film may be directly formed by omitting the etching back step of the second interlayer insulating film (30). It is possible, the manufacturing process can be simplified, and the second interlayer insulating film (3
0) also has the effect of relieving the stress of the Si ₃ N ₄ film. Although it is feared that the moisture resistance may deteriorate as a result of doping the second interlayer insulating film (30) with phosphorus at a high concentration, by covering with a Si ₃ N ₄ film,
It is considered that there is no problem if the content concentration is about 10 wt% or less.

[0021]

As described above, according to the method for manufacturing the ROM semiconductor memory device of the present invention, the process for writing the ROM code can be postponed after the aluminum wiring (29) is formed. The number of steps is smaller than that of the conventional example, and thus the TAT can be significantly shortened.

Further, by omitting the step of etching back the second interlayer insulating film (30) and forming the protective film (31) made of the Si ₃ N ₄ film as it is, the number of manufacturing steps can be further reduced, and The second interlayer insulating film (30) doped with phosphorus at a high concentration also has an effect of relieving the stress of the protective film (31).

[Brief description of drawings]

FIG. 1 is a first sectional view according to an embodiment of a method for manufacturing a ROM semiconductor memory device of the present invention.

FIG. 2 is a second cross-sectional view according to the embodiment of the method for manufacturing the ROM semiconductor memory device of the present invention.

FIG. 3 is a third cross-sectional view according to the embodiment of the method for manufacturing the ROM semiconductor memory device of the present invention.

FIG. 4 is a fourth sectional view according to the embodiment of the method for manufacturing the ROM semiconductor memory device of the present invention.

FIG. 5 is a fifth sectional view according to the embodiment of the method for manufacturing the ROM semiconductor memory device of the present invention.

FIG. 6 is a sixth sectional view according to the embodiment of the method for manufacturing the ROM semiconductor memory device of the present invention.

FIG. 7 is a seventh sectional view according to the embodiment of the method for manufacturing the ROM semiconductor memory device of the present invention.

FIG. 8 is an eighth sectional view according to the embodiment of the method for manufacturing the ROM semiconductor memory device of the present invention.

FIG. 9 is an N-channel transistor vertically stacked NAND type R
FIG. 3 is a partial circuit diagram of an OM semiconductor memory device (vertical stack NAND type ROM).

FIG. 10 is a first cross-sectional view showing the method of manufacturing the ROM semiconductor memory device according to the conventional example.

FIG. 11 is a second cross-sectional view showing the method of manufacturing the ROM semiconductor memory device according to the conventional example.

FIG. 12 is a third cross-sectional view showing the method of manufacturing the ROM semiconductor memory device according to the conventional example.

FIG. 13 is a fourth cross-sectional view showing the method of manufacturing the ROM semiconductor memory device according to the conventional example.

FIG. 14 is a fifth cross-sectional view showing the method of manufacturing the ROM semiconductor memory device according to the conventional example.

FIG. 15 is a sixth cross-sectional view showing the method of manufacturing the ROM semiconductor memory device according to the conventional example.

Claims (3)

[Claims] 1. A step of forming an element isolation insulating film (22 and a gate insulating film (23) on a semiconductor substrate (21) of one conductivity type, and a gate electrode (24) via the gate insulating film (23).
A step of forming a source diffusion layer (25) and a drain diffusion layer (26) of opposite conductivity type by performing ion implantation using the gate electrode (24) as a mask; A step of forming one interlayer insulating film (27), a step of selectively etching the first interlayer insulating film (27) to form a contact hole (28), and the first interlayer insulating film (27) and a step of forming an aluminum wiring (29) on the contact hole (28), and by selectively etching the first interlayer insulating film (27), the gate of the depletion type matrix transistor Q _M. Electrode (24) and the gate electrode (24)
A portion of the source diffusion layer (25) and the drain diffusion layer (26) on the side in contact with the substrate are exposed, and a second interlayer insulating film (30) containing impurities of the opposite conductivity type is formed on the entire surface by LPCVD. And a step of thermally diffusing the impurities of the opposite conductivity type from the exposed portions of the source diffusion layer (25) and the drain diffusion layer (26) to make the matrix transistor Q _M a depletion type. The interlayer insulating film (30) is etched back to flatten its surface, and then a protective film (31) made of a Si ₃ N ₄ film.
A method of manufacturing a ROM semiconductor memory device, comprising the step of forming a semiconductor memory device. 2. A protective film (3) made of a Si ₃ N ₄ film on the second interlayer insulating film (30) without etching back the same.
2. The method for manufacturing a ROM semiconductor memory device according to claim 1, further comprising the step of forming 1) by laminating. 3. The method for manufacturing a ROM semiconductor memory device according to claim 1, wherein the impurity of opposite conductivity type is phosphorus.