JPH05275636A - Complementary connected insulating gate type fet integrated circuit - Google Patents

Abstract

PURPOSE:To boost the breakdown voltage by a method wherein impurity ion- implanted layers are provided in a previously specified gap between source.drain diffused layers formed by diffused impurities. CONSTITUTION:Boron is implanted to be driven into the surface of an N-type substrate 1 to form a P-type well 3 using an oxide film 2 formed on the substrate 1 as a mask. Next, the oxide film 2 is removed and after the formation of a new oxide film 4 to be coated with a photoresist 5, boron ions are implanted in a channel stopper 6 of an N channel transistor (NT) and a gap 7 between channel-drain diffused layers of a P channel transistor (PT). Next, after removing the oxide film 4 and photoresist 5, the other oxide film 8 is formed and then phosphorus ions are implanted in another channel stopper 10 of PT and another gap 11 between channel-drain diffused layers of the NT. Through these procedures, high potential can be absorbed into the ion-implanted layers thereby enabling the breakdown voltage to be boosted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of constructing a complementary connection insulated gate type field effect transistor integrated circuit (CMOS IC).

[0002]

2. Description of the Related Art Recently, with the advent of flat displays such as plasma and liquid crystal, a high withstand voltage transistor for driving has been demanded, and in particular, a high withstand voltage transistor circuit of a driving unit is integrated with a logic circuit of a peripheral control unit. Devices are needed.

CMOS ICs have been widely used as conventional logic ICs due to their characteristics of low power consumption, high-speed response, and high degree of integration, but if high-voltage CMOS transistors can be integrated together. It is possible to provide an excellent device utilizing the characteristics of CMOS in the above fields and the like.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a configuration system for realizing the above-described CMOS IC, and its gist is the same as the step of forming a channel stopper in the CMOS IC. The impurity ion-implanted layer formed in the process is provided in a predetermined gap between the source / drain diffusion layer formed by thermal diffusion of the impurity and the channel region of the transistor. It is intended that it can be manufactured by a process similar to the process.

[0005]

In a complementary connection insulated gate field effect transistor integrated circuit according to the present invention, an impurity ion-implanted layer formed in the step of forming a channel stopper is formed by thermal diffusion of impurities. It is characterized in that it is provided in a predetermined gap between the source / drain diffusion layer and the channel region of the transistor.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A sectional view of an embodiment of a CMOS IC according to the present invention is shown in FIGS.

First, using the oxide film 2 formed on the N-type substrate 1 as a mask, boron ions are implanted and driven in to form the P-type well 3. (FIG. 1) Next, the oxide film 2 is removed, a new oxide film 4 is formed, and after the photoresist 5 is applied, portions 6 and 7 are etched to remove N.
Boron ions are implanted in a predetermined gap 7 between the channel stopper 6 of the channel transistor (NT) and the channel-drain diffusion layer of the P-channel transistor (PT). The implantation layer is formed so as to overlap the gate / drain diffusion layer so as to ensure the connection with the channel under the gate and the drain diffusion layer. (FIG. 2) Next, after removing the oxide film 4 and the photoresist 5, an oxide film 8 is formed and a photoresist 9 is applied. Then, portions 10 and 11 are etched to remove the PT channel stopper 10.
Phosphorus ions are implanted into a predetermined gap 11 between the NT channel-drain diffusion layers. Similar to FIG. 2, this implantation layer is formed so as to overlap the gate and drain diffusion layers so as to ensure the connection with the channel-drain diffusion layer under the gate. (FIG. 3) Next, the diffusion of boron into the source 12 and drain 13 of PT is performed using the oxide film 8 formed after the removal of the oxide film 8 and the photoresist 9 as a mask. (FIG. 4) In FIG. 5, as in FIG.
5. Diffusion of phosphorus to the drain 16 is performed using the oxide film 14 as a mask.

Next, after the oxide film 14 is removed, a field oxide film 17 is formed, the oxide film in the gate region and in the drain region that will be in contact with the wiring later is removed, and a gate oxide film 18 is newly formed. (FIG. 6) Next, polycrystalline silicon 19 is deposited, boron or phosphorus is diffused, and then etched to the gate size. (FIG. 7) Next, after forming the protective film 20, the contact for electrode extraction is etched. (FIG. 8) Next, after depositing aluminum, etching is performed to form the electrode 21.
To form. (FIG. 9) Finally, the protective film 22 is deposited on the entire surface. (Fig. 1
0) In this embodiment, the ion-implanted layer of impurities into the predetermined gap between the channel-drain diffusion layer under the gate of the transistor acts as a normal carrier conductive layer when the drain voltage is low, As the voltage rises, a depletion layer extends from the channel and substrate to this ion-implanted layer, the voltage drop in the ion-implanted layer increases, and the drain voltage is absorbed by this ion-implanted layer, so that a high breakdown voltage can be achieved. ..

[0009]

According to the present invention, this ion implantation resistance layer is formed in the same step as the channel stopper forming step,
A desired high breakdown voltage CMOS transistor can be obtained by increasing the length of the ion implantation resistance layer within a predetermined range by optimizing the ion implantation amount without adding new steps.

In addition to the CMOS / IC having a silicon gate structure in which polycrystalline silicon is used for the gate, the present invention uses CMOS / IC in which various metals such as molybdenum and molybdenum silicide are used as the gate material, and further, the gate and the wiring. Aluminum gate structure CMO commonly made of aluminum
The same applies to S / IC and the like.

The high withstand voltage CMOS IC according to the present invention can be used not only in the field of displays but also in the fields of communication equipment and audio equipment to contribute to downsizing of the system, higher functionality, and further cost reduction.

[Brief description of drawings]

[Figure 1]

FIG. 10 is a sectional view of each of the manufacturing steps of the embodiment of the CMOS / IC of the present invention.

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[Procedure amendment]

[Submission date] February 8, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Next, after the oxide film 14 is removed, a field oxide film 17 is formed, the oxide film in the gate region and in the drain region that will be in contact with the wiring later is removed, and a gate oxide film 18 is newly formed. (FIG. 6) Next, polycrystalline silicon 19 is deposited, boron or phosphorus is diffused, and then etched to the gate size. (FIG. 7) Next, after forming the protective film 20, the contact for electrode extraction is etched. (FIG. 8) Next, after depositing aluminum, etching is performed to form the electrode 21.
To form. (FIG. 9) Finally, the protective film 22 is deposited on the entire surface. (Fig. 1
0) In this embodiment, the ion-implanted layer of impurities into the predetermined gap between the channel-drain diffusion layer under the gate of the transistor acts as a normal carrier conductive layer when the drain voltage is low, As the voltage rises, a depletion layer extends from the channel and substrate to this ion-implanted layer, the voltage drop in the ion-implanted layer increases, and the drain voltage is absorbed by this ion-implanted layer, so that a high breakdown voltage can be achieved. .. Chi words, such
The ion-implanted layer of the present invention which functions as
Kutronics ( 1978, 5-1) P. 102-P. 1
Clear 如 than explanation of the high voltage MOSFET in 27
It is well known and, as is well known,
However, the impurity concentration of the ion-implanted layer is absolutely
And source / drain are both low,
Even the low concentration of tea Nerusutoppa to be.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

As described above, the structure of the present invention is adopted in an integrated circuit.
By, Ru brought about the following effects. (A) Ion-implanted layer and channel of high breakdown voltage transistor
Manufacturing process by forming the stopper in the same process
Is simplified and the cost is reduced. (B) Separately implanting the ion-implanted layer and channel stopper
Once formed, the previously formed layer will be heat treated in a later step.
It spreads. Especially, the ion implantation layer is formed first.
If this is the heat treatment at the time Ji Yanerusutoppa formed
Diffuses to the channel side and causes a problem with the breakdown voltage of the high breakdown voltage transistor
However, the number of heat treatments is small because of simultaneous formation in the present invention.
Since there is no, and control of the spread of the diffusion of ions hitting inclusive layer
It will be easier. Similarly, the channel stopper also spreads the diffusion.
For easier control, optimize the dimensions of the placement of each layer,
High integration is possible. (C) The channel stopper has the same structure as the ion-implanted layer.
Since the pure things low concentration layer, This is diffuses transitional
Close to or in contact with the drain of the star,
Withstand voltage does not deteriorate . Therefore, drain the channel stopper.
It is also possible to place it close to the
It (D) Furthermore, the field stopper prevents field inversion.
Can be stopped and the breakdown voltage of the integrated circuit can be increased.
It In this way, high breakdown voltage and high integration are possible at low cost.
The CMOS IC of the present invention can be used not only in the display field but also in other fields.
Telecommunications equipment, by utilizing the acoustic equipment field, the system
Miniaturization of higher functionality, more it can contribute to cost reduction
It is something.

Claims (1)

[Claims] 1. An impurity ion-implanted layer formed in the step of forming a channel stopper is provided in a predetermined gap between a source / drain diffusion layer formed by thermal diffusion of impurities and a channel region of a transistor. A complementary connection insulated gate field effect transistor integrated circuit, which is provided.