JPH05275623A - Protective circuit - Google Patents

Abstract

PURPOSE:To prevent a protective circuit from performing an erroneous operation by an instantaneous pulse. CONSTITUTION:In a protective circuit which prevents the destruction of an output power transistor due to grounding or power supply short circuit, a delay circuit 9, with which reverse output is controlled by delaying non-inversion output for a specific period of time, is provided on an inversion circuit 1 with which the detected signal of grounding or power supply short circuit is separated to non-inversion output and inversion output. The delay circuit 9 is composed of first and second current mirror circuits 10 and 11 and a filter circuit 12, the non-inversion output can be delayed for a specific period of time by the delay circuit 9, and an instantaneous pulse is absorbed by the delay of inversion output even when the instantaneous pulse is included in the form of grounding or power supply short circuit detected signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit, more specifically, a class B push-pull type power IC for audio.
The present invention relates to a protection circuit which is used for the like and prevents the output power transistor from being destroyed when a ground fault or a power fault occurs.

[0002]

2. Description of the Related Art For example, a class B push-pull audio power IC generally has a built-in protection circuit for preventing the output power transistor from being destroyed when a ground fault or a power fault occurs. Target.

A conventional example of the protection circuit will be described with reference to FIG. This figure shows a part of the protection circuit. It has an inverting circuit (1) to which a detection signal that detects the occurrence of a ground fault or a power fault is input, and the ground fault and power fault of the inverting circuit (1). Working transistors (2a) (2b), reference transistor (3)
Current mirror circuits (4) (5) that supply current to the
A constant current circuit (6), a DC component removal transistor (7) connected to the reference transistor (3) of the inverting circuit (1), and transistors (2a) (2b) that operate during a ground fault and a power fault. And a bias cutoff transistor (8) for differentially stopping a bias circuit (not shown) for driving the output power transistor when a ground fault or a power fault occurs.

Next, the operation of the protection circuit having the above circuit configuration will be described.

First, in a normal state, the base voltage of the transistors (2a) (2b) that operate during ground fault and short-to-power fault is higher than the reference voltage Vref applied to the base voltage of the reference transistor (3) of the inverting circuit (1). Is set high, so A
The potential at the point is high. Therefore, the reference transistor (3) is in the ON state, and the DC component removal transistor (7) is also O.
It is in the N state, and the potential at the point B is as low as approximately the ground potential. As a result, the bias cutoff transistor (8) is held in the OFF state, the bias circuit is in the operating state, and the output power transistor is in the normal operating state.

On the other hand, when a ground fault or a power fault occurs, the detection signal is input to the inverting circuit (1) and the base currents of the transistors (2a) (2b) that operate at the time of the ground fault or the power fault are drawn and The base voltage decreases, and the potential at point A decreases as shown in FIG. Therefore, the transistors (2a) and (2b) that operate at the time of a ground fault or a power fault are turned on, and conversely,
The reference transistor (3) is turned off and the DC component removal transistor (7) is turned off. As a result, a current flows to the point B, its potential increases as shown in FIG. 5B, and a base current flows to the bias cutoff transistor (8). As a result, the bias cutoff transistor (8) is turned off.
N, the bias circuit is turned off and the output power transistor is deactivated.

[0007]

By the way, for example, B
In a class push-pull audio power IC, its output is divided into an upper stage and a lower stage, and in a normal state, when one of the upper and lower stages is in operation, the other is inactive. .. Here, when a signal having a high frequency and a large amplitude is input to the power IC, a phase shift occurs between the upper stage and the lower stage of the output, and the upper stage and the lower stage are in the operating state at the same time. Momentary pulse occurs. This instantaneous pulse is included in the detection signal for detecting the presence or absence of the ground fault or the power fault and is input to the protection circuit.

In the protection circuit, the input of the above-mentioned instantaneous pulse causes a malfunction. That is, when an instantaneous pulse is input to the transistors (2a) and (2b) that operate at the time of the ground fault or the power fault of the inverting circuit (1), the potential at the point A is instantaneous as shown in FIG. 6 (a). And the transistors (2a) and (2b) that operate at the time of a ground fault or a power fault are turned on and a current flows to the point B, and the potential at the point B momentarily rises as shown in FIG. 6 (b). .. As a result, the bias cutoff transistor (8) is turned on, the bias circuit is turned off, and the output power transistor is momentarily stopped, resulting in a problem of sound interruption.

Therefore, the present invention has been proposed in view of the above problems, and an object of the present invention is to provide a protection circuit capable of preventing a malfunction caused by an instantaneous pulse.

[0010]

As a technical means for achieving the above object, the present invention provides a protection circuit for preventing the output power transistor from being destroyed by a ground fault or a power fault. It is characterized in that an inverting circuit that separates a power fault detection signal into a non-inverting output and an inverting output is provided with a delay circuit that delays the non-inverting output for a predetermined time to control the inverting output.

The delay circuit is preferably composed of first and second current mirror circuits and a filter circuit.

[0012]

In the protection circuit according to the present invention, if the delay circuit delays the non-inverted output for a certain period of time, the inverted output is also delayed for a certain period of time, so that an instantaneous pulse causes a ground fault or a power fault. Even if it is included in the detection signal of 1, the instantaneous pulse can be absorbed by the delay of the inverted output.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a protection circuit according to the present invention will be described with reference to FIGS. The same or corresponding parts as those in FIGS. 4 to 6 are designated by the same reference numerals, and the duplicated description will be omitted.

A feature of the present invention is that a delay circuit (9) is added to the inverting circuit (1) as shown in FIG.

Specifically, the delay circuit (9) includes a first current mirror circuit (10) and a second current mirror circuit (10) as shown in FIG.
(11) and a filter circuit (12). First above
The current mirror circuit (10) has an input connected to the reference transistor (3) of the inverting circuit (1) and an output of the second
Connected to the current mirror circuit (11). Also, the second
The input of the current mirror circuit (11) is connected to the first current mirror circuit (10), and the output is connected to the filter circuit (12). On the other hand, the above filter circuit (12)
Is composed of a capacitor (13) and a transistor (14) Darlington-connected to the DC component removal transistor (7).

In the protection circuit of the present invention, since the inverting circuit (1) is provided with the delay circuit (9), the following operation is performed when an instantaneous pulse is generated.

First, in the normal state, as in the conventional case, the potential at the point A is high, the reference transistor (3) and the DC component removing transistor (7) are both in the ON state, and the potential at the point B is almost the ground potential. It is as low as.

In this state, a transistor (2a) whose momentary pulse operates when the inverting circuit (1) has a ground fault or a power fault
When input to (2b), the potential at point A momentarily decreases as shown in Fig. 2 (a), and the transistors (2a) and (2b) that operate during a ground fault or a short-to-power fault turn on and become the reference. The transistor (3) turns off. However, when the reference transistor (3) is turned off, the non-inverted output is the first of the delay circuit (9).
And the second current mirror circuit (10) (11) to be input to the filter circuit (12), and the filter circuit (12)
The ON state of the DC component removal transistor (7) is held for a certain period of time by the output of. As a result, the inverted output due to the ON state of the transistors (2a) and (2b) operating at the time of the ground fault or the short-to-power fault is delayed for a certain period of time while the DC component removing transistor (7) is kept in the ON state, and the current flows to the point B. 2B, and the potential at the point B does not momentarily increase as shown in FIG. Even if a momentary pulse is input in this way, the potential at point B does not momentarily rise, so the OFF state of the bias cutoff transistor (8) can be maintained, and the bias circuit is activated and the output power is The transistor can be maintained in the normal operating state without causing sound interruption.

When a ground fault or a power fault occurs, as shown in FIG.
As shown in (a), the reference transistor (3) is turned off and the DC component removal transistor (7) is turned off from the time when the potential at the point A becomes low until the current flows to the point B, that is, FIG. As shown in (b), there is the above-mentioned constant delay time (t) until the potential at the point B becomes high. However, since this delay time (t) is about 20 μsec, this destroys the output power transistor. There is no such thing.

In the above embodiment, since the transistor (14) is connected to the DC component removing transistor (7) by the Darlington connection, there is a possibility that the amplification degree is increased and the sensitivity in the protection circuit is lowered. By adjusting the emitter area ratio of each of the transistors by the first and second current mirror circuits (10) (11), the transistor (14)
This can be solved by reducing the base current of.

In the above embodiment, the case where the delay circuit (9) is composed of the first and second current mirror circuits (10) (11) and the filter circuit (12) has been described.
The present invention is not limited to this, and can have other specific circuit configurations.

[0022]

According to the protection circuit of the present invention, even if an instantaneous pulse is included in the ground fault or power fault detection signal,
Since the momentary pulse can be absorbed by the delay of the inverted output, the momentary pulse does not cause the protection circuit to malfunction, and the reliability is greatly improved. When used in an IC, it is possible to provide a high-quality audio power IC that does not cause problems such as sound breaks.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a protection circuit according to the present invention.

2A is a waveform diagram showing the potential at point A in FIG. 1 when an instantaneous pulse is input, and FIG. 2B shows the potential at point B in FIG. 1 when an instantaneous pulse is input. Waveform diagram shown

3A is a waveform diagram showing the potential at point A in FIG. 1 when a ground fault or a power fault occurs, and FIG. 3B is a waveform diagram at the point B in FIG. 1 when a ground fault or a power fault occurs. Waveform diagram showing potential

FIG. 4 is a circuit diagram showing a conventional example of a protection circuit.

5A is a waveform diagram showing the potential at point A in FIG. 4 when a ground fault or a power fault occurs, and FIG. 5B is a waveform diagram at the point B in FIG. 4 when a ground fault or a power fault occurs. Waveform diagram showing potential

6A is a waveform diagram showing the potential at point A in FIG. 4 when an instantaneous pulse is input, and FIG. 6B shows the potential at point B in FIG. 4 when an instantaneous pulse is input. Waveform diagram shown

[Explanation of symbols]

 1 Inversion circuit 9 Delay circuit 10 First current mirror circuit 11 Second current mirror circuit 12 Filter circuit

Claims (2)

[Claims] 1. A protection circuit for preventing an output power transistor from being destroyed by a ground fault or a power fault, and an inverting circuit for separating a detection signal of the ground fault or the power fault into a non-inverting output and an inverting output, A protection circuit, wherein a delay circuit for controlling the inverted output by delaying the non-inverted output for a predetermined time is additionally provided. 2. The protection circuit according to claim 1, comprising a first and second current mirror circuit and a filter circuit.