JPH05272988A - Absolute encoder - Google Patents

Abstract

PURPOSE:To obtain an absolute encoder which can process detection signals at the same timing and can output the process output signals nearly at the same time regardless of single signal-processing part. CONSTITUTION:Sample and hold circuits 4, 5, and 6 which can retain each incremental signal simultaneously are selected by a multiplexer 7, thus obtaining absolute position data by signal-processing parts 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 in sequence. Then, after the data are stored temporarily by shift registers 19, 20 and 21, all absolute position data are output nearly simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder.

[0002]

2. Description of the Related Art A plurality of absolute encoders have been used to control the position of a stage of a numerical controller or the like in the X, Y and Z directions. Then, the conventional absolute encoder is composed of a code plate on which a pattern for obtaining a signal indicating an absolute position is formed, a detecting unit that moves relative to the code plate and detects the pattern formed on the code plate, and a detecting unit. And a signal processing unit that converts the detection signal of 1 to a signal indicating an absolute position.

However, the use of a plurality of absolute encoders having such a structure has a plurality of signal processing sections, which requires a large number of signal lines and a large space, resulting in a high cost. was there. As a means for solving the problem, the present applicant has filed Japanese Patent Application No. 3-356.
In 241, a plurality of code plates on which a pattern for obtaining a signal indicating an absolute position is formed, a plurality of detectors that move relative to the plurality of code plates to detect a pattern, and a plurality of detectors are provided. An absolute encoder has been proposed which is composed of a signal selection means for sequentially selecting one of the detection signals to be detected and one signal processing unit for converting the selected detection signal into a signal indicating an absolute position.

[0004]

In the invention of the prior application as described above, the absolute encoder sequentially selects a plurality of code plates and a plurality of detectors in a time division manner, and a signal indicating an absolute position by one signal processing unit. However, there is a problem in that it is impossible to detect the pattern of each code plate at the same time.

For example, when mounted on a numerical control device such as an NC machine tool to control in the X, Y and Z directions, the numerical control device such as the NC machine tool obtains absolute values from the encoder in a time division manner. Extra recesses and grooves were formed on the machined surface to read the position signal. The present invention has been made in view of such problems, and an object thereof is to obtain an absolute encoder that can detect the pattern of each code plate at the same time even if there is only one signal processing unit.

[0006]

According to a first aspect of the present invention, there are N (N is an integer of 2 or more) code plates (1, 2, 3) each having an absolute pattern and an incremental pattern. And N code plates (1, 2, 3)
Relative to each other to detect absolute patterns by N absolute detecting means (50, 5).
1) and N incremental detection means (52, 53) that move relative to the N code plates (1, 2, 3) respectively to detect an incremental pattern, and N incremental detection means (52). , 53) for simultaneously holding the incremental signals respectively detected by the respective holding means (4, 5, 6) and the incremental signals and N held by the N holding means (4, 5, 6), respectively. Absolute detection means (50, 5,
The signal selecting means (7) and the signal selecting means (7) for sequentially selecting a combination of the incremental signal and the absolute signal detected from each of the same code plates from among the absolute signals respectively detected in 1). A signal processing unit (8, which converts the selected incremental signal and absolute signal into a signal indicating an absolute position.
9, 10, 11, 12, 13, 14, 15, 16, 1
7, 18) and the signal processing units (8, 9, 10, 11, 1).
2, 13, 14, 15, 16, 17, 18), and output means (19, 20, 21) for outputting the signals indicating the absolute position converted substantially at the same time.

[0007]

The operation of the absolute encoder according to the present invention is as follows.
Since the holding means for simultaneously holding the detection signals of the patterns of N code plates and the signal selecting means for sequentially selecting the held detection signals are provided, even if there is only one signal processing portion, the detection signals at the same time are provided. Can be processed and the processed output signals can be output at substantially the same time.

[0008]

1 shows a first embodiment of the present invention. The configuration and function of the absolute encoder in the present invention will be described below. The absolute encoder has three channels: a first channel CH1, a second channel CH2, and a third channel CH3.

The first channel CH1 has a linear scale 1. The linear scale 1 has an M series pattern 60 having a minimum reading unit of 128 μm as shown in FIG.
28 μm pitch incremental pattern 61 and 1
An incremental pattern 62 having a pitch of 6 μm is formed. Further, the first channel CH1 includes a first detector 50 and a second detector 51 that detect the M-sequence pattern 60, and a third detector that detects an incremental pattern 61.
It has a detector 52 and a fourth detector 53 for detecting the incremental pattern 62.

The first detector 50 includes sensors 50a, 50b, 50c, 50d and 50e arranged at 128 μm intervals.
・ ・ ・ A total of 14 (only 5 are shown in FIG. 2) are provided, and the second detector 51 includes the first to the sixth detectors 50 to 6.
Sensors 51a, 51b, 51c arranged 4 μm apart,
51d, 51e ... There are a total of 14 (only 5 are shown in FIG. 2), and these first detector 50 and second detector 5 are provided.
1 moves relative to the M-sequence pattern 60.

The reason why the two detectors 50 and 51 are provided for the M series pattern 60 is to detect the M series pattern 60 while avoiding the boundary of the minimum reading unit. Then, the first detector 50 and the second detector 51 are
It is switched by the X / Y signal. First detector 50 or second detector 51 switched by X / Y signal
Detects the M-series pattern 60, generates M-series data 70, and outputs the M-series data 70 serially in synchronization with the scan clock signal SCK (hereinafter, SCK signal).

The third detector 52 includes a sensor 52a and a sensor 5 having a 1/4 pitch phase difference with respect to the sensor 52a.
2b and moves relative to the incremental pattern 61, and the incremental A phase signals A1 and A of 128 μm pitch corresponding to the outputs of the sensors 52a and 52b.
A B-phase signal B1 with a 90 ° phase shift to the phase signal A1 is generated.

The fourth detector 53 comprises a sensor 53a and a sensor 5 having a quarter pitch phase shifted with respect to the sensor 53a.
3b, which moves relative to the incremental pattern 62, and which has a phase difference of 90 ° between the incremental A-phase signal A2 and the A-phase signal A2 of 16 μm pitch according to the outputs of the sensors 53a and 52b. B2 is generated.

Similarly, the configurations of the second channel CH2 having the linear scale 2 and the third channel CH3 having the linear scale 3 are the same as the configuration of the first channel CH1 as shown in FIG. In addition, each channel has
There is a light source (not shown), and 128 μ is provided between each scale 1, 2, 3 and each detector 50, 51, 52, 53.
An index scale for m pitch and an index scale for 16 μm pitch are interposed.

Referring again to FIG. 1, the first channel CH1
Is the incremental signal A from the linear scale 1.
1, B1, A2 and B2 are output to the sample hold circuit 4. Similarly, for the second channel CH2 and the third channel CH3, the incremental signals A1, B1, A2, B2 from the linear scale 2 or the linear scale 3 are used.
A sample hold circuit 5 or a sample hold circuit 6
Output to.

The sample and hold circuit 4 has an incremental signal A1, A2, B from the first channel CH1.
1 and B2 are temporarily held. Similarly, the sample and hold circuits 5 and 6 temporarily hold the four incremental signals from the second channel CH2 and the third channel CH3, respectively.

Upon receiving the channel selection signal C1 from the controller 8, the multiplexer 7 selects the first channel CH1 and the M-sequence data 70 from the first detector 50 or the second detector 51 of the first channel CH1. Is sent to the shift register 9, and at the same time, the incremental A-phase signal A2 and the B-phase signal B2 from the sample hold circuit 4 are sent to the 160 division circuit 13, and the incremental A-phase signal A1 and the B-phase signal B1 are divided into 16 division circuits. 1
Send to 2.

The multiplexer 7, when receiving the selection signal C2 or the selection signal C3 from the controller 8, receives the second channel CH2 or the third channel CH3.
Is selected and the M-sequence data 70 of the second channel CH2 or the third channel CH3 is sent to the shift register 9, and at the same time, the incremental A-phase signal A2 and B-phase signal B2 from the sample hold circuit 5 or the sample hold circuit 6 is 160 The signal is sent to the dividing circuit 13, and the incremental A-phase signal A1 and B-phase signal B1 are sent to the 16-dividing circuit 12.

Each channel CH1, CH2, C
The X / Y signal and the SCK signal are output to H3. The shift register 9 serially inputs the M series data 70 selected by the multiplexer 7, converts the M series data 70 into parallel data, and outputs the M series data 70 to the ROM table 10. This ROM table 10 converts parallel-converted M series data 70 into 14-bit binary data 71,
Output to the latch 11. The latch 11 temporarily holds the binary data 71 obtained by converting the M series data 70.

The 16-division circuit 12 has an interpolation means for dividing A1 and B1 of the selected channel into 16 parts, and converts A1 and B1 into 4-bit binary data 72. The converted binary data 72 is output to the phase adjustment circuit 14. The 160 division circuit 13 has an interpolation means for dividing A2 and B2 of the selected channel into 160, and A2 and B2 are converted into a rectangular wave 73 having a pitch of 16 μm per cycle and 8-bit binary data 74 of 160 bits. Convert to. Binary data 74 is latch 1
5, and the rectangular wave 73 is output to the phase adjustment circuit 14.

The phase adjusting circuit 14 receives the 4-bit binary data 72 output from the 16-division circuit 12 and simultaneously outputs a rectangular wave 73 from the 160-division circuit.
Enter. And 4-bit binary data 72
Phase and 160-bit 8-bit binary data 74
In order to match the phase of, the operation is performed using a rectangular wave 73 having a pitch of 16 μm and a 4-bit binary data 72, and a 160-bit 8-bit binary data 74 and a 3-bit binary data 75 in phase with each other. Is output to the latch 15.

Further, 3 calculated by the phase adjusting circuit 14
The MSB (2 ² ) of the bit binary data 75 is output to each channel as an X / Y signal for switching between the first detector 50 and the second detector 51 of each channel, so that the M sequence data 70 The phase and the 3-bit binary data 75 can be matched. This X /
The Y signal prevents the detector located on the boundary of the minimum reading unit from being used.

The latch 15 temporarily holds the binary data 75 output from the phase adjustment circuit 14 and the binary data 74 output from the 160 division circuit 13. The clock generator 17 includes a system clock signal CLK0 (hereinafter, C
LK0 signal) to the controller 8 and an SCK signal for timing the reading of the M-sequence data 70 to the AND gate 16, and the absolute position data 8
Output clock signal CLK1 (hereinafter referred to as CLK1 signal) for timing when outputting 5a, 85b, and 85c
Is output to the AND gate 18.

The AND gate 16 receives the SCK signal from the clock generator 17 and the sensor detection start command signal (hereinafter, detection signal) 81 from the controller 8. Only when the detection signal 81 is input from the controller 8, the SCK signal is output to the first detector 50 and the second detector 51 of each channel, and the shift register 9.

The AND gate 18 outputs the CLK1 signal from the clock generator 17 and the absolute position data output command signal (hereinafter, data output signal) 86 from the controller 8.
You have entered and. The CLK1 signal is output to each shift register 19, 20, 21 only when the data output signal 86 is input from the controller 8.

The controller 8 uses the channel selection signal C
1, C2, C3 to the multiplexer 7, the hold command signal 82 to the sample and hold circuits 4, 5 and 6, the detection signal 81 to the AND gate 16, the latch command signal 83 to the latches 11 and 15, and the data output signal 86. AND gate 1
It outputs to 8 respectively. Channel selection signal C1,
C2 and C3 are signals for selecting one channel, and the hold command signal 82 is the A signal from the third detector 52.
1 and B1 and A2 and B2 from the fourth detector 53 are held by the sample-hold circuits 4, 5, and 6 at the same time.

The detection signal 81 is a signal for detecting the M series pattern 60 by the first detector 50 or the second detector 51 switched by the X / Y signal. The latch command signal 83 is a signal for holding the 14-bit binary data 71 in the latch 11. Similarly, it is a signal for holding the 3-bit binary data 75, the 8-bit binary data 74, and the latch 15.

The data output signal 86 corresponds to the shift register 1
It is output to 9, 20, and 21, respectively, and the shift register 1
Absolute position data 85a, 8 stored in 9, 20, 21
This is a signal for simultaneously outputting 5b and 85c. Then, the controller 8 calculates the absolute position data 85a, 85b, which is not shown, by calculating the binary data 71, 74, 75 output from the latches 11, 15 into absolute position data 85a, 85b, 85c. ,
And an internal memory (not shown) for storing 85c.

The shift register 19 stores the absolute position data of the linear scale 1 output from the controller 8. Similarly, the shift register 20 stores the absolute position data of the linear scale 2 output from the controller 8, and The shift register 21 stores the absolute position data of the linear scale 3 output from the controller 8.

Then, when the data output signal 86 is output from the controller 8 to the AND gate 18, the absolute position data are simultaneously output by the CLK1 signal.
The operation of the absolute encoder configured as above will be described based on the flowchart of FIG.
First, initial setting for recognizing the absolute position data indicated by each of the linear scales 1, 2, and 3 when the power is turned on is performed.

The initial setting is step 501, step 5
02, step 503, step 504, step 50
5, step 506, step 507, step 50
8, step 509, step 510. [Step 501] When the power is turned on, the clock generator 17 operates, the CLK0 signal is output to the controller 8, and at the same time, the SCK signal is output to the AND gate 16 and the CLK1 signal is output to the AND gate 18. It [Step 502] The controller 8 outputs the channel selection signal C1 to the multiplexer 7 to select the first channel CH1. [Step 503] Next, when the detection signal 81 is output from the controller 8 to the AND gate 16, the AND gate 16 is opened.

When the AND gate 16 is opened, S
The CK signal and the X / Y signal for switching between the first detector 50 and the second detector 51 are passed through the multiplexer 7,
It is output to the first detector 50 or the second detector 51 that detects the M-sequence pattern 60. Then, a detector that is not on the boundary of the minimum reading unit (here, the first detector 50)
The M-series data 70 detected by is synchronized with the SCK signal,
Shift register 9 serially via multiplexer 7
Is output to.

The shift register 9 parallel-converts the M-series data 70, and the parallel-converted M-series data 70.
Is output to the ROM table 10. The parallel-converted M-sequence data 70 is converted into 14-bit binary data 71 in the ROM table 10. At the same time that the first detector 50 detects the M-series pattern 60, the third detector 52 detects the incremental pattern 61 and the fourth detector 53 detects the incremental pattern 62.

As a result, the third detector 52 has A1 and B
1 and the fourth detector 53 generates A2 and B2. Then, A1 and B1 are divided into 16-division circuit 12 via the sample hold circuit 4 and multiplexer 7.
And is converted into 4-bit binary data 72. Then, it is output to the phase adjustment circuit 14.

Further, A2 and B2 are 160 division circuits 1 through the sample hold circuit 4 and the multiplexer 7.
3 and is converted into a 16-adic 8-bit binary data 74 and a rectangular wave 73 having a period of 16 μm. The binary data 74 is output to the latch 15, and at the same time, the rectangular wave 73 is output to the phase adjustment circuit 14.

The operation of the phase adjustment circuit 14 is shown in the timing chart of FIG. (A) is a first detector 50 that detects the M-sequence pattern 60
2B is a rectangular wave, and (b) is a rectangular wave of the output signal of the second detector 51 that detects the M-sequence pattern 60. (C) represents A1 with a rectangular wave having a period of 128 μm.

(D) represents B1 by a rectangular wave having a period of 128 μm. (E) is a signal obtained by interpolating A1 and B1 into a binary signal. (F) is 16μ per cycle converted by the 160 division circuit 13.
It is a rectangular wave 73 of m. Then, using (e) and (f) and the calculation method according to Table 1, the phase of the M-sequence data 70, the phase of the 4-bit binary data 72, and the 8-bit binary data 74.
3-bit binary data 75 with the same phase as
Calculate (g).

[0038]

[Table 1]

A specific example of the calculation method is shown below. When the value of (e) is an even number 6 and (f) is Lo, the arithmetic expression uses (g) = [(e) -2] / 2. Therefore, (g) = [6-2] / 2 and (g) = 2.

(H) is the MSB (2 ² ) of (g),
It is an X / Y signal for switching between the first detector 50 and the second detector 51 for detecting the M-sequence pattern 60. (I) is a diagram in which (a) and (b) are switched by (h), and the M-sequence data 70 whose phases are matched is represented by a rectangular wave. (J) is 8-bit binary data 74 of 160-ary obtained by dividing A2 and B2 by the 160-dividing circuit 13.

Then, by combining (g), (i), and (j), absolute position data in units of 0.1 μm can be obtained. The 3-bit binary data 75 calculated by the phase adjustment circuit 14 is output to the latch 15. The latch 15 is 1 interpolated by the 160 division circuit 13.
The 60-ary binary data 74 and the 3-bit binary data 75 calculated by the phase adjustment circuit 14 are temporarily held by the latch command signal 83 from the controller 8.

The latch 11 temporarily holds the binary data 71 obtained by converting the M series data 70 in the ROM table 10 by the latch command signal 83 from the controller 8. The binary data 74 and 75 output to the latch 11 and the latch 15 are sequentially read by the controller 8. [Step 504] The binary data 74 and 75 are
After the arithmetic processing is performed in the controller 8 to obtain the absolute position data 85a in 0.1 μm units, the absolute position data 85a is stored in the internal memory for the first channel CH1 included in the controller 8.

Here, the absolute position data 85a (ABS)
Is calculated by the following equation (1). In addition, in order to make it easy to understand, the description will be given in decimal system. (ABS) = U + M + N (1) U = u × 2 ³ × 160 M = m × 160 N = n where u is the output value from the ROM table 10, m is the output value from the phase adjustment circuit 14, and n is 160 It is an output value from the division circuit 13.

As described above, the absolute position data 85a of the linear scale 1 of the first channel CH1 is calculated and stored in the internal memory of the controller 8. [Step 505] Next, the controller 8 outputs the channel selection signal C2 to the multiplexer 7 to select the second channel CH2. [Step 506] The same signal processing as in step 505 is performed, and each binary data is sequentially read by the controller 8. [Step 507] Each binary data is 0.1 μm
After the arithmetic processing is performed in the controller 8 so as to obtain the absolute position data 85b of the unit, the second
Absolute position data 8 in internal memory for channel CH2
5b is stored. [Step 508] Next, the controller 8 outputs the channel selection signal C3 to the multiplexer 7 to select the third channel CH3. [Step 509] The same signal processing as in steps 505 and 506 is performed, and each binary data is sequentially read by the controller 8. [Step 510] Each binary data is 0.1 μm
After the arithmetic processing is performed in the controller 8 to obtain the absolute position data 85c of the unit, the third value that the controller 8 has
Absolute position data 8 in the internal memory for channel CH3
5c is stored.

This completes the initial setting. [Step 511] After the initialization is completed, the process of simultaneously detecting the linear scales 1, 2, and 3 of all the channels CH1, CH2, and CH3 is started. A circuit for performing this processing is extracted in FIG.

In FIG. 5, the controller 8 outputs a hold command signal 82 to the sample and hold circuits 4, 5 and 6, and A1 generated by the third detector 52 of each channel.
B1 and A2 and B2 generated by the fourth detector 53 are held simultaneously. In other words, the positions indicated by the linear scales 1, 2, and 3 are simultaneously detected. [Step 512] Next, the controller 8 outputs the channel selection signal C1 to the multiplexer 7 to select the first channel CH1. [Step 513] Then, A2 and B2 held by the sample hold circuit 4 are output to the 160 division circuit 13, and at the same time, A1 and B2 held similarly are divided into 16 division circuit 12.
Output to.

A2 and B2 are 160 division circuits 1
In step 3, it is converted into 8-bit binary data 74 of 160 base and a rectangular wave 73 having a period of 16 μm. The binary data 74 is output to the latch 15 and at the same time, the rectangular wave 73
Is output to the phase adjustment circuit 14. Also, A1, B2
Is a 4-bit binary data 7 in the 16-division circuit 12.
It is converted to 2 and output to the phase adjustment circuit 14.

The phase adjustment circuit 14 is set to M as in the initial setting.
The serial data 70, the 4-bit binary data 72, and the 8-bit binary data 74 are converted into 3-bit binary data 75 having the same phase, and are output to the latch 15. The latch 15 temporarily holds the binary data 74 interpolated by the 160 division circuit 13 and the binary data 75 calculated by the phase adjustment circuit 14 by the latch command signal 83 from the controller 8.

Then, the binary data 74 and 75 held in the latch 15 are read by the controller 8.
The controller 8 outputs 3 from the phase adjustment circuit 14.
Using the binary data 75 of bits, the coefficient for correcting the position data u is obtained from the calculation table of Table 2.

[0050]

[Table 2]

[0051] In Table 2, a (m _t-1) is the output value of the phase adjustment circuit 14 before once stored in the internal memory of the controller 8 (the value of the binary data of 3 bits), (m _t ) Is the output value from the phase adjustment circuit 14 read by the controller 8 this time. However, the X mark in Table 2 indicates the overspeed.

The overspeed is a speed exceeding the allowable movement range of the linear scale. The allowable movement range of the linear scale in the present invention is as shown in (g) of FIG.
For example, if the position currently indicated by the linear scale is number 1,
The range between the third number 6 on the left and the third number 4 on the right is shown. If the speed exceeds the range, detection cannot be performed.

Using (m _t ) and (m _t-1 ) and assuming that the value obtained from Table 2 is k, absolute position data (ABS _t ) can be obtained from the following equation (2). (ABS _t ) = U _t + M _t + N _t (2) U _t = U _t-1 + k M _t = m _t × 160 N _t = n _t However, U _t is a value obtained by calculation, and U _{t- 1} is the absolute position data stored in the internal memory. n _t
Is an output value from the 160 division circuit 13.

For example, if X _t = ₁ = 1 and X _t = 7, then k = −1 from Table 2. Therefore, U _t = U _t-1 −1 and (ABS _t ) = [(U _t−1 −1) × 2 ³ × 160] + m _t × 160 + n _t , and the absolute position data 87a of this time is obtained. [Step 514] The controller 8 newly stores the absolute position data 87a in the internal memory and outputs the absolute position data 87a to the shift register 19.

The shift register 19 stores the absolute position data 87a until the CLK1 signal is output from the AND gate 18. [Step 515] Next, the controller 8 outputs the channel selection signal C2 to the multiplexer 7 to select the second channel CH2. [Step 516] The same signal processing as in step 513 is performed to obtain absolute position data 87b. [Step 517] The controller 8 newly stores the absolute position data 87b in the internal memory and outputs the absolute position data 87b to the shift register 20.

The shift register 20 stores the absolute position data 87b until the CLK1 signal is output from the AND gate 18. [Step 518] Next, the controller 8 outputs the channel selection signal C3 to the multiplexer 7 to select the third channel CH3. [Step 519] The same signal processing as in steps 513 and 516 is performed to obtain absolute position data 87c. [Step 520] The controller 8 newly stores the absolute position data 87c in the internal memory and outputs the absolute position data 87c to the shift register 21.

The shift register 21 stores the absolute position data 87c until the CLK1 signal is output from the AND gate 18. [Step 521] Above, the three linear scales 1,
After a few absolute position data 87a, 87b, 87c are stored in the shift registers 19, 20, 21 respectively, the controller 8 outputs a signal 86 to the AND gate 18,
Open the AND gate 18.

The shift registers 19, 20, and 21 are
The absolute position data 87a, 87b, 87c are sequentially output in synchronization with the signal CLK1 output from the D gate 18. Then, after the absolute position data 87a, 87b, 87c of each linear scale 1, 2, 3 is output, the controller 8 closes the AND gate 18 and releases the hold state of each sample hold circuit 4, 5, 6. Return to sample mode.

The controller 8 waits for the acquisition time of the sample hold circuit (the time until the output is settled within the tolerance of the final value when switching to the sample mode). Then, by repeating steps 511 to 521, absolute position data can be obtained one after another.

Here, in order not to exceed the allowable movement range, the following relational expression should be satisfied. T <{[(a / 2) -1] / a} × (λ / V _MAX ), where T is the read cycle, V _MAX is the maximum speed of the linear scale, and λ is rough when there are multiple incremental patterns. The pitch of the incremental signal when the incremental pattern is detected, and a is the number of divisions of the incremental signal when the coarse incremental pattern is detected.

Further, the M-sequence data 70 is converted to 14
The bit number of bit binary data changes depending on the length of the linear scale, and the length of the linear scale in this embodiment is 128 μm × (2 ¹⁴ −1) .2.
097024 m (where 128 μm is the minimum reading unit of the M-series pattern, and is a multiplier of 14 is the number of bits of binary data converted from the M-series data).

Further, the controller 8 may be a CPU. Further, not only the absolute position data is stored, but also an internal memory capable of simultaneously storing the binary data may be provided. Further, in this embodiment, 1
Although the incremental pattern of 6 μm pitch is divided into 160 to obtain absolute position data in 0.1 μm units, the size of the unit is not limited to this. This is because the size of the unit can be changed according to the number of divisions of the division circuit (for example, in the case of an incremental pattern with a pitch of 16 μm, if 16 divisions, absolute position data in units of 1 μm).

Further, the incremental pattern in this embodiment is a pattern having a pitch of 16 μm and a pattern having a pitch of 128 μm, but a pattern having a pitch other than this may be used. In other words, when the pitch size of the coarse incremental pattern is α and the pitch size of the thin incremental pattern is β, the pitch size may be such that α / β becomes a positive real number other than 2. .. However, when the minimum reading unit of the absolute pattern is γ, α = γ.

In this embodiment, the M series is used as the absolute pattern, but the absolute pattern is not limited to this. Further, instead of the absolute pattern, a backup type absolute encoder provided with a counter that counts the pulses of the incremental pattern and a battery that backs up the counter when the power of the device is turned off may be used. This embodiment will be described below as a second embodiment.

The absolute encoder in the second embodiment has a first channel CH1 and a second channel CH.
2 and a third channel CH3. The first channel CH1 is a linear scale 1
01, an incremental pattern is formed on the linear scale 101.

Further, the first channel CH1 has a detector 116 that moves relative to the linear scale 101 to read an incremental pattern, a counter 113 that counts an incremental signal, and a battery 110 that backs up the counter 113. .. Then, the detector 116 included in the first channel CH1 outputs the incremental A-phase signal and the B-phase signal (hereinafter, incremental signal 210) detected by the detector 116 to the sample hold circuit 104.

Similarly, the second channel CH2 having the linear scale 102 and the third channel CH3 having the linear scale 103 have the same structure as the first channel CH1. The second channel CH2 and the third channel CH3 include linear scales 102 and 103 having an incremental pattern and a linear scale 1
02 and 103, and detectors 117 and 118 that read an incremental pattern and counters 114 and 115 that count an incremental signal, and a counter 1.
It is composed of batteries 111 and 112 for backing up the batteries 14 and 115.

Then, the detector 117 of the second channel CH2 outputs the incremental A-phase signal and the B-phase signal (hereinafter, incremental signal 211) detected by the detector 117 to the sample hold circuit 105, and the third
The detector 118 included in the channel CH3 is the detector 11
The incremental signals A and B detected by 8 (hereinafter, incremental signal 212) are output to the sample hold circuit 106.

The sample and hold circuit 104 temporarily holds the incremental signal 210 output from the detector 116 of the first channel CH1. Similarly, the sample and hold circuit 105 controls the incremental signal 21 output from the detector 117 of the second channel CH2.
1 for temporarily holding the sample hold circuit 1
06 temporarily holds the incremental signal 212 output from the detector 118 of the third channel CH3.

The multiplexer 107 is the controller 1
When receiving the channel selection signal C1 from 08,
The channel CH1 is selected, the counter 113 of the first channel CH1 is connected to the shift register 109, and at the same time, the sample hold circuit 104 is connected to the multi-division circuit 119. Also, the multiplexer 107 receives the channel selection signal C2 or the channel selection signal C3 from the controller 8 and then receives the second channel CH2 or the third channel CH2.
The channel CH3 is selected, the counter 114 or 115 of the second channel CH2 or the third channel CH3 is connected to the shift register 109, and at the same time, the sample hold circuit 105 or 106 is connected to the multi-division circuit 119.

Further, when the multiplexer 107 receives the channel selection signal C3 from the controller 8,
Select the third channel CH3, then select the third channel CH3
The counter 115 is connected to the shift register 109, and at the same time, the sample hold circuit 106 is connected to the multi-division circuit 11.
Connect to 9. The shift register 109 converts the serial counter value 204 into the upper m-bit binary data 20.
It is converted to 5.

The multi-division circuit 119 converts the incremental signal of the channel selected by the channel selection signal into binary data 208 of lower n bits. The latch 120 temporarily holds the lower n bits of binary data 208 output from the multi-division circuit 119. The clock generator 121 includes a system clock signal CLK0 (hereinafter, CLK) which is a basic signal of the entire device.
0 signal) is output to the controller 108, and the CLK1 signal for timing the absolute position data is output.
Output to the ND gate 123.

The controller 108 sends the channel selection signals C1, C2, C3 to the multiplexer 107 and the hold command signal 200 to the sample and hold circuits 104, 10 respectively.
5 and 106, the counter value transmission request signal (hereinafter, REQ
Signal) 201 to each counter 113, 114, 115,
Absolute position data output command signal (hereinafter, data output signal)
202 to AND gate 123 and latch command signal 203
Are output to the latch 120, respectively.

Then, the controller 108 uses the latch 1
Lower n bits of binary data 2 output from 20
08 and the upper m-bit binary data 205 to have absolute position data 132a, 132b, 132c, which are not shown, and an internal memory (not shown) that stores the absolute position data of the operation result. There is. The shift register 124 stores the absolute position data of the linear scale 101 output from the controller 108, and similarly, the shift register 125 stores the absolute position data of the linear scale 102 output from the controller 108. 21 is a controller 108
The absolute position data of the linear scale 3 output from is stored.

When the data output signal 202 is output from the controller 108 to the AND gate 123, C
The absolute position data are simultaneously output by the LK1 signal. The operation of the battery backup type encoder configured as described above will be described. First, initial setting for recognizing the absolute position data indicated by each of the linear scales 101, 102 and 103 is performed when the power is turned on.

When the power is turned on, the clock generator 121 operates, the CLK0 signal is output to the controller 108, and at the same time, the CLK1 signal is input to the AND gate 12.
3 is output. The controller 108 outputs the channel selection signal C1 to the multiplexer 107 and selects the first channel CH1.

Then, the count value counted by the counter 113 is output to the shift register 109, and at the same time, the incremental signal 210 is output to the multi-division circuit 119 via the sample hold circuit 104. The incremental signal 210 is converted into binary data 208 of lower n bits by the multi-division circuit 119 and then temporarily held in the latch 120.

The count value is stored in the shift register 109 as the upper m bits.
It is converted into bit binary data 205 and read by the controller 108. The lower n-bit binary data 208 output to the latch 120 and the upper m-bit binary data 205 whose count value has been read in advance by the controller 8 have been processed into absolute position data 132a. After that, the absolute position data 132a is stored in the internal memory (not shown) for the first channel CH1 of the controller 108.

As described above, the absolute position data 132a of the linear scale 101 included in the first channel CH1 is stored in the internal memory of the controller 108, but the absolute position data 132b of the linear scale 102 included in the second channel CH2 and the third channel CH3. The same processing is performed on the absolute position data 132c of the linear scale 103 included in the controller 108, and the initial absolute position data 132a, 132b, 132c of each linear scale is stored in the internal memory of the controller 108.

After the initial setting is completed, the process of simultaneously detecting the linear scales of all the channels is started. Incremental signals of all channels are used for each sample and hold circuit 10
4, 105 and 106 are held simultaneously. Next, the controller 108 outputs the channel selection signal C1 to the multiplexer 107, and the first channel CH1
Select. Then, the incremental signal 210 held by the sample hold circuit 104 is converted into the multi-division circuit 119.
Output to.

The multi-division circuit 119 interpolates the incremental signal 210 into the lower n bits of binary data 208 and outputs it to the latch 120. Then, the controller 108 outputs the latch command signal 203 to the latch 120 and reads the lower n bits of binary data 208. As in the first embodiment, the upper m-bit binary data 205 is the lower n-bit binary data 203 read this time, the lower n-bit binary data 203 'stored in the internal memory, and the internal memory. The count value of the counter stored in is calculated from the converted upper m-bit binary data 205 'to obtain absolute position data 133a.

After the calculation, the absolute position data 133a is output to the shift register 124, and the shift register 124
Is stored until the CLK1 signal is output. Next, the controller 108 outputs a channel selection signal C2 for selecting the second channel CH2 to the multiplexer 107. Then, the same processing as the processing for obtaining the absolute position data 133a of the linear scale 101 is performed to obtain the absolute position data 133b indicated by the linear scale 102,
Output to the shift register 125.

Next, the controller 108 outputs a channel selection signal C3 for selecting the third channel CH3 to the multiplexer 107, and absolute position data 133a, 133 of the linear scale 101 and the linear scale 102.
The same processing as that for obtaining b is performed to obtain the absolute position data 133c indicated by the linear scale 103, and the absolute position data 133c is output to the shift register 126.

Above, the three linear scales 101, 10
2, 103 absolute position data 133a, 133b, 13
After 3c has been stored in each shift register 124, 125, 126, the controller 108 outputs the data output signal 13
1 is output to the AND gate 123, and the AND gate 123
open. The AND gate 123 outputs the CLK1 signal output from the clock generator 121 to each shift register 124, 125, 126, and each absolute position data 1
33a, 133b, 133c are output to the outside in synchronization with the CLK1 signal.

Although a linear scale has been described in the present invention, a rotary encoder may be used.
In addition, the output of absolute position data was provided with a shift register for each linear scale of each channel, but with one shift register, each channel information (2 bits for 3 channels) is added, and 3 channels worth of data are added. You may output to an external circuit (numerical control apparatus etc.) with one signal line.

[0086]

As described above, according to the present invention, holding means for holding simultaneously the detection signals of the patterns of N code plates,
Since the signal selecting means capable of sequentially selecting the held detection signals is provided, the patterns of N code plates can be detected at the same time and can be processed by one signal processing unit. Therefore, for N code plates and N detectors, it is possible to obtain absolute position data at the same time even if there is only one signal processing unit.

Even if this absolute encoder is attached to a numerical control device such as an NC machine tool, a desired machined surface can be obtained without forming recesses or grooves on the machined surface.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a linear scale and a detector according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the first embodiment.

FIG. 4 is a timing chart of the phase adjustment circuit of the first embodiment.

FIG. 5 is a diagram showing processing after initial setting in the first embodiment of the present invention.

FIG. 6 is a diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 1, 2, 3 Linear scale 4, 5, 6 Sample and hold circuit 7 Multiplexer 8 Controller 9 Shift register 10 ROM table 11, 15 Latch 12 16 Dividing circuit 13 160 Dividing circuit 14 Phase adjusting circuit 16, 18 AND gate 19, 20, 21 shift register 50 first detector 51 second detector 52 third detector 53 fourth detector 101, 102, 103 linear scale 110, 111, 112 battery 113, 114, 115 counter

Claims (1)

[Claims] 1. N (where N is an integer of 2 or more) code plates on which an absolute pattern and an incremental pattern are respectively formed, and relative movement with respect to each of the N code plates to detect the absolute pattern. N absolute detection means, N incremental detection means that move relative to the N code plates to detect the incremental pattern, and incremental detection means detected by the N incremental detection means, respectively. The same code is selected from N holding means for simultaneously holding signals, the incremental signal held by each of the N holding means, and the absolute signal detected by each of the N absolute detecting means. The ink detected from each of the plates A signal selection unit that sequentially selects a combination of a incremental signal and the absolute signal, a signal processing unit that converts the incremental signal and the absolute signal selected by the signal selection unit into a signal indicating an absolute position, and the signal. An absolute encoder, comprising: an output unit that outputs the signal indicating the absolute position converted by the processing unit substantially at the same time.