JPH0527176B2 - - Google Patents

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for automatically determining the recording speed of a magnetic tape in a magnetic recording/reproducing apparatus such as a video tape recorder. 2. Prior Art A typical example of a magnetic recording and reproducing device is a home video tape recorder, but many of the latest products are designed so that the running speed of the magnetic tape can be selected from two or more speeds during recording and reproducing. ing. Taking a VHS video tape recorder with NTSC (television system used in Japan and the United States) as an example, the running speed of the magnetic tape is Standard Play (hereinafter abbreviated as SP). 3. Long play (hereinafter abbreviated as LP) with 1/2 running speed and super long play (hereinafter abbreviated as SLP) with 1/3 running speed.
There are streets, but when playing back, it is determined which of these driving speeds was recorded.
It is necessary to perform playback at the same running speed as the running speed at the time of recording. As a method for determining the running speed during recording during playback, Japanese Patent Application Laid-Open No. 56-37856 (hereinafter referred to as Document 1) proposes a method for running a magnetic tape during one period of a control signal recorded on the magnetic tape. A device has been proposed that determines whether it is SP or LP based on how many times the leading edge of a capstan rotation detection signal arrives. By the way, the frequency of the regeneration control signal is usually much lower than that of the capstan's rotation detection signal.For example, a frequency generator that generates an output signal of 357 pulses per rotation is
Assuming that it is attached to a 3.5mm capstan, when a tape recorded in SP mode is played back in SP mode, the frequency of the playback control signal is 30Hz, while the frequency of the capstan's rotation detection signal is 1080Hz. becomes. Furthermore, when a tape recorded in LP mode is played back in SP mode, the frequency of the playback control signal is 60Hz, and when a tape recorded in SLP mode is played back in SP mode, the frequency of the playback control signal is 90Hz. Note that the ratio of the frequency of the capstan rotation detection signal and the frequency of the reproduction control signal does not change even if the running speed during reproduction is changed.
is shown. Now, when determining the traveling speed during recording in three ways using the method shown in Document 1, the leading edge of the 1080 Hz capstan rotation detection signal is detected during one period of the 60 Hz playback control signal.
Since the leading edge of the capstan rotation detection signal arrives 18 times, the counter for determining the frequency ratio of both signals must be able to count the leading edge of the capstan rotation detection signal up to at least 19, thereby increasing the number of bits of the counter to 5 bits (2 ⁵ -1=31) is required. Hereinafter, an example of a magnetic tape recording speed determination device to which the above-described conventional technique is applied will be described with reference to the drawings. FIG. 4 shows a magnetic tape recording speed discrimination device shown in the above-mentioned document 1 with an added function to discriminate between three recording speeds. In order to make three determinations by the only 5-bit counter 3, which is supplied with a detection signal and a playback control signal which is applied to input terminal 2 as a reset signal, it is necessary to A digital comparator 4 is required to compare the count value during one cycle of the reproduction control signal and a preset threshold value. In Fig. 4, 12 threshold values are prepared in decimal notation, and on the other hand, the configuration is such that the counting operation is stopped when the count value of counter 3 reaches 24.
Essentially, there are two types of thresholds, 12 and 24. Therefore, if the count value of the counter 3 is smaller than 12, it is determined that the mode is SLP mode, if it is larger than 24, it is determined that the mode is SP mode, and in other cases, it can be determined that the mode is LP mode. Note that the D flip-flop 5 is provided to hold the output of the digital comparator 4 until the next determination, and is provided at output terminals 6, 7, 8.
becomes active (logic "1") when the determination results are SP, LP, and SLP, respectively. Problems to be Solved by the Invention As described above, when trying to discriminate between the three tape running speeds using the conventional technology, there was a problem in that the circuit configuration became quite complicated. Of course, if two sets of counters are used, the digital comparator 5 is no longer necessary, but the circuit scale becomes even larger. In view of these problems, the present invention provides a magnetic tape recording speed determination device with a simple circuit configuration. Means for Solving the Problems In order to solve the above problems, the magnetic tape recording speed determination device of the present invention converts the output signal from the frequency generator connected to the capstan motor into the frequency of the reproduction control signal. The output signal and the reproduction control signal are directly compared in frequency by a frequency comparator. The feature is that two sets of vessels are prepared. Effects According to the present invention, with the above-described configuration, it is possible to determine the running speed with a circuit scale smaller than that of the conventional one. Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit diagram of a magnetic tape recording speed determination device according to an embodiment of the present invention. In Figure 1, input terminal 1 is connected to a 1/14 frequency generator (not shown) connected to a capstan motor (not shown) for running the magnetic tape. The first to perform frequency division
The output of the first frequency divider 9 is connected to the input terminal of a second frequency divider 10 that divides the frequency by 1/2, The output of the frequency divider 10 is supplied to one input terminal of a first frequency comparator 11, and the output of the frequency divider 9 is supplied to one input terminal of a second frequency comparator 12. On the other hand, first and second frequency comparators 11 and 12 are connected to an input terminal 2 to which a reproduction control signal output from a control signal detecting means (not shown) for detecting a control signal recorded on a magnetic tape is supplied. The other input terminal of is connected. Also, the first and second frequency comparators 11
The set terminals of RS flip-flops 13 and 14 are connected to the output terminals of RS flip-flops 13 and 14, respectively, and the first and second input terminals of coincidence detection circuits 15 and 16 are connected to the output terminals of RS flip-flops 13 and 14, respectively. The reset terminals of the RS flip-flops 13 and 14 are connected to the output terminal of the circuit 15, and the set terminals of the RS flip-flops 17 and 18 are connected to the first and second output terminals of the second frequency comparator 12, respectively. , the output terminals of the RS flip-flops 17 and 18 are connected to the first and second input terminals of the coincidence detection circuits 19 and 20, respectively.
The output terminal of the RS flip-flop 17,
Eighteen reset terminals are connected. Furthermore, one input terminal of a NAND gate 21 is connected to the first output terminal of the coincidence detection circuit 16, and the other input terminal of the NAND gate 21 is connected to the first output terminal of the coincidence detection circuit 16.
The output terminal is connected to the first output terminal of the frequency comparator 11, and the set terminal of the RS flip-flop 22 is connected to the output terminal.
One input terminal of a NAND gate 23 is connected to the output terminal of the RS flip-flop, and the other input terminal of the NAND gate 23 is connected to the first output terminal of the first frequency comparator 11 via an inverter 24. The reset terminal 22 is connected to the second output terminal of the first frequency comparator 11.
Further, first and second input terminals of a NAND gate 25 are connected to the second output terminal of the coincidence detection circuit 16 and the first output terminal of the coincidence detection circuit 20,
The third input terminal of the NAND gate 25 is connected to the second output terminal of the first frequency comparator 11, the set terminal of the RS flip-flop 26 is connected to the output terminal, and the output terminal of the RS flip-flop 26 is connected to the second output terminal of the first frequency comparator 11. One input terminal of the gate 27 is connected, the other input terminal of the NAND gate 27 is connected to the second output terminal of the frequency comparator 11 via an inverter 28, and the reset terminal of the RS flip-flop 22 is connected to the second output terminal of the AND gate 29. One input terminal of the AND gate 29 is connected to the first output terminal of the first frequency comparator 11, and the other input terminal is connected to the second output terminal of the second frequency comparator 12. It is connected to the. One input terminal of a NAND gate 30 is connected to the second output terminal of the coincidence detection circuit 20, and the other input terminal of the NAND gate 30 is connected to the second output terminal of the second frequency comparator 1.
The output terminal is connected to the second output terminal of 2.
The set terminal of RS flip-flop 31 is connected, and the output terminal of RS flip-flop 31 is connected to
One input terminal of the NAND gate 32 is connected,
The other input terminal of the NAND gate 32 is connected to the second output terminal of the second frequency comparator 12 via an inverter 33, and the other input terminal of the NAND gate 32 is connected to the second output terminal of the second frequency comparator 12.
The reset terminal of the second frequency comparator 12
is connected to the output terminal of the NAND gate 2
The set terminal of an RS flip-flop 34 and one input terminal of an AND gate 35 are connected to the output terminal of the NAND gate 32, and the output terminal of the NAND gate 32 is connected to an RS
The set terminal of flip-flop 36 and one input terminal of AND gate 37 are connected, and the other input terminals of AND gates 35 and 37 are both connected.
The output terminal of the NAND gate 23 is connected, the output terminal 7 for LP and one input terminal of the NOR gate 38 are connected to the output terminal of the RS flip-flop 34, and the output terminal of the RS flip-flop 36 is connected to the output terminal of the RS flip-flop 34.
The output terminal 8 for SLP is connected to the other input terminal of the NOR gate 38, and the output terminal 6 for SP is connected to the output terminal of the NOR gate 38. By the way, the first frequency comparator 11 in FIG.
A frequency discrimination block 100 composed of RS flip-flops 13, 14, coincidence detection circuits 15, 16, a second frequency comparator 12, RS flip-flops 17, 18, coincidence detection circuits 19, 2
Frequency discrimination block 200 configured by 0
have the same configuration, but before explaining the operation of the magnetic tape recording speed determination device shown in FIG.
A concrete logical configuration diagram of this frequency discrimination block 100 is shown in FIG. 2, and its operation will be briefly explained based on the timing chart of the main part shown in FIG. In FIG. 2, a first RS flip-flop includes a NAND gate 51 and a NAND gate 52 whose first input terminal and output terminal are cross-coupled with each other, and a NAND gate 5 having a similar configuration.
3 and a second RS flip-flop by a NAND gate 54, and when the output of the first RS flip-flop is transmitted to the second RS flip-flop after the trailing edge of the input signal arrives, a NAND gate 55 and a NAND gate 56 are connected.
, an inverter 57 and a NAND gate 58 that detect a coincidence between the output of the NAND gate 53 and one input signal, and an inverter 59 and a NAND gate 58 that detect a coincidence between the output of the NAND gate 54 and the other input signal.
The NAND gate 60 constitutes a frequency comparator. In addition, a NAND gate 61 whose first input terminal and output terminal are cross-coupled with each other and
The NAND gate 62 constitutes a third RS flip-flop, and the similarly configured NAND gates 63 and 64 constitute a fourth RS flip-flop. It is the same as 13 and 14. On the other hand, by the output of the NAND gate 65, whose first and second input terminals are supplied with the outputs of the NAND gates 61 and 63, and whose third and fourth input terminals are supplied with the outputs of the NAND gates 58 and 60, The third and fourth RS flip-flops are configured to be reset. Furthermore, this NAND gate 6
5 is the same as the coincidence detection circuit 15 in FIG. Furthermore, the first and second input terminals of an AND gate 66 are connected to the output terminals of the NAND gates 61 and 64, respectively, and the first discrimination output terminal 67 is connected to the output terminal of the AND gate 66.
First and second input terminals of an AND gate 68 are connected to the output terminals of the gates 62 and 63, respectively,
A second discrimination output terminal 69 is connected to the output terminal of the AND gate 68;
Reference numeral 68 constitutes the coincidence detection circuit 16 of FIG. Note that the first input terminal 70 is supplied with the output signal of the frequency divider 9 shown in FIG. 1, and the second input terminal 71 is connected to the input terminal 2 shown in FIG. 3A and 3B show pulse signals supplied to input terminals 70 and 71, and FIG.
is the output signal of the second frequency divider 10 in FIG.
FIG. 3B shows the reproduction control signal. FIGS. 3C and 3D show the NAND gate 51 and
3E and F show the output signal waveforms of the NAND gate 55 and NAND gate 56, respectively, and FIGS. 3G and H show the output signal waveforms of the NAND gate 52, respectively. 53 and NAND gate 54
Figures I and J show the output signal waveforms of the NAND gates 58 and 58, respectively.
3 shows the output signal waveform of the NAND gate 60, FIG. 3 K and L show the output signal waveforms of the NAND gate 61 and NAND gate 62, respectively, and FIG. 3 M and N show the output signal waveforms of the NAND gate 61 and NAND gate 62, respectively.
Figure 3 O shows the output signal waveform of the NAND gates 64 and 63, and Figure 3 P, Q shows the output signal waveform of the NAND gate 65.
show the output signal waveforms of AND gates 66 and 68, respectively. As is clear from Figure 3, the
The first RS flip-flop formed by the NAND gates 51 and 52 receives the leading edge of each input pulse signal while negative direction pulses are alternately supplied to the first input terminal 70 and the second input terminal 71. invert its output state for each
NAND gates 55 and 56 change the output state of the first RS flip-flop into a NAND gate every time the trailing edge of the input pulse signal arrives.
The signal is transmitted to the second RS flip-flop through gates 53 and 54, as at time _t1 in FIG.
The repetition frequency of the pulse signal supplied to the second input terminal becomes higher than that of the first input terminal, and the repetition frequency of the pulse signal supplied to the second input terminal becomes higher than that of the pulse signal supplied to the first input terminal from one leading edge to the next leading edge. When the leading edge of the pulse signal supplied to the second input terminal arrives twice,
The second frequency comparator via NAND gate 60
The same pulse signal as the input pulse signal is sent to the output terminal 73 of. As a result, the output state of the fourth RS flip-flop formed by the NAND gate 63 and the NAND gate 64 is inverted once, but before that, the output level of the NAND gate 61 becomes "1".
In other words, before the frequency of the pulse signal supplied to the second input terminal 71 becomes higher than that of the first input terminal, the frequency of the pulse signal supplied to the first input terminal 71 becomes higher than that of the first input terminal. If the frequency has become higher, the output level of the NAND gate 61 has become "1", and the trailing edge of the pulse signal that caused the output level of the NAND gate 63 to shift to "1" has arrived. sometimes
The output level of the NAND gate 65 shifts to "0" and resets the third RS flip-flop and the fourth RS flip-flop by the NAND gates 61 and 62, so that the output state of the fourth RS flip-flop returns to the original state again. . Said fourth
_The output state of the RS flip-flop is not temporarily but completely reversed at time _t2 in FIG. This is when the leading edge of the pulse signal arrives twice in succession. Therefore, the frequency determination block shown in FIG. from a state in which the level of is "1" and the level of the second output terminal is "0", a state in which it is determined that the frequency of the pulse signal supplied to the first input terminal is lower than that of the second input terminal That is, in order for the level of the first output terminal to be "0" and the level of the second output terminal to be "1", the same determination result must be obtained at least twice in a row, By this,
Even when the playback control signal is temporarily dropped or emphasized as described above, the risk of malfunction is extremely reduced. In the magnetic tape recording speed determination device shown in Figure 1, in order to obtain even higher reliability, either the playback control signal is dropped three times in a row, or the frequency comparator sends out the same determination result three times in a row. The system is configured so that the determination output of the device is not changed unless the device is changed, and this pattern will be explained below along with an explanation of the overall operation of the device shown in FIG. First, in the NTSC specification, the running speed of the magnetic tape is 33.35 mm/sec in the SP state, 16.67 mm/sec in the LP state, and 11.12 mm/sec in the SLP state.
sec. If the shaft diameter of the capstan is 3.51 mm, taking into account the thickness of the magnetic tape, the rotational speed of the capstan motor is 3.024 rps, 1.512 rps, and 1.512 rps, respectively.
1.008rps, and the frequency generator connected to the capstan motor generates an output signal of 357 cycles per rotation, and the output frequency of the frequency generator at each running speed is approximately 1080Hz, 540Hz,
It becomes 360Hz. Also, considering that control signals are recorded at a frequency of 30 Hz at each running speed, it is possible to convert a magnetic tape recorded in the SP state, LP state, and SLP state to the SP state.
When reproduced in the LP state and SLP state, the frequency f1 of the signal appearing at input terminal 1 in FIG. 1, the frequency f2 of the signal appearing at input terminal 2, and the output frequencies f9 and f10 of the frequency dividers 9 and 10. The relationship is as shown in the table below. In addition, in the table below, the unit of frequency is Hz.

[Table] In FIG. 1, a NAND gate 25, an RS flip-flop 26, a NAND gate 27, an inverter 28, an AND gate 29, an RS flip-flop 34, and an AND gate 37 form a master-slave type D flip-flop.
The RS flip-flop 26 is a master cell, and the RS flip-flop 34 is a slave cell. Also, a NAND gate 30, an RS flip-flop 31, a NAND gate 32, an inverter 33,
The RS flip-flop 36 and the AND gate 35 also form another master-slave type D flip-flop, with the RS flip-flop 31 serving as a master cell and the RS flip-flop 26 serving as a slave cell. Furthermore, NAND gate 21, RS
Flip-flop 22, NAND gate 23, and inverter 24 form a master portion of a master-slave type D flip-flop, but the slave portion is omitted. These D flip-flop circuits are added for the purpose of providing further redundancy to the discrimination results obtained by the first frequency discrimination block 100 and the second frequency discrimination block. For example, if a magnetic tape recorded in SP state is
When playing in the state, the second frequency divider 10
Since the output frequency of is higher than the frequency of the reproduction control signal, the coincidence detection circuits 16 and 2
The levels of the first output terminals of the frequency comparators 11 and 12 both become "1", and pulse signals are periodically supplied from the first output terminals of the frequency comparators 11 and 12.
While the RS flip-flops 26 and 31 continue to be reset, the RS flip-flops 26 and 31 are
Since the flip-flops 34 and 36 also continue to be reset, the output level of the NOR gate 38 remains "1".
Therefore, the determination result by the device shown in Figure 1 is SP state, but even if it is the same magnetic tape, when it comes to the part recorded in LP state, the frequency of the playback control signal becomes twice as high as 60Hz. A pulse signal is now supplied from the second output terminal of the frequency comparator 11, and after the detection operation at time _t1 in FIG. 3 has been performed twice, that is, the detection at time _t2 in FIG. After the operation, the level of the second output terminal of the coincidence detection circuit 16 shifts to "1".
An RS flip-flop 26 is set by the NAND gate 25. When a pulse signal is further supplied from the second output terminal of the first frequency comparator 11, the RS flip-flop 34 is set by the NAND gate 27, so that the determination result is
It becomes LP state. In this way, the magnetic tape recording speed determination device shown in FIG. Results first
frequency comparator 11 or second frequency comparator 12 needs to send out the signal. Therefore, it is possible to perform extremely redundant determination even when the reproduction control signal is temporarily dropped or emphasized. Effects of the Invention As described above, the magnetic tape recording speed determination device of the present invention includes a control signal detecting means for detecting a control signal recorded on a magnetic tape and outputting a reproduction control signal, and a a first frequency generator for dividing an output signal from a frequency generator connected to a capstan motor to a frequency close to the frequency of the reproduction control signal;
frequency divider 9 and the output signal of the first frequency divider to 2
a second frequency divider 10 that divides the frequency by a factor of 1/2; a first frequency comparator 11 that compares the frequency of the reproduction control signal and the output signal of the second frequency divider; signal and said first
a second frequency comparator 12 that compares the frequencies of the output signals of the frequency divider 9; and a first memory means (RS flip-flops 13 and 14 in the embodiment) that holds the comparison results of the first frequency comparator. The first memory means is constituted by) and
a second memory means (in the embodiment, the second memory means is constituted by RS flip-flops 17 and 18) for holding the comparison result by the second frequency comparator; and the first memory means. From the output state of the second memory means, it is determined whether the recording speed of the magnetic tape is high speed (explained as SP state in the embodiment), medium speed (explained as LP state in the embodiment), or low speed. (In the example
Explained as SLP condition. ) (In the embodiment, the determining means is constituted by a coincidence detection circuit 16 and a coincidence detection circuit 20.) Considering that the circuit scale of the frequency discrimination blocks 100 and 200 is equivalent to approximately two master-slave type D flip-flops,
A device can be constructed with eight D flip-flops and a frequency divider 9 and a frequency divider 10, and since the frequency divider 9 is not reset by an external signal, it is often used to control the servo of a capstan motor. It can be shared with other blocks such as systems. Therefore, despite the extremely simple circuit configuration, it is possible to perform discrimination with higher reliability than ever before, resulting in a great effect.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a magnetic tape recording speed determination device according to an embodiment of the present invention, and FIG.
A concrete logical configuration diagram of the frequency discrimination block shown in the figure,
FIG. 3 is an operational waveform diagram of each part of the device, and FIG. 4 is a circuit diagram of a conventional magnetic tape recording speed determination device. 9...first frequency divider, 10...second frequency divider,
DESCRIPTION OF SYMBOLS 11...First frequency comparator, 12...Second frequency comparator, 13, 14, 16, 18...RS flip-flop, 16...Coincidence detection circuit (constituting discriminating means), 20...Coincidence detection circuit (constituting the determining means).

Claims (1)

[Claims] 1 A control signal detection means for detecting a control signal recorded on a magnetic tape and outputting a reproduction control signal; and a control signal detection means for detecting a control signal recorded on a magnetic tape and outputting a reproduction control signal; and reproduction of an output signal from a frequency generator connected to a capstan motor for running the magnetic tape. a first frequency divider that divides the frequency close to the frequency of the control signal; a second frequency divider that divides the output signal of the first frequency divider to half the frequency; and a second frequency divider that divides the frequency of the output signal of the first frequency divider to a half frequency; and a first frequency comparator that compares the frequency of the output signal of the second frequency divider, and a second frequency comparator that compares the frequency of the reproduction control signal and the output signal of the first frequency divider. a comparator, and a first frequency comparator that holds the comparison result of the first frequency comparator.
, a second memory means for holding the comparison result by the second frequency comparator, and the output states of the first memory means and the second memory means indicate that the recording speed of the magnetic tape is high. 1. A magnetic tape recording speed discriminating device comprising discriminating means for discriminating in three ways: high speed, medium speed, and low speed.