JPH05268527A - Defect picture element detection circuit for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To detect a defect picture element in an excellent way by using a threshold level corresponding to temperature obtained through multiplication between temperature data from a temperature sensor and threshold data so as to discriminate whether or not an output from the detection circuit is an output due to a defect picture element and so as to reduce the dependency of the detection performance of a defect picture element on temperature remarkably thereby preventing mis-detection. CONSTITUTION:The detection circuit is provided with a system controller 4 detecting a defect picture element outputting a specific level signal in each picture element of a CCD element 2 based on an output signal from the CCD element 2, a switch 20, a predetection processing circuit 21, a detection circuit 22 and a temperature sensor 7 sensing temperature of the CCD element 2, and the system controller 4 varies a threshold level used to detect the defect picture element in response to the temperature data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defective pixel detection circuit for a solid-state image pickup device suitable for application to, for example, a video camera capable of detecting defective pixels and correcting the defective pixels.

[0002]

2. Description of the Related Art For example, in a video camera using a CCD element, it is obtained by picking up an image by a so-called defective pixel which outputs a signal of a peculiar level in each pixel of the CCD element in a state where no light is incident. There is a problem that the image quality deteriorates.

Therefore, conventionally, a correction circuit for correcting a signal output by a defective pixel is mounted on the video camera, and before the video camera is shipped to the user, which pixel is defective in the CCD element of the video camera. After actually inspecting a pixel and storing the information indicating the defective pixel obtained as a result of the inspection in the storage area of the correction circuit of the video camera, the correction circuit The signal output from the defective pixel is corrected by the correction circuit.

As this correction method, a defect correction method such as so-called 0th-order interpolation and 1st-order interpolation and a so-called RPN (residual pattern noise) correction method have been put into practical use.

Among the former correction methods, the 0th-order interpolation is a method in which a signal output from a defective pixel is held in a sampling circuit and the signal output from the defective pixel is replaced with the signal of the immediately preceding pixel.

In the former correction method, the primary interpolation obtains the average of the signal output from the pixel immediately before the defective pixel and the signal output from the pixel next to the defective pixel, and calculates the average from the defective pixels. This is a method of replacing the output signal with an average signal.

In the latter method, that is, RPN (residual pattern noise) correction, a signal corresponding to the signal output from the defective pixel is generated inside the video camera, and the signal output from the defective pixel is generated. This is a method of subtracting the signal to cancel the signal output from the defective pixel.

By the way, the constituent pixels of the CCD element may not only be defective at the manufacturing stage, but also may be suddenly defective even after actually reaching the user's hand. There may be a defect state in which a signal having a peculiar level, that is, residual pattern noise is generated in a state where no light is incident.

Therefore, the CC used in the video camera
When the defective pixel of the D element is inspected to obtain information such as address data of the defective pixel and the information is stored in the memory of the video camera and then passed to the user's hand, the above-mentioned sudden defect It is not possible to deal with the generation of pixels and the generation of defective pixels due to aging.

Therefore, recently, a circuit for detecting a defective pixel is further installed inside the video camera, the defective pixel is detected by the circuit for detecting the defective pixel, and the information on the defective pixel obtained by the detection is detected by the video camera. Has been proposed in which the defective pixel newly generated is corrected by, for example, the above-described RPN correction circuit mounted on the video camera based on this information.

Detection of defective pixels is performed as follows, for example. That is, while the light is not incident on the CCD element, the level of the signal output from each pixel of the CCD element is compared with the level of the signal output from the pixel immediately before this pixel, or each level of the CCD element is compared. The level of the signal output from the pixel is compared with a predetermined threshold level, and 1
When the level of the signal output by the previous pixel or the level of the signal output by the current pixel is higher than the threshold level, it is detected as a pixel (defective pixel) that outputs a signal of a peculiar level, and This is performed by obtaining address (data) and flaw (defective pixel) data based on the signal level output from the pixel and storing these in a memory or the like.

On the other hand, after detecting the defective pixel as described above, based on the address data of the defective pixel stored in the memory, from the signal corresponding to the defective pixel of the video signal supplied from the CCD element, from the memory. By subtracting the read Blemish data corresponding to the read address data of the defective pixel, a signal of a specific level due to the defective pixel is corrected.

[0013]

By the way, when the threshold value for detecting a defective pixel is always constant, the defective pixel output level depends on the temperature, and therefore the defective pixel detection performance depends on the temperature. There was an inconvenience.

Furthermore, when noise is added to a pulse (output that should not be detected as a defective pixel) below the threshold level for various reasons such as jitter, this pulse is erroneously detected as an output by the defective pixel. There was an inconvenience.

The present invention has been made in view of the above points, and provides a defective pixel detection circuit for a solid-state image pickup device capable of greatly reducing the temperature dependence of defective pixel detection and preventing erroneous detection of noise and the like. It is a proposal.

[0016]

A defective pixel detection circuit for a solid-state image pickup device according to the present invention is based on an output signal of the solid-state image pickup device 2 as shown in FIGS. , Defective pixel detection means 4, 20, 21, 22 for detecting a defective pixel that outputs a signal of a peculiar level, a temperature sensor 7 for detecting the temperature of the solid-state image sensor 2, and temperature information from the temperature sensor 7. Defective pixel detection means 4, 20,
21 and 22, and a control means 4 for varying a threshold value used for detecting a defective pixel.

[0017]

According to the present invention described above, defective pixel detection means 4, 20, 21, 2 is generated according to the temperature information from the temperature sensor 7.
Since the threshold value used for detecting the defective pixel in 2 is made variable, the output from the defective pixel having a positive temperature characteristic is judged to be the output from the defective pixel. The threshold value can also be made to have a positive temperature characteristic, and the detection performance with respect to the signal output by the defective pixel can be kept constant, thereby greatly increasing the temperature dependence of the detection performance of the defective pixel detection system. In addition, it is possible to prevent an accident such as erroneously detecting even an output of a minute defective pixel which is unnecessary in the application, and it is possible to detect a good defective pixel. Even if noise is added to the signal at a level lower than the threshold value for various reasons, the threshold value will be raised and the sensitivity will be weakened as a result. Because there, it is possible to prevent erroneous detection.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the defective pixel detection circuit of the solid-state image pickup device of the present invention will be described in detail below with reference to FIGS.

FIG. 1 is a block diagram showing an example in which the defective pixel detection circuit of the solid-state image pickup device of the present example is applied to a video camera. Hereinafter, with reference to FIG. 1, the solid-state image pickup device of the present example is applied to a video camera. The case will be described.

In FIG. 1, reference numeral 1 denotes an optical system such as a lens and an iris, and light from a subject is supplied to the CCD element 2 through the optical system 1. In this embodiment, for example, the CCD element 2 is composed of three CCD elements for green, red and blue components. In this case, the above-mentioned optical system 1 includes a prism, and the light of the green component of the light from the subject is supplied to this CCD element 2 (for the green component light) by this prism, and the light of the red component Light is supplied to this CCD element 2 (for red component light), and light of a blue component is supplied to this CCD element 2 (for blue component light). Incidentally, this CCD element 2
May be, for example, a single plate type or a two plate type.

The light of the green, red and blue components supplied to the CCD element 2 is photoelectrically converted in the CCD element 2 (three CCD elements), and the charge accumulation time is changed by the charge accumulation control signal from the timing generator 5. Are controlled and read by the read signal from the timing generator 5.

Here, there are a field read and a frame read as a method of reading a signal from the CCD element 2, and in this example, for example, when a defective pixel is detected, it is forced by a command from a defective pixel correction system described later. Switch to the frame accumulation mode.

Since it is extremely rare that a signal of a specific level extends over two pixels due to a defective pixel, in frame reading, the output from one defective pixel appears in either an even or odd field. ..

On the other hand, in field reading, the output from one defective pixel appears in both even and odd fields.

Therefore, when the detection is performed by the field reading, the memory capacity for two pixels is required for the output of one defective pixel. However, in order to specify a pixel having one peculiar level of output, the memory capacity of these two pixels is necessary.

In order to correct the output due to a defective pixel and not to correct the output due to a pixel that is not defective during frame reading, it is essential to specify a pixel having an output at a peculiar level. It is a condition.

However, this specifying process is very time-consuming, and in particular, when a defective pixel is detected during field reading, charge accumulation in the photosensor of the CCD element 2 is performed in the field period. Since it is only carried out, 2 of the charge accumulation time in the field read
The signal level output by the defective pixel is half the level of the signal output by the defective pixel in the frame reading, as compared with the frame reading in which the charge accumulation time is doubled.
The S / N of the detection when the field reading is performed to detect the defective pixel is significantly lower than the S / N of the detection when the frame reading is performed to detect the defective pixel.

Therefore, in this example, in the defective pixel detection mode, the read mode from the CCD element 2 is forcibly set to the frame read mode. Therefore, the S / N of the detection is improved by 6 dB as compared with the case where the field reading is performed and the defective pixel is detected, and it is possible to detect the defective pixel with high accuracy and at the same time, and to detect the defective pixel. The required memory capacity can be reduced to half that in the case where field reading is performed and defective pixel detection is performed.

The output from the CCD element 2 is supplied to the sampling circuit 3, and in the sampling circuit 3, the CCD element 2 is based on the signals from the timing generator 5 and the pulse generator 8 as shown in FIG.
The output signal from the above is sampled at a sampling point indicated by P in the figure to remove reset noise and the like, and the sampled signals, that is, signals corresponding to green, red and blue are added to the adder circuits 9, 10 and 11. Supply to each.

These adder circuits 9, 10 and 11 add the correction signals corresponding to green, red and blue from the correction circuit 16 described later to the signals corresponding to green, red and blue from the sampling circuit 3, respectively. The addition signals corresponding to green, red, and blue are supplied to other video signal processing circuits of a video camera (not shown) via output terminals 17, 18 and 19, respectively, and the fixed contacts 20a, 20b of the switch 20 and Two
Supply to 0c respectively.

Now, this switch 20 is provided for each adder circuit 9,
In addition to the fixed contacts 20a, 20b, 20c to which signals corresponding to green, red and blue from 10 and 11 are supplied, the temperature sensor 7 attached to the package of the CCD element 2 detects the temperature of the CCD element 2. It has a fixed contact 20d to which the temperature information of the movable contact 2 is supplied.
0e corresponds to each of these fixed contacts 20a, 20b, 20c and 2
By connecting to 0d, signals and temperature information corresponding to green, red, and blue are supplied to the detection preprocessing circuit 21.

The pre-detection processing circuit 21 detects the discontinuous minute levels of the carrier components of the signals corresponding to green, red and blue among the signals or temperature information corresponding to green, red and blue supplied from the switch 20. After removing the signal, the signals corresponding to green, red and blue from which the discontinuous minute level of the carrier component is removed, and the temperature information are converted into digital signals, and green,
Digital signals corresponding to red and blue are supplied to the detection circuit 22 and digital temperature data is supplied to the system controller 4.

The detection circuit 22 is a pre-detection processing circuit 21.
The low-pass filtering process was performed on the digital signals corresponding to green, red, and blue supplied from, and the comparison was made with the so-called threshold level for white defects that appear white on the screen and for black defects that appear black on the screen. Then, the result is supplied to the system controller 4.

The system controller 4 compares the result from the detection circuit 22 with a threshold level based on the digital temperature data, and the video signal corresponding to the result from the detection circuit 22 is output by the defective pixel according to the comparison result. When it is determined that the address signal from the horizontal / vertical counter 6 is stored in the register 14, various information related to the defective pixel is stored.

After the defect detection is completed (for example, the defect detection mode), the address data of the defective pixel and various information stored in the register 14 are stored in the memory (for example, EEPROM or battery backup) via the read / write circuit 12. RAM 13).

On the other hand, during normal shooting, the memory 1
The address signal of the defective pixel stored in 3 is read out, this address signal is compared with the address signal from the horizontal / vertical counter 6, and if they match, the pulse generator 8
The timing generator 5 is controlled to hold the signal portion corresponding to the defective pixel in the sampling circuit 3.

Further, the system controller 4 corrects the defective pixel when the stored defective pixel level is equal to or higher than the stored level during the defective pixel correcting operation.
The mask signal is supplied from 5 to the correction circuit 16, whereby the correction circuit 16 does not perform correction on the output from the defective pixel whose level changes.

The system controller 4 also has a switch sw2 for supplying a shutter enable signal as a detection enable signal based on the setting information from the switch sw1.
Is turned on and off, and a detection enable signal is supplied to the detection circuit 22 to control the detection of defective pixels by the detection circuit 22. Therefore, for example, the switch sw1
When the user operates to set the defective pixel detection mode,
The detection enable signal is supplied to the detection circuit 22 to enter the detection mode of the defective pixel, and the switch sw2 is turned off by this detection enable signal, whereby the shutter enable signal is not supplied to the timing generator 5. Therefore, the so-called shutter operation, which shortens the charge accumulation time in the CCD element 2 than the normal accumulation time, is not performed, the S / N deterioration of the detection of the defective pixel is reduced, and the defective pixel can be detected satisfactorily. it can.

The defective pixel described above will now be described. As shown in FIG. 3, the defective pixel has a white point (white flaw) W1 that does not depend on the light amount but depends on the temperature, and a white point that depends on both the light amount and the temperature. There are points (white scratches) W2 and black dots (black scratches) B1, and black dots (black scratches) B2 that do not depend on the light amount but depend on the temperature. Therefore, in this example, in order to satisfy these conditions, the defective pixel is detected or corrected based on the temperature information from the temperature sensor 7.

For both such minute white dots and black dots, a constant bias voltage is added or subtracted to the signal output of the defective pixel. The image signal component normally responds to the amount of incident light. Therefore, the position of the defective pixel and the amplitude of the defective component at a certain temperature are measured and stored in advance, and a correction signal having the same amplitude and the opposite polarity as the defective component is generated at the same timing as the signal output of the defective pixel. By adding it to the signal output of, the defect component of the video signal can be canceled. This state is shown in FIG.

FIG. 4 shows each waveform with the vertical axis representing the amplitude level (V) of the video signal and the horizontal axis representing the time (T).
Is the output signal out1 when the amount of light is large and the output signal ou when the amount of light is small.
It shows t2. The range indicated by the broken line corresponds to the output pulse for one pixel.

As shown in FIG. 4A, the minute white point pulse W and the minute black point pulse B output from the defective pixel are generated in both the large light amount output signal out1 and the small light amount output signal out2. ..

Output signal out at high light quantity shown in FIG. 4A
The minute white spot pulse W and the minute black spot pulse B of 1 are shown in FIG. 4B.
Minute white point correction pulse Wp and minute black point pulse Bp shown in
By adding a correction signal consisting of (compensated by the correction circuit 16 in FIG. 1), the minute white-spot corresponding pulse W and the minute black-spot corresponding pulse B are corrected as shown in FIG. 4C as the high light amount output signal out1. ing.

Further, the minute white point pulse W and the minute black point pulse B of the output signal out2 at the small light quantity shown in FIG. 4A are
By adding the correction signal composed of the minute white spot correction pulse Wp and the minute black spot pulse Bp (outputted by the correction circuit 16 in FIG. 1) shown in FIG. 4B, as shown as a small light quantity output signal out2 in FIG. 4C, The minute white-spot corresponding pulse W and the minute black-spot corresponding pulse B are corrected.

Now, each part of the circuit of this embodiment shown in FIG. 1 will be described in more detail below with reference to FIGS.

First, the sampling circuit 3 shown in FIG. 1 will be described with reference to FIGS.

In FIG. 5, reference numeral 30 denotes a correlation double sampling circuit. The correlation double sampling circuit 30 receives a signal (video signal) corresponding to green from the CCD element (green CCD) 2 shown in FIG. The supplied input terminal 31 is connected to the input terminal of the amplifier circuit 32, and the output terminal of the amplifier circuit 32 is connected to the non-inverting input terminal (+) of the operational amplifier circuit 38 via the switch 33. The non-inverting input terminal (+) of 38 is grounded via the capacitor 37, the output terminal of the operational amplifier circuit 38 is connected to the output terminal 45, and the output terminal of the amplifier circuit 32 is connected via the switch 40 to the amplifier circuit 42. And the input terminal of the amplifier circuit 42 is grounded via the capacitor 41,
The output terminal of the amplifier circuit 42 is connected to the inverting input terminal (-) of the operational amplifier circuit 38 via the switch 43, and the inverting input terminal (-) of the operational amplifier circuit 38 is grounded via the capacitor 44. Composed by.

The correlated double sampling circuit 3
The sample hold signal SHP from the timing generator 5 is supplied to the 0 switch 40 via the input terminal 39, and the switch 3 of the correlated double sampling circuit 30 is supplied.
The sample hold signal SHD from the AND circuit 36 is supplied to 3 and 43.

In the AND circuit 36, the sample hold signal SHD supplied to the switches 33 and 43 is the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to green. It is a signal obtained by taking a logical product.

Reference numeral 49 is a correlated double sampling circuit for a signal corresponding to red. This correlated double sampling circuit 4
The configuration of 9 is similar to that of the correlated double sampling circuit 30. The input terminal 46 is connected to the correlated double sampling circuit 49.
A signal corresponding to red from the CCD element (red CCD) 2 shown in FIG. 1 is supplied via the, and the output of the correlated double sampling circuit 49 is supplied to the output terminal 50. Although not shown, the sample hold signal SHP from the timing generator 5 is supplied to the switch 40 of the correlated double sampling circuit 49 via the input terminal 39.
The sample hold signal SH from the AND circuit 48 is applied to the switches 33 and 43 of the correlated double sampling circuit 49.
Supply D.

Switches 33 and 43 not shown in the drawing
The sample-and-hold signal SHD supplied to the AND circuit 48 is obtained by ANDing the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to red in the AND circuit 48. Signal.

Reference numeral 54 is a correlated double sampling circuit for a signal corresponding to blue.
The configuration of 4 is similar to that of the correlated double sampling circuit 30. The input terminal 51 is connected to the correlated double sampling circuit 54.
A signal corresponding to blue is supplied from the CCD element (blue CCD) 2 shown in FIG. 1 via the, and the output of the correlated double sampling circuit 54 is supplied to the output terminal 55. Although not shown, the switch 40 of the correlated double sampling circuit 54 is supplied with the sample hold signal SHP from the timing generator 5 via the input terminal 39, and the switch 33 of the correlated double sampling circuit 54 is supplied.
And 43 are supplied with the sample hold signal SHD from the AND circuit 53.

Switches 33 and 43 not shown in the drawing
The sample-and-hold signal SHD supplied to the AND circuit 53 is obtained by ANDing the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to blue in the AND circuit 53. Signal.

A signal shown in FIG. 6A is supplied to each AND circuit 36, 48 and 53, and the AND circuit 36 is provided with a signal (G) corresponding to green as shown in FIG. 6B in addition to this signal.
A frame signal from the timing generator 5 that is active for one frame for every three frames (ch) is supplied, and the logical product of these two signals is calculated to generate the sample hold signal SHD as shown in FIG. 6E.

Similarly, in the AND circuit 48, in addition to the signal shown in FIG. 6A, the signal from the timing generator 5 which becomes active for one frame for every three frames for signals (Rch) corresponding to red as shown in FIG. 6C. A frame signal is provided, and the logical AND of these two signals is performed.
A sample hold signal SHD as shown by F is generated.

Similarly, the AND circuit 53 has the configuration shown in FIG.
In addition to the signal shown in FIG. 6D, a frame signal from the timing generator 5 that is active for one frame for every three frames for signals corresponding to blue (Bch) as shown in FIG. 6D is supplied, and the logical product of these two signals is supplied. Is taken,
A sample hold signal SHD as shown in FIG. 2G is generated.

Next, the operation of the sampling circuit 3 shown in FIG. 5 will be described with reference to FIG.

As shown in FIG. 7A, the signals (G, R, Bch signals) supplied from the CCD element 2 to the sampling circuit 3 shown in FIG. 5 have the pre-charge level shown in FIG. 7B. The signal SHP (the signal from the timing generator 5 supplied to the input terminal 39 in FIG. 5) is sample-held, and the data level of the signal shown in FIG. 7A is the sample-hold signal SHD shown in FIG. 7C (the AND circuit 36 in FIG. 5). Four
The signals corresponding to the outputs of 8 and 53 are sampled and held by (in FIG. 6, corresponding to FIGS. 6E, F and G respectively).

If the data level is the abnormal level pa as shown in FIG. 7A, the abnormal level pa is also output in the normal operation as shown in FIG. 7D. Therefore, as shown in FIG. 7E, a signal indicating the position of the abnormal level pa is used so as not to output a signal corresponding to this abnormal level pa among the sampling signals SHD shown in FIG. 7C (FIG. 7F). .. Thus, as shown in FIG. 7G, an abnormal level p of the output signal
The signal corresponding to a remains the output signal of the previous pixel, that is, the held state. Therefore, as shown in FIG. 7G, the abnormal levels pa are removed from the outputs from the respective output terminals 45, 50 and 55 of the correlated double sampling circuits 30, 49 and 54 connected to the operational amplifier circuit 38 shown in FIG. Output.

Further, as shown in FIG. 5, the operational amplifier circuit 3
A signal obtained by sampling the data level of each pixel is supplied to the non-inverting input terminal (+) of 8 and a signal obtained by sampling the data level of each pixel is supplied to the inverting input terminal (-) of the operational amplifier circuit 38. Therefore, the data potential of each pixel and the reset potential of each pixel are sampled and held, and the difference between these is obtained in the operational amplifier circuit 38, and this is output.

Therefore, the reset noise and the like, which are in-phase components between the reset potential and the data potential, can be removed.

As described above, in the sampling circuit 3, as shown in FIG. 6, a signal corresponding to green, a signal corresponding to red and a signal corresponding to blue from the CCD element 2, that is, Gch (channel). ), Rch (channel) and Bch (channel) outputs are sampled respectively, and Rch is sampled during Gch sampling.
And sampling of Bch are stopped, sampling of Gch and Bch is stopped during sampling of Rch,
Since sampling of Gch and Rch is stopped during sampling of Bch, it is possible to prevent deterioration of image quality due to so-called jumping of data from a channel other than the channel being sampled.

FIG. 8 is a block diagram showing another example of the sampling circuit 3 described above. As shown in FIG. 8, in this example, CCD element (R) 2R, CCD element (G) 2
The outputs from the G and CCD elements (B) 2B are output to the sampling circuit 1 via switches 130, 131 and 132, respectively.
33, the output is output from the output terminal 135, and the switches 130, 131, and 132 are sequentially turned on, for example, for each frame by a control signal from a separately provided control circuit 134.

When the control signal output from the control circuit 134 is a signal as shown in FIGS. 6B, 6C and 6D, for example, a frame signal that becomes active in one frame in three frames shown in FIG. 6B is supplied to the switch 131. The switch 131 is turned on while the frame signal is active, so that the output from the CCD element 2G is output to the sampling circuit 133 via the switch 131.
And is sampled. Next, a frame signal that is active for one frame in three frames shown in FIG. 6C is supplied to the switch 130, and the switch 130 is turned on for a period in which this frame signal is active,
As a result, the output from the CCD element 2R is switched to the switch 13
It is supplied to the sampling circuit 133 via 0 and is sampled. Next, a frame signal that is active for one frame in three frames shown in FIG. 6D is supplied to the switch 132, and the switch 132 is turned on while the frame signal is active, which causes the CCD to operate.
The output from the element 2B is supplied to the sampling circuit 133 via the switch 132 and is sampled.

Therefore, also in this case, as in the sampling circuit 3 described with reference to FIG.
To the signal corresponding to green from the CCD element 2R, the signal corresponding to red from the CCD element 2R and the signal corresponding to blue from the CCD element 2B, that is, for the output of Gch (channel), Rch (channel) and Bch (channel). Rch during sampling of Gch
Since the signals of Bch and Bch are not supplied to the sampling circuit 133, sampling is not performed, and the signals of Gch and Bch are sampled by the sampling circuit 1 during sampling of Rch.
Since it is not supplied to 33, sampling is not performed and Bc
Since the Gch and Rch signals are not supplied to the sampling circuit 133 during the sampling of h, the sampling is not performed, thereby preventing the deterioration of the image quality due to the so-called data jump from the channel other than the sampling channel. it can.

Next, the system controller 4 shown in FIG. 1 will be described with reference to FIG.

As shown in FIG. 9, inside the system controller 4 shown in FIG.
The comparison circuit 60 is arranged in addition to the original circuit (not shown). That is, the output signal (comparison result signal) from the detection circuit 22 shown in FIG. 1 is supplied to the comparator 62 via the input terminal 61, and the digital temperature data from the detection preprocessing circuit 21 shown in FIG. The signal is supplied to the multiplication circuit 65 via the input terminal 63, and the threshold circuit 64 is supplied.
To the multiplying circuit 65. In the multiplication circuit 65, the temperature sensor (see FIG. 1) thermally coupled to the CCD element 2 detects the threshold data from the threshold circuit 64, and the pre-detection processing circuit 21 digitally detects this. Modulate with the converted digital temperature data.
Further, the modulated threshold data and the signal supplied from the detection circuit 22 are compared with each other by a comparator 62.
To the other circuit of the system controller 4 (not shown) via the output terminal 66.

In this way, the threshold data for determining that this output is the output from the defective pixel with respect to the output from the defective pixel having the positive temperature characteristic, also has the positive temperature characteristic. Yes, the detection performance for the signal output by the defective pixel can be kept constant,
As a result, the dependency of the detection performance of the automatic defective pixel detection system on temperature is significantly reduced, and, for example, an accident such as erroneous detection of even a minute defective pixel output that is unnecessary in the application is prevented. However, a good defective pixel can be detected. Further, even when noise is added to a signal having a level lower than the threshold level due to various reasons such as jitter, the threshold level is eventually raised and the sensitivity is lowered, so that erroneous detection can be prevented.

Next, the internal structure and operation of the register 14 will be described with reference to FIGS.

In FIG. 10, 70r, 70r +
70r + n are main registers, and these main registers 70r, 70r + 1 ,.
+ N is an area in which a horizontal address is stored, an area in which a vertical address is stored, an area in which a field flag indicating the number of the field is stored, and channel information (Rc
(h, Gch and Bch information) and an area in which time history data is stored. The information stored in each of these areas is information corresponding to the defective pixel.

The time history here is the number of times that a certain pixel is not detected as a defect, and in the present example, when a certain pixel is not detected as a defect 10 times, for example, this pixel is not made a defective pixel. .. This is because some pixels may or may not output a signal of a specific level (a level as a defect) on a field-by-field or frame-by-frame or irregular basis. In such a case, even if it is desired to correct such a pixel as a defective pixel, if a defective pixel is detected when a signal of a specific level is not output, the defective pixel is not detected, and the correction processing cannot be performed. Is. In this example, the pixel which outputs a signal of a peculiar level irregularly can be corrected as a defective pixel. Further, in this way, noise that is suddenly mixed into the video signal will not be erroneously detected as a defective pixel.

The main registers 70r, 70r + 1,
The information stored in 70r + n is the information of the pixel determined to be defective before the detection of the defective pixel is started this time, that is, at the present time.

72r, 72r + 1, ... 72r + n
Are sub registers, and these sub registers 72r, 7r
72r + n is an area in which a horizontal address is stored, an area in which a vertical address is stored, an area in which a field flag indicating the number of the field is stored, and channel information (Rch, Gch and Bch information).
Is stored and an area where time history data is stored. The information stored in each of these areas is information corresponding to the defective pixel, and before the detection of the defective pixel is started,
The main registers 70r, 70r + 1, ... 7 described above
The information of the defective pixel determined to be defective at the present time stored in 0r + n is stored in the sub-registers 72r, 72r + 1,
72r + 2, ... 72r + n, respectively.

71c, 71c + 1, ... 71c + n
Are respectively comparators, and the sub-registers 72r, 72r + 1, ... 72r + read by the data selector 73.
defective pixel information from n and main registers 70r and 70r
+1 ... Detects a match of information from 70r + n,
For example, the system controller 4 is notified of this detection result.

Next, referring to FIG. 11 to FIG.
The operation of the register 14 shown in FIG.

In FIG. 11, the pixel information judged to be defective at the present time is shown in the main registers 70r, 70r + 1, 70r.
It is stored in +2, ..., 70r + n. The address area of the main register 70r stores the address data of the defective pixel at the address "x" (horizontal / vertical address in FIG. 10), and the time history data "8" is stored in the time history area. In addition, the main register 70r
The address data of the defective pixel, which is the address “y” (horizontal / vertical address in FIG. 10), is stored in the +1 address area, and the time history data “3” is stored in the time history area. The address area of the main register 70r + 2 stores the address data of the defective pixel having the address "z" (horizontal / vertical address in FIG. 10), and the time history area "0" is stored.

For the convenience of explanation, the explanation of other information shown in FIG. 10 will be omitted.

Before the detection, the main registers 70r and 7r are controlled by the control signal from the system controller 4.
0r + 1, 70r + 2, 70r + 3, ... 70r +
The contents of n are shown in FIG.
r, 72r + 1, 72r + 2, 72r + 3, ... 7
2r + n, and then main registers 70r, 7
0r + 1, 70r + 2, 70r + 3, ... 70r +
Clear each area of n.

Further, in each of FIGS. 11 to 18, "not" indicates a cleared state in which pixel information is not stored.

Now, the main registers 70r, 70r +
After clearing 1, 70r + 2, 70r + 3, ... 70r + n, defective pixels are detected by the control of the system controller 4, and information of the pixels determined to be defective is stored in the main registers 70r, 70r + 1, 70r + 2, 70.
Stored in r + 3, ..., 70r + n, respectively. An example of this case is shown in FIG. As shown in FIG. 13, the address "x" is stored in the address area of the main register 70r.
Since the address data of the defective pixel is stored and the time history area is detected by the first detection operation, the time history data “10” is stored, for example. In addition, the main register 70
Since the address data of the defective pixel having the address “v” is stored in the address area of r + 1, and the time history area is detected by the first detection operation, for example, the time history data “1”.
0 "is stored. Although not shown, other information other than the address data and time history data of these defective pixels is also stored.

Next, as shown by the hatched signal lines in FIG. 14, the contents of the sub-register 72r is the data selector 73.
Information of the defective pixels read by the comparators 71c, 71c + 1, 71c + 2, 71.
c + 3, ..., 71c + n, respectively, and these comparators 71c, 71c + 1, 71c + 2, 71+
3, ... 71c + n, the main register 70
r, 70r + 1, 70r + 2, 70r + 3, ... 7
The information of the defective pixel read from 0r + n is sequentially compared. As a minimum condition for this matching, it is necessary that the channel data and the address data match.

In the example of FIG. 14, the sub-register 72r
Since the address data of the defective pixel information stored in (1) coincides with the address data of the defective pixel information stored in the main register 70r (the same applies to the channel data if not shown), the comparator 71c A signal corresponding to the detection result is sent to, for example, the system controller 4
Supply to.

Next, as shown by the hatched signal lines in FIG. 15, the contents of the sub-register 72r + 1 are read out by the data selector 73, and the information of the read out defective pixels is read out by the comparators 71c, 71c + 1, 71c + 2.
71c + 3, ..., 71c + n, and these comparators 71c, 71c + 1, 71c + 2, 71+
3, ... 71c + n, the main register 70
r, 70r + 1, 70r + 2, 70r + 3, ... 7
The information of the defective pixel read from 0r + n is sequentially compared.

In the example of FIG. 15, the sub-register 72r
The address data of the defective pixel information stored in +1 (the same applies to the channel data (not shown)) is stored in the main registers 70r, 70r + 1, 70r + 2, 70r +.
3 ... 70r + n does not match any of the address data of the defective pixel information (the same applies to the channel data (not shown)), so that the comparators 71c, 71c + 1, 71c + 2, 71c + 3,
··········· 71c + n does not react At this time, the time history data stored in the time history area of the sub-register 72r + 1 is "3" and has not yet become "0". For example, the system controller 4 is stored in this sub-register 72r + 1. The information of the defective pixel is not erased, and "1" is subtracted from the time history data "3" stored in the sub register 72r + 1 to change the time history data to "2".
The information of the defective pixel (only the time history data is set to "2") stored in the unused main register 70r +
Stored in any of 2, 70r + 3, ..., 70r + n. In this case, the signal is stored in the unused main register 70r + 2 as indicated by the hatched signal line in FIG.

Next, as shown by the hatched signal lines in FIG. 17, the contents of the sub-register 72r + 2 are read by the data selector 73, and the information of the read defective pixel is read by the comparators 71c, 71c + 1, 71c + 2,
71c + 3, ..., 71c + n, and these comparators 71c, 71c + 1, 71c + 2, 71+
3, ... 71c + n, the main register 70
r, 70r + 1, 70r + 2, 70r + 3, ... 7
The information of the defective pixel read from 0r + n is sequentially compared.

In the example of FIG. 17, the sub-register 72r
The address data of the defective pixel information stored in +2 (the same applies to the channel data (not shown)) is stored in the main registers 70r, 70r + 1, 70r + 2, 70r +.
3 ... 70r + n does not match any of the address data of the defective pixel information (the same applies to the channel data (not shown)), so that the comparators 71c, 71c + 1, 71c + 2, 71c + 3,
··········· 71c + n does not react At this time, since the time history data stored in the time history area of the sub register 72r + 2 is “0”, the system controller 4 uses the information of the defective pixel stored in the sub register 72r + 2 as the main register. 70r,
70r + 1, 70r + 2, 70r + 3, ... 70r
It is not stored in either + n. Therefore, in the case of this example, the information of the defective pixel stored in the main register 70r + 2 is stored immediately before the start of the detection of the next defective pixel and corresponds to the address data "z" stored in the sub register 72r + 2. Only the information of the defective pixel to be erased is erased.

After the above processing is completed, the process shown in FIG.
As shown in, the main register 70r has time history data of "10", information of defective pixel corresponding to the address "x" is stored, and the main register 70r + 1 has time history data of "10" and address "x". The information of the defective pixel corresponding to v "is stored, the time history data is" 2 "in the main register 70r + 2, the information of the defective pixel corresponding to the address" y "is stored, and the time history data is stored in the sub register 72r. Is "8", the information of the defective pixel corresponding to the address "x" is stored, and the sub register 72r + 1 stores the information of the defective pixel corresponding to the address "y" with the time history data of "3". In the sub register 72r + 2, the time history data is "0", and the information of the defective pixel corresponding to the address "z" is stored. As will be described later, when the temperature is low at the next detection, only the information of the defective pixel stored in the sub register 72r + 2 is cleared in this way, and the other sub registers 72r, 72r + 1, 72r + 3, ... 72
The information of the defective pixel stored in r + n may be retained.

In this way, for example, when a pixel once judged to be defective at the time of detection is not judged to be defective ten times in succession during the detection period or at each detection, the corresponding pixel is not judged to be a defective pixel. Therefore, it is possible to judge a pixel that outputs a signal of a specific level irregularly as a defective pixel irregularly due to, for example, the influence of the temperature described above, and perform the correction processing for this defective pixel. The signal of a unique level is not mistakenly determined to be a defective pixel, and therefore the pixel of the channel and address corresponding to the portion on which this signal is present is not erroneously corrected. It is possible to detect a defective pixel with high accuracy and correct the defective pixel.

In the above example, the case in which the pixel once determined to be a defective pixel is not made to be a defective pixel when the time history data becomes "0" has been described. The time history data is set to "0", "1" is added every time it is not determined to be defective, and when the time history data becomes "10", the pixel having the time history data is determined not to be a defective pixel. You can

Next, a case where the contents of the register 14 of FIG. 1 described with reference to FIGS. 11 to 18 are processed according to the temperature will be described.

The register 14 shown in FIG. 1 stores various pieces of information on defective pixels obtained as a result of the defective pixel detection processing. In this example, in performing the detection, two methods can be selectively adopted for handling various information of the defective pixel obtained by the detection before the current detection.

One is a method of erasing all the information of the previous defective pixel and detecting again, and the other is a method of correcting the defective pixel with the information of the previous defective pixel and detecting the defective pixel This is a method of adding various kinds of information of the pixel detected as the defective pixel to the information of the defective pixel detected last time.

The defective pixel has a positive temperature characteristic, and the absolute value of the level of the signal output by the defective pixel increases as the temperature increases. Therefore, the former method has the advantage that erroneous data obtained by erroneous detection is erased, so that erroneous data does not remain, but on the other hand, if defective pixels are detected when the temperature is low, Since the level of the signal output from the defective pixel is low, there is a possibility of failing to detect a defective pixel that poses a problem at high temperatures.

On the other hand, in the latter method, since the data of the defective pixel is not erased, even if the defective pixel may be missed at a low temperature, the data obtained at the previous high temperature remains without being erased. Therefore, the information of the originally defective pixel is held in the register 14 and the defective pixel can be corrected even when it is detected at a low temperature. On the other hand, it is obtained by accidental erroneous detection or the like. Unnecessary data is not deleted and is retained in the register forever,
Extra correction processing will be performed.

Therefore, in this example, the system controller 4 selects which of the above two methods is to be used each time it is detected, based on the temperature information from the temperature sensor 7 shown in FIG. To do. That is, when the temperature is low, the method of adding the information of the defective pixel obtained by the current detection to the above-mentioned previous detection data is adopted, and when the temperature is high, the previous detection data is deleted.

In this way, when the temperature is high,
By erasing the previously detected defective pixel information, accidentally erroneously detected data can be erased, and when the temperature is low, the defective pixel information detected this time is added to the previously detected defective pixel information to detect defects at low temperatures. Accidents in which pixels are not detected can be prevented, and thus a memory having a limited capacity can be effectively used, and reliable and highly accurate defective pixel detection can be performed, and good defective pixel correction can be performed.

The time history management method of the register 14 described with reference to FIGS. 10 to 18 and the method of erasing or adding information of the previously detected defective pixel depending on the temperature are used in combination. Is also good.

Next, the correction control circuit 15 shown in FIG. 1 will be described. In this example, the correction control circuit 15 shown in FIG. 1 supplies a control signal to the timing generator 5 via the system controller 4 based on the temperature data from the temperature sensor 7, and the charge accumulation time in the CCD element 2 Is varied within the range of the normal accumulation time to the accumulation time longer than the normal accumulation time.

When the charge storage time in the CCD element 2 is made longer than the normal storage time, the number of frames of the output image decreases, but the amplitude of the output signal increases under the same light amount, and at the time of detecting a defective pixel, This is the detection S / N
It will be an improvement factor. In particular, since the S / N of the output of the CCD element 2 is more likely to deteriorate at low temperatures than at high temperatures,
Thus, making the charge storage time longer than usual is very effective.

Therefore, in this example, the correction control circuit 1
5 is supplied from the temperature sensor 7 via the system controller 4 (note that the temperature sensor 7 or the detection preprocessing circuit 2
The temperature data may be supplied directly from the controller 1. When the temperature data is low, a control signal is supplied to the timing generator 5 via the system controller 4 in accordance with the temperature, and the CCD device 2 receives the control signal. The charge storage time is made longer than usual, and is kept normal when the temperature is high.

In this way, the CCD image pickup device 2 is not used at a low temperature, and the output S / N is not deteriorated even if the CCD device 2 is at a low temperature immediately after the power is turned on. It is possible to improve accuracy and perform good defective pixel detection, and also to perform detection under wider temperature conditions (outside air temperature, temperature of the CCD element 2 itself).

Further, the correction control circuit 15 compares the temperature data supplied from the temperature sensor 7 via the system controller 4 with the reference temperature data, and when the supplied temperature data is lower than the reference temperature data, the correction circuit 16 To a low level "0", and when the temperature data supplied is higher than the reference temperature data, the control signal supplied to the correction circuit 16 is set to a high level "1".

As will be described later, when this control signal is low level "0", that is, when the temperature of the CCD element 2 is low, the gain of the amplifier circuit of the correction circuit 16 is changed. As a result, the level of the correction signal supplied from the correction circuit 16 to each of the adder circuits 9, 10 and 11 can be varied.

Further, the correction control circuit 15 supplies a mask signal (enable signal of the analog switch 88) to an analog switch 88 (see FIG. 19) of the correction circuit 16 which will be described later, and outputs a signal output from the defective pixel due to a temperature rise. When the level reaches a level that the correction circuit 16 cannot completely correct, the defective pixel is not corrected.

Next, the correction circuit 16 will be described with reference to FIG.

In FIG. 19, reference numeral 84 is an input terminal to which the control signal from the correction control circuit 15 shown in FIG. 1 is supplied. The control signal supplied to this input terminal 84 controls the on / off of the switch 85. To do. Reference numeral 80 is an input terminal to which the temperature information from the temperature sensor 7 is supplied, and this input terminal 80 is connected to the input terminal of the temperature characteristic circuit 81.
The temperature characteristic circuit 81 converts the temperature data supplied through the input terminal 80 so as to match the characteristics of the minute white point (the output of the positive electrode of the output of the defective pixel), and outputs the output obtained by this conversion to the temperature. It is supplied to the conversion circuit 82.

This temperature conversion circuit 82 is a temperature characteristic circuit 8
1 is connected to the inverting input terminal (-) of the operational amplifier circuit 83 via the resistor R1, the output terminal of this operational amplifier circuit 83 is connected to the input terminal of the DA converter 87, and this operational amplifier is connected. The output terminal of the circuit 83 is connected to the connection point of the resistor R1 and the temperature characteristic circuit 81, and the resistors R3 and R2 and the switch 85 are provided.
Connected via a series circuit of, the connection point of the resistors R3 and R2 is further connected to the inverting input terminal (-) of the operational amplifier circuit 83, and the non-inverting input terminal (+) of this operational amplifier circuit 83 is grounded. Consists of

As can be seen from this figure, the correction control circuit 1
When the control signal supplied from 5 through the input terminal 84 is at the low level "0", the gain of the temperature conversion circuit 82 is large, and when the control signal is at the high level "1", the temperature conversion circuit 82 has a high gain. The gain becomes smaller.

Therefore, the output from the temperature characteristic circuit 81 is amplified by the operational amplifier circuit 83 with a gain corresponding to the control signal at that time, and then the reference voltage input to the DA converter 87 is used as the reference voltage to the DA converter 87. Supplied to the terminal. The DA converter 87 converts the level data of the defective pixel read out from the memory (for example, ROM) 89 by the system controller 90 into an analog signal based on the reference voltage from the temperature conversion circuit 82, and the analog signal is converted into an analog signal. Supply to the switch 88.

The memory 89 stores the level data of the defective pixel in addition to the level data of the defective pixel described above, and the system controller 90 stores the level data of the defective pixel stored in the memory 89 as D. −
The address signal corresponding to the level data of the defective pixel is supplied to the A converter 87, that is, the analog switch 88 is supplied with a pulse indicating which of the G, R, and B channels is to be corrected.

This analog switch 88 outputs the correction signal supplied from the DA converter 87 to the output terminal 91 for the G channel, the output terminal 92 for the R channel or the B channel according to the address signal from the system controller 90. It is supplied to the adder circuit 9, 10 or 11 shown in FIG. 1 via any of the output terminals 93, and is supplied from the DA converter 87 according to the mask signal supplied from the correction control circuit 15 via the input terminal 86. The supply of the corrected signal to the output terminal 91, 92 or 93 is determined.

Now, the operation of the correction circuit 16 will be described with reference to FIG.

FIG. 20A shows the output from the sampling circuit 3 shown in FIG. 1. As shown in FIG.
The projecting portion indicated by diagonal lines is an offset of the charge having temperature dependence, and has a property that the level becomes large in proportion to the storage time for photoelectric conversion. That is, this is one of the defective pixels that has a peculiar level of output on the projected image.

Here, the waveform shown in FIG. 20A is changed to that shown in FIG. 20B.
The output due to the defective pixel can be canceled by performing the defective pixel correction by adding the waveform shown in FIG. However, the output level of a defective pixel may change over time, and as shown by the broken line in FIG. 20A, the level output by one defective pixel in the waveform increases with time, as shown by p20. May be.

In such a case, even if the output of the defective pixel is corrected, the level increase p2 indicated by the broken line in FIG.
0 becomes a peculiar level output and appears in the output.
If the output of the defective pixel is corrected here, as shown in FIG. 20C, the corresponding portion of the level increase p20 shown in FIG. 20A is replaced with the previous output.

If defective pixel correction is performed using the waveform shown in FIG. 20B in the state shown in FIG. 20C, the result shown in FIG.
As indicated by the hatched line in 0D, an output of the opposite polarity corresponding to the level increase amount p20 indicated by the broken line in FIG. 20 appears.

Therefore, in this example, the correction control circuit 15 is caused to generate a mask signal (for example, a pulse for two clocks) as shown in FIG. 20E, and this mask signal is input through the input terminal 86 shown in FIG. Analog switch 8
8 and the analog switch 88 shown in FIG.
When the mask signal shown in FIG. 6 is at the high level "1", the output is not performed, so that the portion p21 having the opposite polarity to the level increase p20 shown in FIG. 20B is masked as shown by the broken line in FIG. 20F. To do.

Therefore, the output of the defective pixel whose output level changes depending on the temperature can be accurately corrected, and thus the accuracy of the correction of the output of the defective pixel can be increased and the defective pixel can be corrected satisfactorily.

Further, as described above, this correction circuit 16
In accordance with the control signal (switching signal) from the correction control circuit 15, the temperature conversion circuit 82 shown in FIG.
Change the gain of.

This will be described with reference to FIG.

FIG. 21A shows the output from the sampling circuit 3 shown in FIG. 1. As shown in FIG. 21A,
The projecting portion indicated by diagonal lines, that is, the output 22 of the already existing defective pixel is an offset of the temperature-dependent charge, and has a property that the level becomes large in proportion to the accumulation time for photoelectric conversion. That is, this is one of the defective pixels that has a peculiar level of output on the projected image.

FIG. 21B shows the waveform shown in FIG. 21A.
The output due to the defective pixel can be canceled by performing the defective pixel correction by adding the waveform shown in FIG. However, as shown by the broken line in FIG. 21A, when a peculiar level output p23 suddenly appears (a peculiar level at which a normal pixel is determined to be a defective pixel is suddenly output).
If, for example, the above-described charge storage time is set longer than usual when correcting the output of the defective pixel (e.g., doubled), the output of each defective pixel shown in FIG. The levels of p22 and p23 are shown in Fig. 2.
As shown in 1C, the level is doubled.

When the output of the defective pixel is corrected with the waveform shown in FIG. 21B, as shown in FIG. 21D, the correction for the normal output of the defective pixel has been canceled and the output shown in FIG. 21A already exists. Output of defective pixel p22
Up to the output, and these are detected as defective pixels.

Therefore, in this example, the correction control circuit 15
19 is turned off by the control signal from FIG. 19 to increase the gain of the temperature conversion circuit 82, thereby doubling the reference voltage of the DA converter 87, thereby causing a defect from the system controller 90. The output level of the pixel is doubled as shown in FIG. 21E.

By doing so, as shown in FIG. 21F, only the portion corresponding to the output p23 of the new defective pixel remains,
It becomes possible to correct this. Therefore, it is possible to appropriately detect the output of the defective pixel that has suddenly occurred, and to perform an appropriate correction process on the detected defective pixel, which allows good detection of the defective pixel and its correction. it can. Moreover, the output of the defective pixel that is not the detection target is not erroneously detected.

Next, the pre-detection processing circuit 21 shown in FIG. 1 will be described with reference to FIG.

In FIG. 22, reference numeral 100 denotes a signal from the movable contact 20e of the switch 20 shown in FIG. 1 (adding circuits 9 and 1).
0 or 11, or an input terminal to which temperature information from the temperature sensor 7) is supplied, and a signal supplied via the input terminal 100 is supplied to the amplifier circuit 102 and the delay element 101 via the resistor R4. It

The main purpose of the detection preprocessing circuit 21 is to reduce the detection error due to the sampling frequency component. Therefore, the resistor R4 and the delay element 101 described above remove the carrier component in the input signal that is the object of erroneous detection, and the input signal from which this carrier component is removed is amplified by the amplifier circuit 102 having a gain of, for example, several tens of times. Then, the amplified input signal is converted into a digital signal by the A / D converter 103, and the digital signal obtained by this conversion is supplied to the detection circuit 22 shown in FIG. When the detection preprocessing circuit 21 is used, for example, the detection target level of several mV is 100 mVp.
Even if it is added to the carrier component of −p, the detection target level of several mV can be supplied to the detection circuit 15.

Next, the operation of the pre-detection processing circuit 21 will be described with reference to FIG.

A signal to the detection preprocessing circuit 21 through the input terminal 100 of FIG. 22 is a signal having a protruding portion p30 (for example, due to an output signal of a defective pixel) indicated by hatching in a part of the signal as shown in FIG. 23A. 22 is input, if the delay element 101 shown in FIG. 22 is impedance-matched, the signal passed through the resistor R4 is
As shown in FIG. 23B, the projecting portion p30 in the waveform of FIG. 23A becomes the projecting portion p31 indicated by diagonal lines.

When the signal shown in FIG. 23 is delayed by the delay element 101 shown in FIG. 22, the phase is inverted by 180 degrees at the point indicated by the arrow dl in FIG. 22, and the reflected waveform is as shown in FIG. 23C. 23B, the phase of the protruding portion p31 in the waveform of FIG. 23B is inverted (the other portions are the same), and is further delayed by the time of one cycle.

Therefore, the signal supplied to the amplifier circuit 102 shown in FIG. 22 is a waveform obtained by adding the waveform shown in FIG. 23B and the waveform shown in FIG. 23C, that is, as shown in FIG.
3A shows a waveform in which only the projecting portion p30 indicated by hatching is taken out. The waveform shown in FIG. 23D is applied to the amplifier circuit 102 shown in FIG. 22 as a voltage having a level exceeding the threshold level Th for determining a defective pixel in the detection circuit 22 as shown in FIG. 23E, This is converted into a digital signal by the A-D converter 103 and then supplied to the detection circuit 22 described later.

Therefore, it is possible to accurately extract only the output from the defective pixel, which enables good defect detection and correction of the good output of the defective pixel. Note that the temperature information from the temperature sensor 7 is provided separately in A
Alternatively, the signal may be converted into a digital signal by the -D converter and directly supplied to each unit.

Next, the detection circuit 22 shown in FIG. 1 will be described with reference to FIG.

In FIG. 24, 110 is an input terminal to which the pre-detection-processed digital signal from the detection pre-processing circuit 21 shown in FIG. 1 is supplied. The digital signal from this input terminal 110 is added to the addition circuit 112 and the subtraction circuit. Circuit 111
Are supplied to each.

The adder circuit 112 adds the input signal supplied via the input terminal 110 and the signal fed back, and supplies the added output to the flip-flop circuit 114 via the time constant circuit 113. The flip-flop circuit 114 supplies the output signal from the time constant circuit 113 to the subtraction circuit 111 based on the output signal from the comparator 116 described later, and feeds it back to the addition circuit 112 as described above. The addition circuit 112, the time constant circuit 113, and the flip-flop circuit 114 form a low-pass filter. Therefore, the signal output from the flip-flop circuit 114 becomes a signal of the average level of DC neighboring pixels in which so-called whiskers and noise components of the original signal are removed.

The output from the flip-flop circuit 114 is supplied to the subtraction circuit 111, and the subtraction circuit 111 is supplied.
At, the output signal of the flip-flop circuit 114 is subtracted from the input signal supplied through the input terminal 110, that is, the signal which may be the output from the defective pixel. The signal obtained by this subtraction is supplied to the absolute value circuit 115. The absolute value circuit 115 obtains the absolute value of the signal from the subtraction circuit 111. That is, the levels of the white spots (white spots) produced by the output of the defective pixel and the black spots (black spots) produced by the output of the defective pixel are set to the same polarity, and then supplied to the comparator 116 and the signal supplied from the subtraction circuit 111. Determines whether the signal is due to a white defect or a signal due to a black defect, generates a control signal (flag) according to the result of the determination, supplies the control signal to the switch 119, and controls the switching of the switch 119.

One fixed contact 11 of this switch 119
9a is connected to the output terminal of the threshold circuit 117 that outputs the positive threshold signal, the other fixed contact 119b is connected to the output terminal of the threshold circuit 118 that outputs the negative threshold signal, and the movable contact 119c is connected. It is connected to one input terminal of the comparator 116.

The switch 119 generates a threshold level signal from the threshold circuit 117 for generating a threshold level (a positive signal) corresponding to a white defect and a threshold level (a negative signal) for a black defect. Threshold circuit 11
8 and the threshold level signal from the comparator 8 selectively according to the control signal from the absolute value circuit 115.
It is a switch for supplying to 16. The threshold circuits 117 and 118 may have a configuration in which the threshold level data stored in the memory is read by the reading circuit and converted into an analog signal by the DA converter, or a circuit configuration that simply generates an analog voltage. It may be a circuit inside the controller 4.

The comparator 116 compares the absolute value signal from the absolute value circuit 115 with the threshold level signal supplied from the threshold circuit 17 or 18 via the switch 119, and the absolute value signal is larger than the threshold level signal. In this case, the output from the corresponding pixel is determined to be the output from the defective pixel, and the control signal is supplied to the flip-flop circuit 114 so that the output from the corresponding defective pixel is not input to the flip-flop circuit 114. This is because if the output of the defective pixel is used to obtain the average level of the neighboring pixels, the average value will be disturbed.

Here, how the low-pass filter (hereinafter referred to as a filter) composed of the adder circuit 112, the time constant circuit 113, and the flip-flop circuit 114 described above obtains the average value of the neighboring pixels described above. Will be explained.

The output of this filter is the weighted average of the pixels in the front in the horizontal direction. The horizontal address is now k
It is assumed that the pixel is focused on. Assuming that the pixel level at the address k is Pk, the filter output (average level of neighboring pixels) Pkm at time k is (1 / 2Pk-1).
+ (1 / 4Pk-2) + (1 / 8Pk-3) + (1/1
6Pk-4) + ... + ((1/2 nth power) Pk-n
+ ... Therefore, it can be said that it is effectively a weighted average of the front few pixels.

Now, the operation of the above detection circuit 22 will be described.

The digital signal from the pre-detection circuit 21 is added via the input terminal 110 to the addition circuit 112 and the subtraction circuit 11.
1 is supplied. The output from the adder circuit 112 is supplied to the flip-flop circuit 114 via the time constant circuit 113.

On the other hand, when the output of the subtraction circuit 111 is supplied to the absolute value circuit 115, the polarity of the input signal is detected in the absolute value circuit 115, and based on this detection result, a signal due to a white defect or a black defect. The control signal based on the determination result is supplied to the switch 119, the input signal is converted into absolute value data, and the conversion data is supplied to the other input terminal of the comparator 120.

On the other hand, the switch 119 has an absolute value circuit 115.
The movable contact 119c is connected to one or the other movable contact 119a or 119b based on the control signal from the. As a result, a positive (for white flaw) or negative (for black flaw) threshold level signal from the threshold circuit 117 or 118 is read, and the read threshold level signal is input to one input terminal of the comparator 116. Is supplied to.

The comparator 116 compares the absolute value data from the absolute value circuit 115 with the threshold level signal supplied from the threshold circuit 117 or 118, and when the absolute value data is larger than the threshold level signal, the defective pixel is detected. 1 is supplied to the system controller 4 shown in FIG. 1 through the output terminal 120 and the control signal is supplied to the flip-flop circuit 114. Do not capture the signal of. This can prevent the disturbance of the average level of neighboring pixels due to the output of the defective pixel.

As described above, the detection circuit 22 determines whether the signal to be detected is due to the black defect due to the negative output of the defective pixel or due to the white defect due to the positive output of the defective pixel, and it is determined as the white defect. If it is, the threshold level signal for white flaws is used to determine whether the output is due to a defective pixel.If it is determined to be black flaw, the threshold level signal for black flaw is used to determine whether the output is due to a defective pixel. Since it is determined whether or not it is possible, erroneous detection due to so-called whiskers, noise, etc. can be prevented, and good detection can be performed.

As described above, in this example, as shown in FIG. 9, the threshold level corresponding to the temperature obtained by multiplying the temperature data from the temperature sensor 7 by the threshold data is used. Since it is determined whether or not the output from the detection circuit 22 is the output from the defective pixel, the output from the defective pixel having a positive temperature characteristic is judged to be the output from the defective pixel. The threshold level can also be made to have a positive temperature characteristic, and the detection performance with respect to the signal output by the defective pixel can be kept constant, which significantly increases the temperature dependence of the detection performance of the defective pixel detection. Reduced,
For example, it is possible to prevent an accident such as erroneously detecting even an output of a minute defective pixel which is unnecessary in the application, and detect a defective pixel in good condition. Even if there is noise on the signal below the threshold level,
As a result, the threshold level is raised and the sensitivity is lowered, so that erroneous detection can be prevented and defective pixels can be satisfactorily detected.

The above embodiment is an example of the present invention.
Of course, various other configurations can be adopted without departing from the scope of the present invention.

[0151]

According to the present invention described above, the threshold value used for detecting the defective pixel by the defective pixel detecting means in accordance with the temperature information from the temperature sensor is set to be high when the temperature is higher than the predetermined temperature. Therefore, with respect to the output by the defective pixel having the positive temperature characteristic, the threshold value for determining this output as the output by the defective pixel can also have the positive temperature characteristic,
The detection performance with respect to the signal output by the defective pixel can be kept constant, thereby greatly reducing the temperature dependence of the detection performance of the defective pixel detection, and for example, in the case of a minute amount unnecessary in the application. Accidents such as erroneous detection of defective pixel output can be prevented, and defective pixel can be detected satisfactorily. Furthermore, due to various reasons such as jitter, noise may occur in signals below the threshold value. Even when the ‘x’ is added, the threshold value is consequently increased and the sensitivity is lowered, so that there is an advantage that erroneous detection can be prevented and defective pixels can be satisfactorily detected.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a defective pixel detection circuit of a solid-state image sensor according to the present invention.

FIG. 2 is a waveform diagram for explaining an embodiment of a defective pixel detection circuit of the solid-state image pickup device of the present invention.

FIG. 3 is an explanatory diagram for explaining an embodiment of a defective pixel detection circuit of the solid-state image sensor of the present invention.

FIG. 4 is a waveform diagram for explaining an embodiment of the defective pixel detection circuit of the solid-state image sensor of the present invention.

FIG. 5 is a configuration diagram showing an example of a main part of an embodiment of a defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 6 is a waveform diagram provided for explaining a main part of an embodiment of a defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 7 is a waveform diagram provided for explaining a main part of an embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 8 is a configuration diagram showing another example of a main part of an embodiment of the defective pixel detection circuit of the solid-state image sensor of the present invention.

FIG. 9 is a configuration diagram showing an example of a main part of an embodiment of a defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 10 is a configuration diagram showing an example of a main part of an embodiment of a defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 11 is an explanatory diagram for explaining the operation of the main part of the embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 12 is an explanatory diagram for explaining the operation of the main part of the embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 13 is an explanatory diagram for explaining the operation of the main part of the embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 14 is an explanatory diagram for explaining the operation of the main part of the embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 15 is an explanatory diagram for explaining the operation of the main part of the embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 16 is an explanatory diagram for explaining the operation of the main part of the embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 17 is an explanatory diagram for explaining the operation of the main part of the embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 18 is an explanatory diagram for explaining the operation of the main part of the embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 19 is a configuration diagram showing an example of a main part of an embodiment of a defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 20 is a waveform diagram for explaining a main part of an embodiment of the defective pixel detection circuit of the solid-state image sensor of the present invention.

FIG. 21 is a waveform diagram for explaining a main part of an embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 22 is a configuration diagram showing an example of a main part of an embodiment of the defective pixel detection circuit of the solid-state imaging device of the present invention.

FIG. 23 is a waveform diagram provided for explaining a main part of an embodiment of the defective pixel detection circuit of the solid-state image sensor of the present invention.

FIG. 24 is a configuration diagram showing an example of a main part of an embodiment of a defective pixel detection circuit of the solid-state imaging device of the present invention.

[Explanation of symbols]

 1 Optical System 2 CCD Element 3 Sampling Circuit 4 System Controller 5 Timing Generator 6 Horizontal / Vertical Counter 7 Temperature Sensor 8 Pulse Generator 9, 10, 11 Adder Circuit 12 Read / Write Circuit 13 Memory 14 Register 15 Correction Control Circuit 16 Correction Circuit 20 Switch 21 Pre-detection processing circuit 22 Detection circuit

Claims (2)

[Claims] 1. A defective pixel detection unit that detects a defective pixel that outputs a signal of a specific level among pixels of the solid-state image sensor based on an output signal of the solid-state image sensor, and a temperature of the solid-state image sensor. A solid state liquid crystal display device comprising: a temperature sensor that detects the temperature, and a control unit that varies a threshold value used to detect a defective pixel by the defective pixel detection unit according to temperature information from the temperature sensor. Defective pixel detection circuit of image sensor. 2. The control means sets a threshold value used for detecting a defective pixel by the defective pixel detecting means when detecting that the temperature is higher than a predetermined temperature based on the temperature information from the temperature sensor. 2. The defective pixel detection circuit for a solid-state image pickup device according to claim 1, wherein the defective pixel detection circuit is set to a high value.