JPH05268188A - Multiplex radio modulator-demodulator - Google Patents

Abstract

PURPOSE:To provide a multiplex MODEM whose entire size is miniaturized. CONSTITUTION:In the multiplex radio MODEM in which each single carrier of an H polarized wave in orthogonal relation to a V polarized wave is modulated and divided into plural carriers through modulation, the carriers whose frequencies are respectively f1, f2, f3 are synthesized, the synthesized carrier frequency is converted into a radio frequency, it is transmitted, and the signal is demodulated while compensating the mutual effect of the radio signals of the V polarized wave and the H polarized wave to be sent, a signal whose frequency is the greatest common of carrier frequencies is outputted from an oscillator 71, one oscillating frequency is directly multiplied, the other frequency is multiplied via a PLL circuit 79 and each single carrier is modulated by frequencies f1, f2, f3 synchronized with the V polarized wave side and the H polarized wave side obtained from the multiplication.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple radio modulation / demodulation device for performing multilevel modulation / demodulation. In the multiplex radio modulator / demodulator, multicarriers are used for the purpose of improving the fading resistance.

Multi-carrier conversion means that a single carrier S having a center frequency f ₀ as shown in FIG.
As shown in (b), a plurality of carriers (here, three) S1, S2, whose center frequencies are different from f ₁ , f ₂ , and f ₃ , respectively.
This is a method of dividing into S3 to reduce the influence of fading or the like. The bandwidth of each carrier S1, S2, S3 is 1/3 of the bandwidth of the single carrier S.

In the method of transmitting a single carrier, when fading occurs, the band tilts obliquely, and the in-band deviation, which is the difference between the upper limit and the lower limit of the amplitude in the tilted band, increases. The larger the deviation within the band, the more the proof stress is required.

Therefore, the in-band deviation is reduced by using multi-carrier. For example, when the single carrier S is divided into three, even if fading occurs, as shown in FIG.
In the case of, the in-band deviation b can be set to 1/3 of that.

Since such a multiplex radio modulation / demodulation apparatus has a large circuit size due to its circuit configuration, there is a demand for a circuit configuration which can be downsized.

[0006]

2. Description of the Related Art FIG. 11 shows a block diagram of a conventional multiplex radio modulator / demodulator and its description will be given.

In FIG. 11, reference numeral 1 is a transmission apparatus (modulation apparatus), and reference numeral 2 is a reception apparatus (demodulation apparatus). The transmitter 1 and the receiver 2 simultaneously handle V polarization and H polarization of the same frequency based on the single carrier S having the center frequency f ₀ shown in FIG. 10A for the purpose of improving frequency utilization efficiency. It is like this.

The V polarization and the H polarization are orthogonal to each other,
They do not interfere with each other. The upper side of the alternate long and short dash line 3 shown in FIG. 11 is the V polarization side that handles V polarization, and the lower side is the H polarization side that handles H polarization.

The modulator 1 is a modulator (MO
D) 11, 12, 13, hybrid circuit (H) 14,
A transmitter (Tx) 15 and an antenna 16, a modulator (MOD) 21, 22, 23 on the H polarization side, a hybrid circuit (H) 24, a transmitter (Tx) 25, and an antenna 26 are provided. It is configured.

The modulators 11 to 13 have the same structure,
Further, the modulators 21 to 23 have the same configuration, respectively, and have a configuration as shown in FIG. In addition, each modulator 11-1
Single carriers S and S'having orthogonal polarization planes are input to 3 and 21 to 23, respectively.

When the input signal is 16-value QAM, as shown in FIG. 12, P channel (Pch) and Q channel (Qc
The single carriers S and S ′ of h) are input. Figure 1
The modulators 11 to 13 on the V-polarized wave side of 2 are the D / A converters 3
1, 32, mixers 33 and 34, a 90-degree hybrid circuit 35, a local oscillator 36, an in-phase synthesis hybrid circuit 37, and amplifiers 38 and 39.

However, the local oscillator 36 outputs a signal of frequency f ₁ if this modulator has the code 11 in FIG. 11, and if it has the code 12, the frequency f ₂
If the signal of No. 13 is the signal of No. 13, the signal of frequency f ₃ is output.

The D / A converters 31 and 32 convert the single carrier S input as data into an analog signal and output it. The local oscillator 36 has a frequency (eg f ₁ )
Of the hybrid circuit 35.
Is for setting the phase of the output signal of the local oscillator 36 to 0 ° and 90 °, that is, adding a phase difference of 90 ° and outputting to the respective mixers 33 and 34.

The mixers 33 and 34 mix the signal output from the hybrid circuit 35 and the signals output from the D / A converters 31 and 32 and output the mixed signal. The hybrid circuit 37 combines the signals output from the mixers 33 and 34 and outputs the combined signal. Thereby, quadrature amplitude modulation is performed.

The signal output from the hybrid circuit 37 is amplified by the amplifier 38 and output. Local oscillator 36
If the frequency is f ₁ of the output signal of the frequency of the signal output from the amplifier 38 is f _1, and the frequency as long as the f ₂ of the output signal of the local oscillator 36, the frequency of the signal output from the amplifier 38 Is f ₂ , and the frequency of the output signal of the local oscillator 36 is f ₃ , the frequency of the signal output from the amplifier 38 is f ₃ .

Further, the amplifier 39 amplifies the signal output from the local oscillator 36, and modulators 21 to 23 on the H polarization side.
Is output to. The modulators 21 to 23 on the H polarization side have substantially the same configuration as the modulators on the V polarization side, but the difference is 90
That is, the PLL circuit 40 is connected to the input side of the hybrid circuit 35 '. That is, the V polarization side is the master side and the H polarization side is the slave side.

In the modulators 21 to 23 on the H polarization side, V
The same parts as the modulators 11 to 13 on the polarization side are given the same reference numerals with "'". The PLL circuit 40 includes a phase detector (PD) 41, a low pass filter 42, and a voltage controlled oscillator 43.

The phase detector 41 detects a phase error between the signal output from the amplifier 39 and the signal output from the voltage controlled oscillator 43, and the error is supplied to the voltage controlled oscillator 43 via the low pass filter 42. It has a loop configuration.

[0019] If the signal from the amplifier 39 a frequency f ₁ is outputted, PLL circuit 40 is locked at that frequency f _1, will output a signal of frequency f ₁ to the hybrid circuit 35 '. The same applies to the frequencies f ₂ and f ₃ .

That is, the modulator 1 on the V polarization side shown in FIG.
1 and the frequency f ₁ output from the modulator 21 on the H polarization side
Will be output in synchronization with each other. The same applies to the other modulators 12 and 22, 13 and 23.

The hybrid circuit 14 on the V polarization side synthesizes and outputs the signals output from the modulators 11 to 13,
The transmitter 15 converts the combined signal into a radio frequency and outputs it. The converted signal is transmitted from the antenna 16 to the transmitter 2 as a radio wave. Let this electric wave be V.

The hybrid circuit 24 on the H polarization side also synthesizes the signals output from the modulators 21 to 23 and outputs the combined signal.
The transmitter 25 converts the combined signal into a radio frequency and outputs it. The converted signal is transmitted from the antenna 26 to the transmitter 2 as a radio wave. Let this electric wave be H.

However, it is assumed that the transmitters 15 and 25 are in local synchronization like the demodulator. The transmitter 2 includes an antenna 45 on the V polarization side, a receiver (Rx) 46,
Hybrid circuit (H) 47 for signal branch, demodulator (DE
M) 48, 49, 50, adders 51, 52, 53, and cross polarization interference compensator (XPIC) 54, 55, 56.
And an antenna 57 on the H polarization side, a receiver (Rx) 58, a signal branching hybrid circuit (H) 59, a demodulator (DE
M) 60, 61, 62, adders 63, 64, 65, and cross polarization interference compensators (XPIC) 66, 67, 68.

On the V polarization side, when the radio wave V transmitted by the antenna 45 is received, it is converted into an intermediate frequency by the receiver 46, and the hybrid circuit 47 converts the frequencies f ₁ and f.
_Two branches are made for every ₂ and f ₃ . Each of the demodulators 48 to 50 reverses its operation to the modulators 11 to 13 so that each of the frequencies f ₁ , f ₂ , f
The analog signal of ₃ is demodulated into a digital signal (data) of frequency f ₀ and output.

Similarly, on the H polarized wave side, the antenna 57
When the radio wave H transmitted at is received, the receiver 58 splits it into _three frequencies f ₁ , f ₂ , and f ₃ . Each demodulator 6
0 to 62 demodulate analog signals of frequencies f ₁ , f ₂ and f ₃ into digital signals (data) of frequency f ₀ and output them by the reverse operation of the modulators 21 to 23.

When the data output from the demodulators 48 to 50 and 60 to 62 are normally transmitted without being affected by fading during wireless transmission, the data are output to the adders 51 to 53 and 63 to 65 as they are. Through the same frequency f ₀
Are output as single carriers S and S '.

However, when there is an influence of fading or the like, the single carriers S and S'cannot be properly demodulated in the demodulators 48 to 50 and 60 to 62.
In this case, XPIC 54-56 and 66-68 modify it to the proper one.

The XPICs 54 to 56 and 66 to 68 are for canceling the leakage when the transmitted V polarization and H polarization are slightly interfered by the influence of fading or the like. Further, in order to operate XPIC, the transmitter 1 side must be in local synchronization. This is because the signals on the different polarization side cannot be generated by XPIC unless they are synchronized.

For example, it is assumed that there is a leak from the V polarized wave side to the H polarized wave side. When the leak amount is ΔV, the H polarization side is H + ΔV. In this case, the demodulator 6 on the H polarization side
Data of H + ΔV is output from 0 to 62, and data of V is output from the demodulators 48 to 50 on the V polarization side.

That is, the V data output from the demodulator 48 is input to the XPIC 66 on the H polarization side. The XPIC 66 produces −ΔV from the V and outputs it. H is output by adding the −ΔV and H + ΔV by the adder 63. That is, the single carrier S'is output. Other XPIC
The same is true for.

[0031]

By the way, in the above-described multiplex radio modulation / demodulation apparatus, the V-polarization side and the H-polarization side have to be locally synchronized on the modulation side (transmission apparatus) 1. As shown in 11, each modulator 1
1-13 and 21-23 and each transmitter 15 and 25 must be connected. In order to synchronize, P is set for each of the demodulators 21 to 23 on the slave side and the transmitter 25.
An LL circuit is required.

That is, there is a problem that the number of connections between devices increases and the size of each circuit increases, so that the size of the entire device increases. This becomes more remarkable as the number of divisions of the single carrier increases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multiplex radio modulation / demodulation apparatus which can be downsized as a whole.

[0034]

A multiplex radio modulator / demodulator according to the first principle of the present invention will be described with reference to FIG. The multiplex radio modulator / demodulator modulates each of a first single carrier S on the V polarization side and a second single carrier S ′ on the H polarization side having an orthogonal frequency with the V polarization side and having the same frequency f _0. A plurality of modulators on the V polarization side and a plurality of modulators on the H polarization side to be divided, and respective frequencies f ₁ output from the plurality of modulators,
After synthesizing a plurality of divided carriers in which f ₂ and f ₃ have a multiplication relationship for each of the V polarization side and the H polarization side, the radio frequency f
A modulator having a transmitter on the V polarization side and a transmitter on the H polarization side for converting into _RF and transmitting the signal, and the V transmitted from the modulator.
The demodulation device performs cross-polarization interference compensation processing in which demodulation is performed while compensating the mutual influence of radio signals on the polarization side and the H polarization side. Signal synchronization is established between a plurality of wave-side modulators, and signal synchronization is established between the V polarization side and H polarization side transmitters.

The characteristic of the first principle is that an oscillator 71 outputs a signal of frequency f _{M1 which is} the greatest common divisor of the carrier frequencies f ₁ , f ₂ and f ₃ described above, and a frequency f of the signal output from the oscillator 71. _M1 is multiplied to output signals of the same frequency f ₁ , f ₂ , f ₃ as each carrier frequency, and the output signals of frequencies f ₁ , f ₂ , f ₃ are modulated by a plurality of V-polarized waves. a first multiplying circuit 72 to be output to the vessel 73,74,57, a PLL circuit 79 and outputting the locked frequency f _M1 of the signal output from the oscillator 71, the frequency f _M1 of the signal output from the PLL circuit 79 To output signals of the same frequency f ₁ , f ₂ , f ₃ as each carrier frequency, and output the signals of the frequencies f ₁ , f ₂ , f ₃ to a plurality of modulators on the H polarization side. And a second multiplication circuit 80 for outputting to 81, 82 and 83 in the above-mentioned modulator. That is, the configuration is such that signal synchronization can be established between the plurality of modulators 73 to 75 and 81 to 83 on the V polarization side and the H polarization side.

A multiple radio modulator / demodulator according to the second principle of the present invention.
The device will be described with reference to FIG. The characteristic of the second principle is that
Each carrier frequency f₁, F₂, F₃And the above
Line frequency f_RFFrequency f of the greatest common divisor of_M2Output the signal
Of the oscillator 101 and the signal output from the oscillator 101
Frequency f_M2Each carrier frequency and radio frequency
Same frequency as₁, F₂, F₃, F_RFOutput the signal
Output frequency f of₁, F₂, F₃, F_RFSignal of
Output to a plurality of modulators 73 to 75 and transmitter 77 on the V polarization side.
Output from the oscillator 101.
Signal frequency f_M2Circuit that locks and outputs
79 and the frequency f of the signal output from the PLL circuit 79
_M2To the same frequency as each carrier frequency and radio frequency
Number f₁, F₂, F₃, F_RFOutput the signal of
Frequency f₁, F₂, F ₃, F_RFSignal on the H polarization side
Output to the plurality of modulators 81 to 83 and the transmitter 86 of the
The above-mentioned modulator is equipped with a doubling circuit 103, and
Wave-side and H-polarized wave side modulators 73 to 75 and 81 to 8
Signal synchronization between 3 and between transmitters 77 and 86
Is configured.

A multiplex radio modulator / demodulator according to the third principle of the present invention will be described with reference to FIG. The feature of the third principle is that any one of the above-mentioned carrier frequencies f ₁ , f ₂ , and f ₃
One of the outputs a signal of a frequency (e.g., f _1), an oscillator 111 which outputs a signal of the output frequency f _1, the V polarization side modulator 73 for outputting a carrier frequency f ₁ and the frequency f ₁ And a _first frequency dividing circuit 112 for dividing the frequency f ₁ of the signal output from the oscillator 111 into a frequency f _M1 having the greatest common divisor of the carrier frequencies f ₁ , f ₂ , f ₃ , and a first frequency dividing circuit 112. The frequency f _M1 of the signal output from the circuit 112 is multiplied to obtain the frequency f _{1 of the} signal output from the oscillator 111.
Other than the carrier frequencies, signals of the same frequencies f ₂ and f ₃ are output, and the output signals of the frequencies f ₂ and f ₃ are output on the V polarization side where the oscillator 111 previously output the signal of the frequency f ₁ . a first multiplier circuit 114 for outputting to the modulator 74 and 75 other than the modulator 73 outputs a frequency f ₁ and the frequency f ₁ of the signal output from the oscillator 111, the signal of the output frequency f ₁ , The PLL circuit 7 for outputting to the modulator 81 on the H-polarized wave side which outputs the carrier of the frequency f ₁ and the same frequency f _1.
9 and the frequency f _{1 of the} signal output from the PLL circuit 79.
The multiplication with the carrier frequency f _1, f _2, f second frequency divider 113 for frequency f _M1-divided greatest common divisor of _3, a frequency f _M1 of the signal output from the second frequency divider 113 Then, signals having the same frequencies f ₂ and f ₃ as carrier frequencies other than the frequency f _{1 of the} signal outputted from the oscillator 111 are outputted, and the outputted signals having the frequencies f ₂ and f ₃ are outputted to the PLL.
The above-mentioned modulator is provided with the second multiplication circuit 102 in which the circuit 79 outputs the signal of the frequency f ₁ to the modulators 82 and 83 other than the modulator 81 on the H-polarized wave side which has previously output the signal of the V-polarized wave side. And, the signals are synchronized between the plurality of modulators 73 to 75 and 81 to 83 on the H polarization side.

A multiplex radio modulator / demodulator according to the fourth principle of the present invention.
The device will be described with reference to FIG. The feature of the fourth principle is that
Each carrier frequency f₁, F₂, F₃Any one of
One frequency (eg f₁) Signal is output.
Frequency f₁Signal of frequency f₁Same frequency as₁of
Output to the modulator 73 on the V polarization side that outputs the carrier
Frequency of signal output from oscillator 111 and oscillator 111
Number f₁Is the carrier frequency f₁, F₂, F₃And the above
Radio frequency f_RFFrequency f of the greatest common divisor of_M3Divide into
Output from the first frequency dividing circuit 120 and the first frequency dividing circuit 120
The frequency f of the signal_M3From the oscillator 111
Frequency f of output signal₁Carrier frequencies other than
Same frequency as radio frequency f₂, F₃, F_RFOutput signal
And this output frequency f₂, F₃, F_RFSignal of
The frequency of the oscillator 111 is f first. ₁V polarization that outputs the signal
Modulators 74 and 75 other than the modulator 73 on the side and the transmitter 77
Output from the first multiplication circuit 122 and the oscillator 111.
Frequency f of the applied signal₁Locked and output
Forced frequency f₁Signal of frequency f₁Same frequency as
₁Output to the modulator 81 on the H polarization side that outputs the carrier of
PLL circuit 79 and the signal output from the PLL circuit 79.
Frequency f₁Is the carrier frequency f ₁, F₂, F₃
And radio frequency f_RFFrequency f of the greatest common divisor of_M3Divide into
Output from the second frequency dividing circuit 121 and the second frequency dividing circuit 121
The frequency f of the signal_M3From the oscillator 111
Frequency f of output signal₁Carrier frequencies other than
Same frequency as radio frequency f₂, F₃, F_RFOutput signal
And this output frequency f ₂, F₃, F_RFSignal of
The PLL circuit 79 first outputs the frequency f₁H bias that outputs the signal
Modulators 82 and 83 other than wave-side modulator 81 and transmitter 1
The second multiplication circuit 123 for outputting to the
And a plurality of modulators 73 on the V polarization side and the H polarization side.
Between ~ 75 and 81-83 and between transmitters 11 and 104
It is configured so that issue synchronization can be achieved.

[0039]

According to the above-mentioned first principle, multi-carrier synchronization can be achieved by one PLL circuit 79. In the conventional example, it is necessary to provide a PLL circuit for each modulator 81, 82, 83 on the H polarization side. Therefore, although the multiplying circuits 72 and 80 are required, the overall size can be considerably reduced as compared with the conventional one.

Further, according to such a configuration, it is divided into
One PLL circuit 79, regardless of the number of carriers
Multi-carrier (frequency f₁，
f₂, F ₃) Can be synchronized, so carry
It is more effective as the number of divisions of S and S'increases.

In the second principle, the multiplication circuits 102, 1
In addition to the signals of the frequencies f ₁ , f ₂ , f ₃ output to the demodulators 73-75, 81-83, the transmitters 77, 10
Since the signal of the frequency f _RF to be output to 4 can be created, the PLL circuit is not required in the transmitter on the H polarization side which has conventionally been the slave side. That is, the transmitter 104 on the H-polarized wave side in FIG. 5 is smaller than the transmitter 85 shown in FIG. 1, and the entire size can be made smaller than the first principle.

In the third principle, the signal frequencies f ₁ , f ₂ and f output from the demodulators 73 to 75 or 81 to 83 are used.
Any one of ₃ is output from the oscillator 111, and the oscillator 1
The signal frequency (for example, f ₁ ) output from 1 is divided by the frequency dividing circuits 112 and 113 into the frequency f _M1 having the greatest common divisor of the frequencies f ₁ , f ₂ , and f ₃ , and the frequency f _M1 is multiplied. The remaining frequencies f ₂ and f ₃ by 114 and 115
Since it is configured to be multiplied by, it is possible to reduce the size as a whole in substantially the same manner as the first principle.

In the fourth principle, the signal frequencies f ₁ , f ₂ and f output from the demodulators 73 to 75 or 81 to 83 are used.
Any one of ₃ is output from the oscillator 111, and the oscillator 1
The signal frequency (for example, f ₁ ) output from 1 is divided by the frequency dividing circuits 120 and 121 into the frequency f _M3 which is the greatest common divisor of the frequencies f ₁ , f ₂ , f ₃ and the radio frequency f _RF .
Since the frequency f _M3 is multiplied by the frequency multiplication circuits 122 and 123 to the remaining frequencies f ₂ , f ₃ and f _RF , the PLL circuit is used in the transmitter on the H polarization side which is the slave side. No longer needed. That is, the entire size can be made smaller than that of the third principle.

[0044]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram of a demodulation device (transmission device) in a multiplex radio modulation / demodulation device according to a first embodiment of the present invention. However, the single carriers S and S'input to this demodulator are the same as those described in the conventional example, and the demodulator (receiver) is the same as that of the conventional example shown in FIG.
Are the same as those indicated by reference numeral 2.

The transmitter 70 shown in FIG. 1 includes an oscillator 71 on the V polarization side, a multiplication circuit 72, modulators 73, 74 and 75, a signal combining hybrid circuit 76, a transmitter 77, an antenna 78, and an H polarization. Wave-side PLL circuit 79, multiplication circuit 8
0, modulators 81, 82, 83, a signal combining hybrid circuit 84, a transmitter 85, and an antenna 86.

The oscillator 71 outputs a signal of a frequency f _M1 which is the greatest common divisor of the carrier frequencies f ₁ , f ₂ and f ₃ output from the modulators 73 to 75. The multiplication circuit 72 determines the frequency f _{M1 of the} signal output from the oscillator 71.
To output signals of frequencies f ₁ , f ₂ and f ₃ and have a configuration as shown in FIG. Also,
The multiplication circuit 80 also has the same configuration.

In FIG. 2, 87 is a limiter amplifier for amplifying the signal of the frequency f _M1 output from the oscillator 71, which can be realized by an amplifier having a large gain. 88-9
0 is a bandpass filter. Bandpass filter 8
Of the harmonics output from the limiter amplifier 87, 8 passes the one having the frequency f ₁ , the bandpass filter 89 passes the one having the frequency f ₂ , and the bandpass filter 90.
Allows the frequency f ₃ to pass.

For example, the frequency f _M1 of the output signal of the oscillator 71
Is 10 MHz, frequency f _{1 of} 10 MHz, frequency f _{2 of} 20 MHz, frequency f of 30 MHz
₃ is output.

The demodulators 73 to 75 shown in FIG. 1 are constructed as shown in FIG. Further, the demodulators 18 to 83 also have the same configuration. The modulator shown in FIG. 3 is a D / A converter 9
1, 92, mixers 93 and 94, a 90-degree hybrid circuit 95, an in-phase combining hybrid circuit 96, and an amplifier 37.

The D / A converters 91 and 92 convert the single carrier S input as data into an analog signal and output it. The hybrid circuit 95 sets the phase of the signal of the frequency f ₁ or f ₂ or f ₃ output from the multiplication circuit 72 to 0 ° and 90 °, that is, outputs a phase difference of 90 ° to the mixers 93 and 94. To do.

The mixers 93 and 94 mix the signal output from the hybrid circuit 95 and the signals output from the D / A converters 91 and 92 and output the mixed signal. The hybrid circuit 96 synthesizes the signals output from the mixers 93 and 94 and outputs the combined signal. Thereby, quadrature amplitude modulation is performed.

The signal output from the hybrid circuit 96 is amplified by the amplifier 97 and output. by this,
The amplifier 97 outputs a signal of frequency f ₁ or f ₂ or f ₃ .

The hybrid circuit 76 shown in FIG. 1 has frequencies f ₁ , f ₂ and f ₃ output from the modulators 73 to 75.
The signal of is combined and output. The output signal is converted into a radio frequency by the transmitter 77 and output from the antenna 78.

The PLL circuit 79 has a structure as shown in FIG. The PLL circuit shown in FIG. 4 is a phase detector (P
D) 98, a low pass filter 99, and a voltage controlled oscillator 100.

The phase detector 98 detects a phase error between the signal of the frequency f _M1 output from the oscillator 71 and the signal output from the voltage controlled oscillator 100, and the error is passed through the low pass filter 99 to the voltage controlled oscillator. The loop configuration is such that 100 is supplied. That is, the signal is locked at the frequency f and the signal of the frequency f is output. The hybrid circuit 84 shown in FIG. 1 includes modulators 81 to 83.
The signals of the frequencies f ₁ , f ₂ , and f ₃ output from are combined and output.

The output signal is converted into a radio frequency by the transmitter 85 and output from the antenna 86.
However, between the transmitters 77 and 85, 77 is the master side and 85
Are on the slave side and are in local synchronization with each other.

According to the configuration of the first embodiment described above, 1
One PLL circuit 80 can synchronize multicarriers. In the conventional example, it was necessary to provide a PLL circuit for each modulator on the H polarization side.

Although the multiplying circuits 72 and 80 are required, the size can be considerably reduced as compared with the conventional one as a whole. Further, according to such a configuration, since one PLL circuit 79 can synchronize multi-carriers regardless of the number of divided carriers, it is effective as the number of divided carriers increases.

Next, a second embodiment will be described with reference to FIG. However, in each part of the second embodiment shown in FIG.
The same parts as those of the first embodiment shown in FIG.

The second embodiment shown in FIG. 5 is different from the first embodiment in that the radio frequency f _RF of the transmitter is also produced by the multiplier circuit, which is different from the first embodiment in configuration. Is an oscillator 101, multiplication circuits 102 and 103, and H
And the transmitter 104 on the polarization side.

The oscillator 101 is provided from each modulator 73 to 75.
Output carrier frequency f₁, F ₂, F₃And the transmitter
Radio frequency f of 77_RFFrequency f which is the greatest common divisor of_M2
The signal of is output.

The multiplication circuit 102 multiplies the frequency f _M2 of the signal output from the oscillator 101 to generate frequencies f ₁ , f ₂ ,
It outputs signals of f ₃ and f _M2 , and has a configuration as shown in FIG. Further, the multiplication circuit 103 also has the same configuration.

In FIG. 6, 106 is a limiter amplifier for amplifying the signal of frequency f _M2 output from the oscillator 101. Reference numerals 106 to 109 are bandpass filters.
The bandpass filter 106 allows _one of the harmonics output from the limiter amplifier 105 to have a frequency of f ₁ ,
The bandpass filter 107 passes the frequency f _{2 and} the bandpass filter 108 passes the frequency f _{3 and} the bandpass filter 109 passes the frequency f _RF .

In this way, the multiplication circuit 1 also applies to the radio frequency f _RF.
Since it is possible to output from 02 and 103, the PLL circuit is not required in the transmitter on the H polarized wave side which is the slave side.

That is, the transmitter 104 on the H polarization side of FIG.
Is smaller than the transmitter 85 shown in FIG. As a result, the second embodiment can be made more compact than the first embodiment.

Next, a third embodiment will be described with reference to FIG. However, in each part of the third embodiment shown in FIG.
The same parts as those of the first embodiment shown in FIG.

The third embodiment shown in FIG. 7 is the demodulators 73-7.
5 or signal frequency f output from 81 to 83₁，
f₂, F₃Of the oscillator 111,
The signal frequency output from the oscillator 11 (for example, f₁)
Is divided by the frequency dividing circuits 112 and 113 into a frequency f₁, F
₂, F₃Frequency f of the greatest common divisor of_M1Frequency divided by
Number f _M1The frequency of the remaining frequency
f₂, F₃It is configured to be multiplied by.

However, the configurations of the multiplying circuits 114 and 115 are as shown in FIG. In FIG. 8, the harmonic of the frequency f ₂ of the signal of the frequency f _M1 amplified by the limiter amplifier 116 passes through the low pass filter 117,
The harmonic wave of the frequency f ₃ passes through the low pass filter 118.

With this structure, the entire circuit can be downsized, as in the first embodiment.
Next, a fourth embodiment will be described with reference to FIG. However, in each part of the fourth embodiment shown in FIG. 9, the same parts as those of the third embodiment shown in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted.

The fourth embodiment shown in FIG. 9 is a demodulator 73-7.
5 or 81 to 83 output signal frequency f ₁ ,
Either one of f ₂ and f ₃ is output from the oscillator 111,
Signal frequency output from oscillator 11 (eg f ₁ )
Are divided by the frequency dividing circuits 120 and 121 into frequencies f ₁ , f
Frequency f _M3 of the greatest common divisor between ₂ , f ₃ and radio frequency f _RF
And frequency f _M3 is multiplied by the frequency multiplication circuits 122 and 123 to the remaining frequencies f ₂ , f ₃ and f _RF .

With this configuration, the PLL circuit is not required in the H-polarized wave side transmitter, which is the slave side. That is, the transmitter 104 on the H polarization side of FIG.
It is smaller than the transmitter 85 shown in FIG.

Therefore, the fourth embodiment can be made smaller than the third embodiment.

[0073]

As described above, according to the multiplex radio modulation / demodulation device of the present invention, there is an effect that the entire device can be downsized by reducing the circuit components, and the cost can be reduced. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a modulator in a multiplex radio modulator / demodulator according to a first embodiment of the present invention.

FIG. 2 is a block configuration diagram of a multiplication circuit shown in FIG.

FIG. 3 is a block configuration diagram of a demodulator in the example.

FIG. 4 is a block configuration diagram of a PLL circuit according to an embodiment.

FIG. 5 is a block configuration diagram of a modulator in a multiplex radio modulator / demodulator according to a second embodiment of the present invention.

FIG. 6 is a block configuration diagram of the multiplication circuit shown in FIG.

FIG. 7 is a block diagram of a modulator in a multiplex radio modulator / demodulator according to a third embodiment of the present invention.

FIG. 8 is a block configuration diagram of the multiplication circuit shown in FIG.

FIG. 9 is a block configuration diagram of a modulator in a multiplex radio modulator / demodulator according to a third embodiment of the present invention.

FIG. 10 is an explanatory diagram of carriers handled by the multiplex radio modulator / demodulator.

FIG. 11 is a block configuration diagram of a modulator in a conventional multiplex radio modulator / demodulator.

12 is a block diagram of the modulator shown in FIG. 11. FIG.

[Description of Reference Signs] 71 oscillator 72 first multiplication circuit 73 to 75 V polarization side modulator 77 V polarization side transmitter 79 PLL circuit 80 second multiplication circuit 81 to 83 H polarization side modulator 85 H Polarization side transmitter

Claims (4)

[Claims] 1. A first single carrier (S) on the V-polarized wave side and a second single carrier (S ') on the H-polarized wave side, which is in an orthogonal relationship with the V-polarized wave side and has the same frequency (f ₀ ). A plurality of modulators on the V polarization side and a plurality of modulators on the H polarization side, which are each modulated and divided into a plurality of frequencies, and respective frequencies output from the plurality of modulators.
Vs which are transmitted after being converted into a radio frequency (f _RF ) after synthesizing each of the plurality of divided carriers in which (f ₁ , f ₂ , f ₃ ) have a multiplication relationship for each of the V polarization side and the H polarization side While compensating for the mutual influence of a modulator having a transmitter on the polarization side and a transmitter on the H polarization side and radio signals on the V polarization side and the H polarization side transmitted from the modulator, respectively. And a demodulation device for performing cross-polarization interference compensation processing for demodulation.
In a multiplex radio modulator / demodulator configured to synchronize signals between a plurality of modulators on the polarization side and the H polarization side and to synchronize signals between transmitters on the V polarization side and the H polarization side, wherein an oscillator (71) for outputting a signal greatest common divisor of the frequency of each carrier frequency _{(f 1, f 2, f} 3) (f M1), the signal output from the oscillator (71) frequency (f _M1 ) multiplies the in each carrier frequency in the same frequency (f _1, f _2, and outputs a signal f _3), a signal of the output frequency (f _1, f _2, f _3), V polarization side First output to multiple modulators (73,74,75)
A multiplication circuit (72), a PLL circuit (79) that locks and outputs the frequency (f _M1 ) of the signal output from the oscillator (71), and a frequency of the signal output from the PLL circuit (79) ( by multiplying the f _M1) outputs a signal of each carrier frequency in the same frequency _{(f 1, f 2, f} 3), a signal of the output frequency _{(f 1, f 2, f} 3) the H-polarized By providing the modulator with a second multiplier circuit (80) for outputting to the plurality of wave-side modulators (81, 82, 83), a plurality of modulators on the V polarization side and the H polarization side ( 73,74,75 and 81,8
2.83) A multiplex radio modulator / demodulator characterized by enabling signal synchronization between the two. 2. A first single carrier (S) on the V polarization side and a second single carrier (S ') on the H polarization side having the same frequency (f ₀ ) and having an orthogonal relationship with the V polarization side. A plurality of modulators on the V polarization side and a plurality of modulators on the H polarization side, which are each modulated and divided into a plurality of frequencies, and respective frequencies output from the plurality of modulators.
Vs which are transmitted after being converted into a radio frequency (f _RF ) after synthesizing each of the plurality of divided carriers in which (f ₁ , f ₂ , f ₃ ) have a multiplication relationship for each of the V polarization side and the H polarization side While compensating for the mutual influence of a modulator having a transmitter on the polarization side and a transmitter on the H polarization side and radio signals on the V polarization side and the H polarization side transmitted from the modulator, respectively. And a demodulation device for performing cross-polarization interference compensation processing for demodulation.
In a multiplex radio modulator / demodulator configured to synchronize signals between a plurality of modulators on the polarization side and the H polarization side and to synchronize signals between transmitters on the V polarization side and the H polarization side, An oscillator (101) that outputs a signal of a frequency (f _M2 ) that is the greatest common divisor of the carrier frequencies (f ₁ , f ₂ , f ₃ ) and the radio frequency (f _RF ) and that is output from the oscillator (101). The frequency (f _M2 ) of the signal to be multiplied is multiplied by each carrier frequency and the same frequency as the radio frequency.
The signals of (f ₁ , f ₂ , f ₃ , f _RF ) are output, and the signals of the output frequencies (f ₁ , f ₂ , f ₃ , f _RF ) are output to a plurality of modulators on the V polarization side. (73,74,75) and 1st multiplier circuit to output to transmitter (77)
(102), and the frequency of the signal output from the oscillator (101) (f _M2) PLL circuit to lock to output (79), said PLL circuit (79) the signal of the frequency output from the (f _M2 ) Is output and signals of the same frequency (f ₁ , f ₂ , f ₃ , f _RF ) as each carrier frequency and the radio frequency are output, and the output frequencies (f ₁ , f ₂ , f ₃ , f _{3 By} providing the modulator with a second multiplier circuit (103) for outputting a signal of _RF ) to a plurality of modulators (81, 82, 83) on the H polarization side and a transmitter (86), V Multiple modulators for polarization and H polarization (73,74,75 and 81,8
2,83) and a transmitter / receiver (77 and 86) so that signal synchronization can be achieved. 3. A first single carrier (S) on the V polarization side and
It is orthogonal to the V polarization side and has the same frequency (f₀) H polarization side
The second single carrier (S ') of
Multiple modulators on the V polarization side and multiple modulations on the H polarization side.
Frequency output from the modulator and multiple modulators
(f₁， F₂， F₃) Has a multiplication relationship,
After combining the rear for each V polarization side and H polarization side,
Number (f_RF) Each of the V polarization side and the H polarization side for transmission
A modulator having a transmitter, and transmitted from the modulator.
Wireless signals on the V polarization side and the H polarization side
Cross-polarization interference compensation processing that demodulates while compensating for the effects of
And a V demodulator for
Signal synchronization between multiple modulators on the polarization side and H polarization side
Along with this, signal synchronization is established between the transmitters on the V polarization side and the H polarization side.
In the multiplex radio modulator / demodulator configured as described above, each carrier frequency (f₁， F₂， F₃) Any one of
Frequency (for example f₁) Output the signal
Frequency (f₁) Signal at the frequency (f₁) And the same frequency (f₁) Key
Oscillation output to the modulator (73) on the V polarization side that outputs a carrier
And the frequency (f) of the signal output from the oscillator (111).₁)
Each carrier frequency (f₁， F₂， F₃) Frequency of greatest common divisor of
(f_M1) And the frequency of the signal output from the first frequency divider circuit (112)
(f_M1) Is multiplied by the signal output from the oscillator (111)
Frequency of (f₁Other than carrier frequency (f)₂， F₃)
 Of the output frequency (f₂ ， F₃) of
The frequency of the signal (f₁) Output signal
Output to modulators (74, 75) other than the V polarization side modulator (73)
And a frequency (f) of a signal output from the oscillator (111).₁)
Output the frequency (f₁) Signal
Frequency (f₁) And the same frequency (f₁) H polarization output carrier
Side PLL circuit (79) to output to the modulator (81) and the frequency (f of the signal output from the PLL circuit (79)₁),
Each carrier frequency (f ₁， F₂， F₃) Of the greatest common divisor of
Number (f_M1) And the frequency of the signal output from the second frequency dividing circuit (113)
(f_M1) Is multiplied by the signal output from the oscillator (111)
Frequency of (f₁Other than carrier frequency (f)₂， F₃)
 Of the output frequency (f₂ ， F₃) of
The PLL circuit (79) sends the signal to the frequency (f₁) Signal
Output to modulators (82, 83) other than the applied H polarization side modulator (81).
And a second multiplying circuit (115) for applying to the modulator.
As a result, multiple modulators (73,74,75 and 81,8
It is characterized in that signal synchronization can be established between (2,83)
Multiple wireless modem. 4. A first single carrier (S) on the V polarization side and
It is orthogonal to the V polarization side and has the same frequency (f₀) H polarization side
The second single carrier (S ') of
Multiple modulators on the V polarization side and multiple modulations on the H polarization side.
Frequency output from the modulator and multiple modulators
(f₁， F₂， F₃) Has a multiplication relationship,
After combining the rear for each V polarization side and H polarization side,
Number (f_RF) Each of the V polarization side and the H polarization side for transmission
A modulator having a transmitter, and transmitted from the modulator.
Wireless signals on the V polarization side and the H polarization side
Cross-polarization interference compensation processing that demodulates while compensating for the effects of
And a V demodulator for
Signal synchronization between multiple modulators on the polarization side and H polarization side
Along with this, signal synchronization is established between the transmitters on the V polarization side and the H polarization side.
In the multiplex radio modulator / demodulator configured as described above, each carrier frequency (f₁， F₂， F₃) Any one of
Frequency (for example f₁) Output the signal
Frequency (f₁) Signal at the frequency (f₁) And the same frequency (f₁) Key
Oscillation output to the modulator (73) on the V polarization side that outputs a carrier
And the frequency (f) of the signal output from the oscillator (111).₁)
Each carrier frequency (f₁， F₂， F₃) And the radio frequency (f
_RF) Frequency of the greatest common divisor of (f_M3) 1st division round
Path (120) and the frequency of the signal output from the first frequency divider circuit (120)
(f_M3) Is multiplied by the signal output from the oscillator (111)
Frequency of (f₁Other than carrier frequency and radio frequency
Frequency (f₂ ， F₃, f_RF) Output the signal
Frequency (f₂， F₃, f_RF) Signal from the oscillator (111) first.
Frequency (f₁) Other than the V polarization side modulator (73) that output the signal
1st multiplication output to modulator (74,75) and transmitter (77) of
Path (122) and the frequency (f) of the signal output from the oscillator (111).₁)
Output the frequency (f₁) Signal
Frequency (f₁) And the same frequency (f₁) H polarization output carrier
Side PLL circuit (79) to output to the modulator (81) and the frequency (f of the signal output from the PLL circuit (79)₁),
Each carrier frequency (f ₁， F₂， F₃) And the radio frequency
(f_RF) Frequency of the greatest common divisor of (f_M3) To divide the second
The frequency of the signal output from the circuit (121) and the second frequency dividing circuit (121)
(f_M3) Is multiplied by the signal output from the oscillator (111)
Frequency of (f₁Other than carrier frequency and radio frequency
Frequency (f₂ ， F₃, f_RF) Output the signal
Frequency (f₂， F₃, f_RF) Signal to the PLL circuit (79) first.
At frequency (f₁) Output the signal of H polarization side modulator (81) or later
The second multiplication output to the external modulator (82,83) and transmitter (104)
By equipping the modulator with a multiplier circuit (123),
And multiple modulators (73,74,75 and 81,8 for V polarization and H polarization)
Signal synchronization between transmitters (77 and 104)
A multiplex radio modulator / demodulator characterized by the above.