JPH05268183A - Multiplexer circuit and demultiplexer circuit - Google Patents

Abstract

PURPOSE:To deliver a reference signal as well as a main signal to a high speed processing side by allowing a multiplexer circuit to apply parallel/serial conversion to the reference signal in addition to N:1 parallel/serial conversion of an N-channel parallel signal. CONSTITUTION:The multiplexer circuit has an N:1 parallel/serial conversion circuit 12 for a reference signal equal to an N:1 parallel/serial conversion circuit 11 multiplexing an N-parallel signal, applies N:1 parallel/serial conversion to the N-channel of parallel signals to multiplex the signals and applies similarly N:1 parallel/serial conversion to the reference signal to multiplex it. Moreover, the demultiplexer circuit is provided with a shift register section giving a delay from 0-bit to (N-1) bits to a multiplex signal inputted to a frequency division clock generating section generating a 1/N frequency division clock of a usual 1:N serial/parallel conversion circuit 1, an N:1 selector section selecting one of N multiplex signals having the delay in 0-bit to (N-1) bits and giving the selected signal to the 1:N serial/parallel conversion circuit, and a phase comparator section controlling the N:1 selector section depending on the relation of phase between the reference signal and the 1/N frequency division clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer circuit for performing a multiplexing process and a demultiplexer circuit for performing a demultiplexing process in a high speed multiplexing terminal device. In particular, the present invention relates to a multiplexer circuit and a demultiplexer circuit that perform multiplexing processing and demultiplexing processing based on an input reference signal indicating a reference position of an input signal.

[0002]

2. Description of the Related Art An interface (NNI) between a network and a notebook in an optical transmission system is used for future video communication, high-speed digital data communication and other wide band ISDN.
In 1988, CCITT introduced Synchronous Digital Hierarchy (SDH: Synchronous Digital
ierarchy).

The functions of the multiplexing terminal station device in this SDH are roughly classified into demultiplexing processing for performing multiplexing and demultiplexing and signal terminal processing and other terminal station processing. Higher-order group signal STM
-N (STM: Synchronous Transport Module Level
N) multiplexing processing is the basic of SDH, 155.52 Mb / s
The STM-1 signal of N channels is used as a reference, and the STM-1 signal of N channels is multiplexed in byte (8 bits) units, resulting in a speed of N × 156 Mb / s. For this reason, in addition to the N-to-1 bit-to-bit serial-parallel conversion, it is necessary to perform byte conversion processing for rearranging the data series in byte units. Also,
Since the process of separating the multiplexed high-order group signal into the low-order group signal (N channel) is the reverse operation of the multiplexing process,
It is necessary to separate 1 to N for each byte.

The terminal processing in SDH includes terminal processing between multiplexing terminals (intersection), which is 156 Mb / s based processing, and intermediate relay (interrepeater section), which is N × 156 Mb / s based processing. ) End processing.

FIG. 10 shows the configuration of a multiplexing terminal station apparatus that performs such multiplexing terminal station processing. (1) shows the configuration on the multiplexing side, and (2) shows the configuration on the demultiplexing side. In FIG. 10 (1), a low-speed termination processing unit 101 that performs 156 Mb / s base processing.
Performs N-terminal 156Mb / s parallel signals (# 1 to #N) based on a reference clock from within the station, and performs termination processing between the multiplexing terminal stations to generate N-parallel 156Mb / s signals and reference signals. Send out. The byte conversion processing unit 102 uses the low-speed termination processing unit 10
Based on the reference signal from 1, the bit multiplexing unit 103 in the subsequent stage
In N, the N-channel signals are rearranged so that the multiplexed signals are in byte units. Bit multiplexing unit 103
Performs N-to-1 parallel-to-serial conversion of N-channel parallel signals and delivers the reference signal to the high speed side. The high-speed termination processing unit 104 performs termination processing between the intermediate repeaters on the byte-multiplexed N × 156 Mb / s signal based on the reference signal from the bit multiplexing unit 103.

In FIG. 10 (2), the high-speed termination processing unit 11
4 carries out termination processing between the intermediate repeaters with respect to the input N × 156 Mb / s signal, and sends out the reference signal together with the main signal. The bit separation unit 113 performs 1-to-N serial / parallel conversion on the N × 156 Mb / s main signal based on the reference signal from the high-speed termination processing unit 114, and converts the N-channel 156 Mb / s parallel signal. , With reference signal. Byte processing unit 1
12 is N based on the reference signal from the bit separation unit 113.
The rearrangement is performed so that the parallel signals of the channels become byte units. The low-speed termination processing unit 111 performs termination processing between multiplexing terminal stations on N-channel parallel signals (# 1 to #N).

As described above, the multiplexer circuit of the bit multiplexing unit 103 on the multiplexing side needs to perform the N-to-1 parallel-to-serial conversion of the N-channel signal and pass the reference signal to the high-speed side. In addition, the demultiplexer circuit of the bit separation unit 113 on the separation side needs to perform N-to-N serial-to-parallel conversion of the N-channel signal based on the reference signal and pass the reference signal to the low speed side.

[0008]

By the way, in the conventional demultiplexing process in the optical transmission system before SDH, since it is not a byte unit but a bit unit, serial / parallel conversion or parallel / serial conversion performed based on the reference signal. There was no need for.

On the other hand, the multiplexer circuit of the bit multiplexing unit and the demultiplexer circuit of the bit separation unit in SDH realize the function of delivering the reference signal to the high speed side and the low speed side, and the parallel-serial conversion and serial-parallel conversion functions by the reference signal. There is a need to.

An object of the present invention is to provide a multiplexer circuit and a demultiplexer circuit that can perform processing based on an input reference signal.

[0011]

According to a first aspect of the present invention, in a multiplexer circuit including an N-to-1 parallel-to-serial converter that multiplexes N-channel parallel signals, a reference position of the N-channel parallel signals is provided. And a parallel-serial converter for multiplexing the reference signal at the timing of multiplexing the first channel signal of the N-channel parallel signals.

According to a second aspect of the present invention, the multiplexed signal is N
In a demultiplexer circuit including a 1-to-N serial-parallel converter that separates channels into parallel signals, delays the multiplexed signal from 0 bits to (N-1) bits, and
Data shift means for selecting a multiplexed signal having one delay amount and giving it to the 1-to-N serial-parallel converter, a reference signal indicating a reference position of the multiplexed signal, and a 1 / N divided clock inside the circuit. And a control means for selectively controlling the delay amount of the multiplexed signal in the data shift means according to the phase state of.

According to a third aspect of the present invention, in the demultiplexer circuit according to the second aspect, the data shift means is 1 bit, 2 bits, ..., 2 when N = 2 ^k.
A shift register that gives a delay of ^k-1 and k 2-to-1 selectors that select each delay amount are provided, and bits 0 to (N
-1) The configuration is such that a multiplexed signal having any delay amount up to 1 bit is selected.

According to a fourth aspect of the present invention, in the demultiplexer circuit according to the second aspect, the control means generates M 1 / N frequency-divided clocks using the input reference signal as a trigger (2 ^M = N). ), The state of the T flip-flop is judged and the phase of the reference signal and the 1 / N divided clock is compared.

According to a fifth aspect of the present invention, in the demultiplexer circuit according to the second aspect, the input reference signal is given to the 1-to-N serial-parallel conversion section via the data shift means to be separated. Is characterized by.

[0016]

In the multiplexer circuit of the present invention, N-channel parallel signals are N-to-1 parallel-serial converted and multiplexed, and
Similarly, the reference signal can be transferred to the high-speed side in addition to the main signal by N-to-1 parallel-serial conversion and multiplexing.

Further, the demultiplexer circuit of the present invention is
The control means determines the phase state of the reference signal and the 1 / N frequency-divided clock, and controls the phase (delay amount) of the multiplexed signal for the 1-to-N serial-parallel conversion in accordance with the phase state. The parallel-to-N serial / parallel conversion becomes possible and the reference signal can be transferred to the low speed side.

[0018]

1 is a diagram showing the basic configuration of a multiplexer circuit of the present invention having a function of delivering a reference signal to a high speed side.

In the figure, the number of input channels is N, and the input data series of each channel is shown by a suffix after the channel number. For example, the third data sequence of channel 2 is 2-
Set to 3. At this time, the reference signal indicating the reference position of the parallel signal of N channels is input in the same phase as the first data of each channel, that is, 1-1, 2-1, ..., N-1.

This multiplexer circuit is provided with a circuit equivalent to the N-to-1 parallel-to-serial converter circuit 11 for multiplexing N parallel signals for the reference signal in order to pass the reference signal to the high speed side.
The N-to-1 parallel-to-serial converter circuit 12 for the reference signal inputs the reference signal to the first input port (# 1) and inputs the low level (L) to the other input ports (# 2 to #N). To do. Therefore, the reference signal is output in a state of being in phase with the input data 1-1. In the figure, dedicated N to 1 parallel-to-serial conversion circuits are arranged for simplification of description. However, if two circuits for the signal of # 1 can be provided, N for the reference signal can be provided. Parallel-to-parallel conversion circuit 1
No need to input # 2 to #N.

Next, the serial-parallel conversion function using the reference signal will be described. A normal 1-to-N demultiplexer circuit performs separation processing regardless of the phase of an input data series. That is, when the multiplexed signals 1-1 , 2-1, ..., N-1, 1-2 , 2-2, ... Are separated, the first output port (# 1) does not necessarily have the 1-1, 1 The data of −2, ... Is not always output. For this reason, it is necessary to perform a process of switching the output data to a predetermined output port, and a demultiplexer circuit that performs the operation using a shift register and a selector before performing serial-parallel conversion has been proposed (Japanese Patent Application No. 16765
3).

The demultiplexer circuit of the present invention determines the operation of the selector based on the phase relationship between the reference signal and the divided clock generated during serial-parallel conversion. Figure 2
FIG. 3 is a block diagram showing a basic configuration of a demultiplexer circuit of the present invention.

In the figure, the demultiplexer circuit includes a normal 1-to-N serial-parallel conversion circuit 21, a frequency-divided clock generation unit 22 for generating a 1 / N frequency-divided clock, and a 0-bit input multiplexed signal. The shift register unit 23 that delays to (N-1) bits and one to N serial-parallel conversion circuit 21 by selecting one of N multiplexed signals having a delay amount of 0 to (N-1) bits. To N selector unit 24
And a phase comparison section 25 for controlling the selection operation of the N: 1 selector section 24 by judging the phase relationship between the input reference signal and the 1 / N divided clock.

Here, the operation of the demultiplexer circuit of the present invention will be described by taking a one-to-two demultiplexer circuit as an example. FIG. 3 is a diagram showing a configuration (1) of a 1-to-2 serial-parallel conversion circuit and an operation example (2) thereof. In the figure, the input multiplexed signal is delayed by one bit in the D flip-flop 31. The multiplexed signal delayed by 1 bit is input to the D flip-flop 32, and the input multiplexed signal is input to the D flip-flop 33 as it is. Each of the D flip-flops 32 and 33 is a frequency-divided clock given through the T flip-flop 34 and has a 1-bit delay signal and 0.
The bit delay signal is latched and output to the output ports 35 and 36, and 1-to-2 serial-parallel conversion is performed.

Here, the separated signal of channel 1 (1-1,
..) to the first output port (# 1) 35, the phase relationship between the 1-bit delay signal and the divided clock must be in the state shown in FIG. 3 (2). That is, it is necessary to input the signal of channel 1 in synchronization with the rising edge of the divided clock given to the D flip-flop 32 for latch connected to the first output port 35. For this purpose, the data phase input to the serial-parallel conversion circuit must be changed so as to match the divided clock phase.

FIG. 4 shows a 1-bit shift register section and a 2-bit shift register section.
It is a figure which shows the data series of each part of the demultiplexer circuit which has a to-one selector part. In the figure, the 2-to-1 selector section selects and outputs either a selector output having a 1-bit delay difference or a selector output with respect to an input multiplexed signal. Further, although Case 1 and Case 2 are shown depending on the difference of the divided clock phase, the divided clock phase can be determined by performing a phase comparison with the input reference signal.

In case 1, by selecting the selector output, the first output port (# 1) and the second output port (# 1) are selected.
Separated signals of channel 1 and channel 2 can be output to the output port (# 2), respectively. In case 2, by selecting the selector output, the first output port (# 1) and the second output port (# 1) are selected.
The separated signals of channel 1 and channel 2 can be output to 2).

Although the 1: 2 demultiplexer circuit has been described above, the extension of the 1: N demultiplexer circuit can be similarly explained. Next, the function of delivering the reference signal to the low speed side in the demultiplexer circuit will be described. Since the reference signal can be considered in the same way as the signal of channel 1, a similar circuit may be configured separately from the main signal system so that the reference signal is output to the first output port.

FIG. 5 is a block diagram showing the basic configuration of the demultiplexer circuit of the present invention having the function of passing the reference signal to the low speed side. In the figure, a 1-to-N serial-parallel conversion circuit 21, a divided clock generation unit 22, which constitute a main signal system,
The shift register unit 23, the N-to-1 selector unit 24, and the phase comparison unit 25 have the same configurations as those shown in FIG. The configuration in which the reference signal is output to the first output port is similar to that of the shift register unit 23a and the N-to-1 selector unit 24a and 1
It is realized by the N-to-N serial-parallel conversion circuit 21a, and each unit operates in the same manner as the main signal system. The 1-to-N serial-parallel conversion circuit 2
1a has only a first output port, the reference signal is
It is delivered from the output port (# 1) to the low speed side.

The configuration of the multiplexer circuit and the demultiplexer circuit of the present invention will be described below.
FIG. 6 is a block diagram showing an embodiment configuration (8: 1 multiplexer circuit) of the multiplexer circuit of the present invention.

In the figure, the multiplexer circuit of the present embodiment has D flip-flops (DFF) 61 _{1 to} 61.
₁₅ and T flip-flops (TFF) 62 _{1 to} 62
₃ and a 2-input AND circuit (AND) 63 _{1 to} 63 ₁₇ ,
And an 8-input OR circuit (OR) 64.

[0032] DFF61 ₁ ~61 ₉ latches the input signal of the reference signal and the channel 1 to 8, align the signal phase.
The TFFs 62 _{1 to} 62 ₃ generate a 1/8 divided clock. DFF61 _{10 to} 61 ₁₃ and AND 63 _{10 to} 63 ₁₇
Are control signals S1 to S8 for performing 8-to-1 serial-parallel conversion.
To occur. DFF61 ₂ ~61 input signal channels 1-8 latched in _9, AND63 ₂ ~63 ₉ control signals S1~S8 and logical product is taken in, further OR64 8
After taking the logical sum of pair 1, it is shaped by the DFF 61 ₁₅ and output as a multiplexed signal. The reference signal latched in DFF61 _1, as well as the input signal of the channel 1, is taken control signal S1 and the logical product in AND63 _1, D
The data is shaped by the FF61 ₁₄ and output. This reference signal is
Since the multiplexed signal is output in the same phase as the channel 1 signal, the reference signal can be delivered to the high speed side.

FIG. 7 is a block diagram showing an embodiment configuration (one-to-two demultiplexer circuit) of the demultiplexer circuit of the present invention. In the figure, the demultiplexer circuit of the present embodiment has D flip-flops (DFF) 71 _{1 to} 71 _10.
And a D flip-flop (SDF) 7 with a 2: 1 selector
2 _{1-72 2,} constituted by a T flip-flop (TFF) 73. The SDF 72 selects the signal of the input port D1 when the control signal S is at the low level (L), and selects the signal of the input port D2 when the control signal S is at the high level (H).

The DFFs 71 ₁ and 71 ₂ and the SDF 72 ₁ are
The shift register unit of 0 to 1 bit and the 2-to-1 selector unit described in FIG. 2 are configured. The TFF 73 constitutes a 1/2 divided clock generation unit. DFF71 ₃ ~71 ₅ constitute a pair 2 parallel conversion circuit described in FIGS. The DFFs 71 _{7 to} 71 ₁₀ and the SDF 72 _{2 form} the shift register unit for the reference signal, the 2: 1 selector unit and the 1: 2 serial-parallel conversion circuit described in FIG. DFF71
Reference numeral ₆ constitutes a phase comparison unit for comparing the phase states of the reference signal and the 1/2 frequency-divided clock output from the TFF 73.

The multiplexed signal is input to the DFF 71 ₁ , the reference signal is input to the DFF 71 ₈ and the DFF 71 ₁ is input.
Input to ₆ clock input terminal. DFF71 ₆ is,
The reference signal is used to latch the 1/2 frequency-divided clock. As a result, the phase state of the reference signal and the 1/2 divided clock is D
FF71 becomes the output of _6. The inverted signal of this output causes S
Controls the DF72 ₁ and 72 _2, and controls the DFF 71 ₁ or D
0-bit delay signal output from FF71 ₈ or DFF
71 ₂ or a 1-bit delay signal output from the DFF 71 ₉ is selected, and the corresponding signal sequence is delivered to the 1-to-2 serial-parallel conversion circuit in the next stage. The subsequent operation is as described with reference to FIG. Since the reference signal has the same phase as the channel 1 signal of the multiplexed signal, the first output port (#
It is configured to be output through the same path as the signal of 1).

FIG. 8 is a block diagram showing an embodiment configuration (1 to 8 demultiplexer circuit) of the demultiplexer circuit of the present invention. In the figure, the demultiplexer circuit of the present embodiment is an extension of the 1: 2 demultiplexer circuit, and includes D flip-flops (DFF _{1 to} DFF ₄₂ ),
D flip-flop with 2-to-1 selector (SDF _{1 to} SD
F ₆ ) and T flip-flops (TFF _{1 to} TFF ₃ )
And an exclusive OR circuit (EXOR). The SDF similarly selects the signal of the input port D1 when the control signals S1 to S3 are at the low level (L) and selects the signal of the input port D2 when the control signals S1 to S3 are at the high level (H).

DFF _{1 to} DFF ₈ constitute a 0, _1, 2 and ₄ bit shift register section, and 0 to 7 bit shift register section including SDF ₁ to SDF ₃ and 8 to 1 selector section. .. TFF _{1 to} TFF _{3 form} a 1/8 divided clock generation unit. DFF _{9 to} DFF ₂₃ constitute a 1-to-8 serial-parallel conversion circuit. DFF ₂₇ ~ DFF ₄₂ and SDF
_{4 to} SDF _{6 form} a shift register unit for the reference signal, an 8-to-1 selector unit, and a 1: 8 serial-parallel conversion circuit (however, the output is 1 terminal). DFF _{24 to} DFF ₂₆ and EX
The OR forms a phase comparison unit that compares the phase states of the reference signal and the 1/8 divided clock.

The DFF _{24 to} DFF ₂₆ latch the respective output signals of TFF ₁ to TFF ₃ which generate the ⅛ frequency divided clock with the reference signal. Therefore, 1 /
The phase state of the divided-by-8 clock becomes the output of DFF ₂₄ to DFF ₂₆ . All three outputs control SDF ₁ to SDF _6, and _{one of} 0 bit delay signal to 7 bit delay signal is controlled.
A signal is selected and the corresponding signal sequence is delivered to the 1-to-8 serial-parallel conversion circuit at the next stage. Since the reference signal has the same phase as the channel 1 signal of the multiplexed signal, the first output port (#
It is configured to be output through the same path as the signal of 1).

Here, an example of the data series of each part is shown in FIG. There are eight types of operating states depending on the phase relationship between the 1/8 divided clock generated in the demultiplexer circuit and the reference signal.
It is assumed to have a relationship with FF ₃ . The signals (1-1, 1-2, ...) Of channel 1 of the multiplexed signal are output from the DFF ₂₃ , and the reference signal is output from the DFF _{42. The} serial-parallel conversion function by the reference signal and the reference signal It can be seen that the transfer function to the low speed side is realized.

[0040]

As described above, the multiplexer circuit of the present invention performs parallel-serial conversion of the reference signal in addition to the N-to-1 parallel-serial conversion of N-channel parallel signals, so that the reference signal as well as the main signal is converted into the high-speed side. Can be handed over to. Further, the demultiplexer circuit of the present invention can perform 1-to-N serial-parallel conversion based on the reference signal and can pass the reference signal to the low speed side. Therefore, using these multiplexer and demultiplexer circuits, S
A DH compatible demultiplexer can be configured.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a multiplexer circuit of the present invention.

FIG. 2 is a block diagram showing a basic configuration of a demultiplexer circuit of the present invention.

FIG. 3 is a diagram showing a configuration example of a 1-to-2 serial-parallel conversion circuit and an operation example thereof.

FIG. 4 is a diagram showing a data series of each unit of the demultiplexer circuit of this embodiment.

FIG. 5 is a block diagram showing a basic configuration of a demultiplexer circuit of the present invention.

FIG. 6 is a block diagram showing an embodiment configuration (8: 1 multiplexer circuit) of the multiplexer circuit of the present invention.

FIG. 7 is a block diagram showing an embodiment of a demultiplexer circuit according to the present invention (1
It is a block diagram showing a pair 2 demultiplexer circuit).

FIG. 8 is a block diagram showing an embodiment of a demultiplexer circuit according to the present invention (1
It is a block diagram showing a pair 8 demultiplexer circuit).

FIG. 9 is a diagram showing an example of a data series in a 1-to-8 demultiplexer circuit.

FIG. 10 is a block diagram showing a configuration of a multiplexing terminal device.

[Explanation of symbols]

 11, 12 N-to-1 parallel-serial conversion circuit 21 1-to-N serial-parallel conversion circuit 22 Divided clock generation unit 23 Shift register unit 24 N-to-1 selector unit 25 Phase comparison unit 31 to 33 D flip-flop (DFF) 34 T flip-flop Output port 61, D flip-flop (DFF) 62 T flip-flop (TFF) 63 AND circuit (AND) 64 Logical sum circuit (OR) 71 D flip-flop (DFF) 72 2-to-1 selector D flip-flop (SDF) 73 T flip-flop (TFF) 101 Low speed termination processing unit 102 Byte conversion processing unit 103 Bit multiplexing unit 104 High speed termination processing unit 111 Low speed termination processing unit 112 Byte conversion processing unit 113 Bit separation unit 114 High speed termination Processing unit

Claims (5)

[Claims] 1. A multiplexer circuit including an N-to-1 parallel-to-serial converter that multiplexes N-channel parallel signals, wherein a reference signal indicating a reference position of the N-channel parallel signals is input to the N-channel parallel signals. A multiplexer circuit comprising parallel-serial conversion means for multiplexing the reference signal at the timing of multiplexing the first channel signal of the signals. 2. A demultiplexer circuit including a 1-to-N serial-parallel converter that separates a multiplexed signal into N-channel parallel signals, wherein the multiplexed signal is delayed from 0 bits to (N-1) bits. , A data shift means for selecting a multiplexed signal having the one delay amount and giving it to the 1-to-N serial-parallel converter, a reference signal indicating a reference position of the multiplexed signal, and a 1 / N component inside the circuit. A demultiplexer circuit comprising: control means for selectively controlling the delay amount of the multiplexed signal in the data shift means in accordance with the phase state with the peripheral clock. 3. The demultiplexer circuit according to claim 2, wherein the data shift means has 1 bit when N = 2 ^k ,
A shift register that gives a delay of 2 bits, ..., 2 ^k−1 , and k 2-to-1 selectors that select each delay amount, and any delay amount from 0 bit to (N−1) bits A demultiplexer circuit having a configuration for selecting a multiplexed signal having: 4. The demultiplexer circuit according to claim 2, wherein the control means is a state of ^M (2 ^M = N) T flip-flops which generate a 1 / N frequency-divided clock by using an input reference signal as a trigger. And a phase comparison between the reference signal and the 1 / N divided clock. 5. The demultiplexer circuit according to claim 2, wherein the input reference signal is given to a 1-to-N serial-parallel conversion section via a data shift means to be separated. ..