JPH05268076A - Digital pll device - Google Patents

Abstract

PURPOSE:To provide the digital PLL device having good accuracy in arithmetic operation even when the low-order bit is cut down in an integrating device. CONSTITUTION:The digital PLL device consists of a phase comparison section 1 comparing the phase difference of a digital input signal, digital voltage control oscillator 4, and loop filter 2. The digital voltage control oscillator 4 is of an integrating device made up of an entire adder 7, to which high-order (k) bits of (n) bit outputted by the loop filter 2 are inputted and the code bit of (n)-bit digital signal is inputted to a carry input terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL device using digital signal processing. The resolution of the digital PLL device is determined by the number of bits of the digital signal of the arithmetic processing, and the accuracy of the PLL is improved by increasing the number of bits. However, as the number of bits increases, so does the hardware scale, so there is a trade-off between arithmetic precision and hardware scale. The accuracy is usually determined by the purpose of use of the designed PLL circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional digital PLL device (the number of bits shown in the drawing is merely an example for explanation).

In the figure, 61 is a phase comparator,
The 8-bit digital input signal and 8-bit VCO output signal are input and multiplied, and the higher 8 bits of the 16-bit multiplication result
The bits are output as a phase error.

Reference numeral 62 denotes a second-order loop filter for removing noise, stabilizing the system, and the like. The 8-bit phase error is multiplied by a 16-bit filter coefficient to output a 26-bit loop filter output signal. Is output (the multiplication result of 8 bits and 16 bits becomes 24 bits, but it is set to 26 bits in consideration of the sign bit and carry). 63 is an 8-bit input section, 64 is a filter operation section,
Reference numeral 65 is a 26-bit output section.

A digital VCO 66 outputs a VCO signal corresponding to the output value of the loop filter 62. 66 ′ is an integrator, which is a loop filter 62
The 26-bit loop filter output signal output from is input and added to the loop filter output signal input in the past to perform integration processing. Then, the integrator 66 'outputs the upper 16 bits of the 26 bits of the operation result as the integration result. Reference numeral 67 is a 26-bit input section, and 68 is an integral operation section, which comprises a 26-digit full adder. 69 is a 16-bit output section.

A VCO signal generator 70 generates an 8-bit VCO signal based on the integrated output. The operation of the digital PLL device in FIG. 4 will be described.

The phase comparator 61 receives the 8-bit input signal and the 8-bit VCO signal and multiplies them to obtain a phase error, and inputs the upper 8 bits of the 16-bit operation result to the loop filter 62. .. Filter calculation unit 6
4 performs a filter operation by multiplying an 8-bit phase error by a 16-bit filter coefficient. Then, the loop filter output signal is output as 26 bits in consideration of the sign bit and the carry.

The integrator 66 'receives the 26-bit loop filter output signal, and the integral calculating unit 68 adds it to the past loop filter output signal to perform integral calculation. Then, the integrator 66 'outputs the upper 16 bits of the integration result as an integrated value. VCO signal generator (co
The s-wave ROM) 70 outputs an 8-bit VCO signal according to the integrated value output from the integrator 66 '.

In the case of the conventional digital PLL device as shown in FIG. 4, a loop filter 6 is applied to an 8-bit input signal.
2. Since the integrator 66 'processes 26-bit data, the calculation accuracy is guaranteed. However, since 26-bit data processing is required, a large-scale hardware scale is required. In particular, the integrator 66 'has a 26-digit full adder and F
Since it requires F, it was a heavy burden.

Therefore, conventionally, the number of bits was cut off within an allowable range in which the accuracy can be compensated, and the increase in hardware scale was suppressed. FIG. 5 shows the configuration. In the figure, the integrators 6 and 6'are set to 16 bits, and the lower 10 bits of the output 26 bits of the loop filter output signal are truncated and the integration operation is performed in 16 bits.

In FIG. 5, the 26-digit (26-bit) integral calculator 68 of FIG. 4 is replaced by a 16-digit (16-bit) integral calculator 6.
8 ', except that the 26-bit input section 67 of FIG. 4 is replaced with a 16-bit input section 67', the configuration is the same as that of FIG.

[0012]

Problems to be solved by the invention will be described with reference to FIGS. 6 and 7. FIG. FIG. 6 (a) shows the phase error response. The horizontal axis represents the passage of time, and the vertical axis represents the phase error. As shown in the figure, the phase error converges to 0 with time.

FIG. 6 (b) shows the relationship between the analog voltage value and the digital value when the fractional part is truncated. As shown, between 1.0V and -1.0V (1.0V and -1.0V
Not included, in the figure 0.5V, 0.0V, -0.4V,-
Only 0.7V) has a digital value of 0.

FIG. 3C shows a digital value of 1.0 V to −1.0 V when the decimal point is truncated in the representation of the digital value. If the number after the decimal point is rounded down, from 1.0V-
The digital value must be 0 up to 1.0V (not including 1.0V and -1.0V),
In reality, the negative range is -1 as shown in the figure (in the figure, -0.1V to -0.9V is shown).

The reason for this will be described with reference to FIG.
In FIG. 7, (a) shows an example of the data structure in the case of 8 bits. The most significant bit is the sign bit, 0 is positive,
1 represents negative. The lower 2 bits are the digits after the decimal point.

(B) shows an example of a binary number representation in 2's complement. Normally, a calculator operates by a binary number representation with 2's complement. Then, in the case of the two's complement representation, “−1”
Is represented by "11111111" as shown.

(C) represents a binary number expression when 2 of the decimal number "-0.5" is used as a complement. 6 from the most significant bit
Up to the first digit, "111111" is displayed, and the lower two digits are "10".

(D) represents "-0.5" when the fractional part (lower 2 bits) is truncated. As shown in the figure, if the lower 2 bits after the decimal point are truncated, "-
It becomes “111111” with respect to 0.5 ”.

This is the same as when the lower 2 bits of "-1" are truncated. This means that, when the fractional part is rounded down, the range between 0V and -1.0V (not including 0V) is represented by "-1".

For the above reasons, when the lower bits of the output signal of the loop filter are truncated and processed by the integrator, a large error occurs between 0V and -1.0V (0V is not included). ..

According to the present invention, even when the lower bits are truncated and processed in the integrator, the digital P having a high calculation accuracy is used.
It is an object to provide an LL device.

[0022]

According to the present invention, the sign bit of the loop filter output signal is input to the carry input terminal of the integrator so that the lower bit is truncated to 0V to −.
There was no error between 0.1 (not including 0V).

FIG. 1 shows the basic configuration of the present invention. In the figure, 1 is a phase comparator, 2 is a loop filter,
It outputs an n-bit loop filter output signal. 3 is an n-bit output section.

A digital voltage controlled oscillator (VCO) 4 outputs a VCO signal according to the loop filter output signal. Reference numeral 5 denotes an integrator, which performs an integral operation of k bits (k <n). Reference numeral 5'denotes an integral calculation unit, which has a k-bit full adder, inputs a loop filter output signal, and adds the loop filter output signal to a past loop filter output signal to perform an integral calculation of k bits (k <n). It is something to do. Reference numeral 6 denotes a carry input section in the integrator, which inputs the sign bit of the loop filter output signal. Reference numeral 7 denotes a full adder which inputs the loop filter output signal and adds it to the past loop filter output signal. 8 is a k-bit input section,
The higher k bits of the n-bit loop filter output signal are input. Reference numeral 9 represents the sign bit of the most significant bit of the n-bit signal output from the loop filter 2.

Reference numeral 10 is a VCO signal generating section for generating a VCO signal based on the output value of the integrator.

[0026]

Before explaining the operation of the basic configuration of FIG. 1, the meaning of inputting the sign bit to the carry input section of the integrator will be described with reference to FIG.

In FIG. 2A, 20 is 8-bit data, and the figure shows "-0.
5 ". Reference numeral 21 is a 6-digit full adder, and 22 is a flip-flop (FF), which temporarily holds the output data of the full adder 21 and inputs it to the full adder 21 as past data. The full adder 21 adds the past data and the current data (data 20 in the figure) to obtain an integrated value with respect to time.

The data obtained by discarding the lower 2 bits (decimal point) of the binary representation of "-0.5" is input to the full adder 21, and the most significant code bit is input to the carry input terminal (Ci) of the full adder 21. ).

As shown in FIG. 2B, this means that the full adder has input data (data 20 obtained by discarding the lower 2 bits of "-0.5") and a code bit "1" input as a carry. (21) is added.

As a result, the operation result of the full adder becomes "000000" as shown in the figure, which exactly matches the result of rounding down "-0.5". The operation of the basic configuration of FIG. 1 will be described.

The input signal and the VCO signal are input to the phase comparison unit 1. The loop filter 2 performs a filter operation based on the output of the phase comparison unit 1 and outputs an n-bit loop filter output signal. K-bit input section 8 of integrator 5
Is the upper k of the n-bit loop filter output signal
Enter the bit. On the other hand, the carry input unit 6 of the integrator 5
Input the sign bit of the loop filter output signal to. The full adder 7 adds the input k-bit signal and the value of the sign bit input to the carry input unit 6,
The error of the input data due to the truncation is eliminated, and the integration operation of the k-bit data is performed.

The digital voltage controlled oscillator (VCO) 4 is
A VCO signal is generated based on the output of the integrator 5, and is input to the phase comparison unit 1. In the above configuration, the output signal to the external device is the output of the loop filter 2 or the output of the digital voltage controlled oscillator (VCO) 4.

[0033]

FIG. 3 shows an embodiment of the present invention. In the figure,
Reference numeral 31 is a phase comparison unit, which inputs an 8-bit input signal and an 8-bit VCO signal and multiplies them to obtain the higher 8 bits of the operation result.
The bits are output as a phase error.

Reference numeral 32 denotes a second-order loop filter, which is 8
A bit phase error is input, a 16-bit filter coefficient is multiplied, and a 24-bit operation result is output as a 26-bit loop filter output signal. 33,3
A multiplying unit 4 multiplies an 8-bit phase error by a 16-bit filter coefficient and outputs a 24-bit operation result. Reference numerals 35 and 36 denote addition units which add the 24-bit outputs of the multiplication units 33 and 34 to form a 26-bit loop filter output signal (carry generated by addition result of code bits and absolute value). 26 bits including carry by addition of parts). 37 is a 26-bit output section.

Reference numeral 38 denotes a digital VCO which inputs the loop filter output signal and generates and outputs the VCO signal according to the value thereof. Reference numeral 38 'denotes an integrator, which discards the lower 10 bits of the 26-bit loop filter output signal and inputs the upper 16 bits to perform an integral operation (Ci is a carry input unit). 39 is 16
A bit input unit, 40 is a 16-digit full adder, and 41 is a sign bit of 26-bit data output from the loop filter 32. 42 is a VCO signal generator (cos wave ROM)
Is.

In the configuration shown in the figure, the phase comparison unit 31 inputs an 8-bit input signal and an 8-bit VCO signal, and outputs 8 bits out of the 16-bit multiplication result as a phase error. The loop filter 32 has the multiplication units 33 and 34,
The 8-bit phase error and the 16-bit filter coefficient are respectively multiplied to obtain a 24-bit multiplication result. Adder 35
At 2, the secondary filtering process is performed, and the addition unit 36 adds the calculation result of the multiplication unit 33 and the calculation result of the addition unit 35. At that time, the carry is 26 bits in consideration of the carry by addition of the sign and the carry by addition of the absolute value part. The 26-bit output unit 37 outputs the loop filter output data.

The integrator 38 'inputs the upper 16 bits of the 26-bit data output from the loop filter 32, inputs the sign bit to the carry input terminal, and adds it to eliminate the error due to the truncation. And 1
The 6-digit full adder 40 adds the past loop filter output signal temporarily held in the FF and the current loop filter signal without error, and outputs the integration result in 16 bits.

VCO signal generator (cosROM) 42
Outputs an 8-bit VCO signal based on the 16-bit integration result output from the integrator 38 '. In addition, although the case where the arithmetic processing is performed by the two's complement has been described above, the present invention can be applied to an arithmetic method using another expression.

According to the present invention, the error due to the truncation can be eliminated only by connecting the upper bit line of the parallel signal output from the loop filter to the integrator and inputting the sign bit to the carry terminal of the integrator. Therefore, highly accurate PLL processing can be performed with a small number of bits.

[0040]

The PLL device of the present invention can perform highly accurate integration processing with a small hardware configuration. Also, the method of eliminating the influence of the truncation error is simple, and high calculation accuracy is guaranteed.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is an explanatory view of the operation of the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing a conventional digital PLL device (1).

FIG. 5 is a diagram showing a conventional digital PLL device (2).

FIG. 6 is an explanatory diagram (1) of a problem to be solved by the invention.

FIG. 7 is an explanatory diagram (2) of a problem to be solved by the invention.

[Explanation of symbols]

 1: phase comparison unit 2: loop filter 3: n-bit output unit 4: digital voltage controlled oscillator 5: integrator 5 ': integral calculation unit 6: carry input unit 7: full adder 8: k-bit input unit 9: sign Bit 10: VCO signal generator

Claims (1)

[Claims] 1. A digital PLL device comprising a phase comparator (1) for comparing the phase difference of digital input signals, a digital voltage controlled oscillator (4) and a loop filter (2). ) Is composed of an integrator consisting of a full adder, and inputs the upper k bits of the n bits output from the loop filter (2) and inputs the sign bit of the n bits of the digital signal to the carry input terminal. A digital PLL device characterized by: