JPH05267965A - Time constant circuit - Google Patents

Abstract

PURPOSE:To reduce tertiary higher harmonic distortion in an output signal by providing a buffer amplifying circuit for outputting a level detecting signal and driving a time constant setting circuit, and also, allowing an input signal of the time constant setting circuit to be subjected to negative feedback to an input side. CONSTITUTION:A level detecting signal D being a full-wave rectifying current being proportional to a level of an input signal from a level detecting circuit 4 is impressed to a positive input of an operational amplifier A61 of a buffer amplifier 61. A (b) point of an emitter side of a transistor Q61 is connected to an inversion input of the operational amplifier A61, therefore, a negative feedback circuit of the operational amplifier A61 is constituted. Accordingly, by this negative feedback operation, a variation portion of a base-emitter voltage caused by a variation of an emitter current of the transistor Q61 at the time of charging of a capacitor C61 is absorbed. As a result, a condition that a peak position of a voltage of an (a) point and a peak position of a voltage of the (b) point are always equal to each other is held, therefore, a faithful level control is executed to the level of the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time constant circuit, and more particularly to a time constant circuit for a logarithmic compression and expansion type noise reduction system for audio signals.

[0002]

2. Description of the Related Art A time constant circuit of this type is used in a signal processing circuit of a logarithmic compression and expansion type noise reduction system.

In recent years, noise reduction systems for reducing noises such as tape hiss and receiver noises contained in audio signals are becoming widespread in audio video (AV) devices. As one of these techniques, there is a method based on logarithmic compression and expansion of an audio signal.

FIG. 3 is a block diagram showing an example of a level signal processing circuit which is a main part of a logarithmic compression and expansion type noise reduction system.

As shown in FIG. 3, the level signal processing circuit comprises a signal system filter 1, a level control circuit 2, a control system filter 3, a level detection circuit 4, and a time constant circuit 5. Was there.

Next, the operation will be described. First, the input signal I is divided into two systems and input to the signal system filter 1 and the control system filter 3, respectively. Signal system filter 1
Is suitable for each noise reduction system and gives the input signal I a frequency characteristic necessary for frequency modulation / demodulation. The signal F output from the signal filter 1 is input to the level control circuit 2.

On the other hand, the control system filter 3 removes noise outside the band which is harmful to the detection of the signal level and gives a required frequency characteristic to the input signal I and applies it to the level detection circuit 4 as the signal C. The level detection circuit 4 full-wave rectifies the input signal C and outputs a level detection signal D to output a time constant circuit 6
Apply to. The time constant circuit 6 smoothes the input level detection signal D so as to give an transient response time constant suitable for each noise reduction system, and outputs it to the level control circuit 2 as a DC time constant signal T. The level control circuit 2 sets the level of the signal F input by the time constant signal T and outputs it as an output O.

As shown in FIG. 3, the conventional time constant circuit 5 includes two transistors Q5 having the same structure and the same current density.
1, Q52 and resistor R53, a current mirror circuit 51, resistors R51 and R52, and a capacitor C51.
It was equipped with and.

Next, the operation of the conventional time constant circuit will be described.

FIGS. 5A and 5B are diagrams showing the output waveforms of the high frequency and low frequency, respectively, at points a and b of the current mirror circuit 51.

First, the input signal I from the level detection circuit 4
The level detection signal D, which is a full-wave rectified current proportional to the level of, is input to the current mirror circuit 51. A on the emitter side of the transistor Q51 of the current mirror circuit 51
The full-wave rectified waveform of the level detection signal D is output to the point. Further, a pulsating current waveform obtained by smoothing the full-wave rectified waveform at the point a is output to the point b on the emitter side of the transistor Q52. As is well known, the current mirror circuit 51 includes two transistors Q51 and Q52 having the same structure and current density.
Is used, the base-emitter voltage VBE given by
Have the property that they are equal to each other.

[0012]

Where k is Boltzmann's constant, T is absolute temperature, q is electron charge, IS is reverse saturation current, and IE is emitter current.

Transistor Q of current mirror circuit 51
The emitter of 52, that is, the voltage at point b is smoothed by a time constant circuit composed of a resistor R51 and a capacitor C51, and is supplied to the level control circuit as a time constant signal T of a DC voltage corresponding to the level of the input signal I. It was to be output.

Further, the transient response time constant when the level of the level detection signal D input from the level detection circuit 4 varies is expressed by the following equation.

ΤA = C × R52 τR = C × R (51 + R52) ………………………………………… (2) where τA (attack) is high , ΤR (recovery) indicates a time constant when the level becomes small.

When the voltage at the point a is higher than the voltage at the point b, the emitter of the transistor Q52 is connected to the capacitor C.
An extra charging current of 51 flows. Therefore, FIG. 5 (B)
As shown in, the voltage at the point b at this moment is greater than the voltage at the point a at the base-emitter voltage Δ of the transistor Q52 at this moment.
It decreases by VBE. As a result, the phase of the time constant signal T, which is the output voltage, is apparently delayed by Δφ, which causes an error in the control characteristics of the level control circuit. This error in the control characteristic is distorted near the peak of the control time constant signal T, resulting in an increase in the third harmonic of the output signal O. In the equation (2), since τR (recovery) is constant, a relatively low frequency in which the point pressure fluctuation amount at the point b due to the charging / discharging of the capacitor is large appears more prominently.

[0018]

Since the above-mentioned conventional time constant circuit uses the current mirror circuit in the drive circuit, a difference in the current density of the two transistors causes a difference in the base-emitter voltage. There is a drawback in that the third-order harmonic of the level-controlled output signal increases due to the apparent fluctuation of the phase of the level-controlling signal with respect to the controlled signal.

[0019]

The time constant circuit of the present invention comprises:
A time constant setting circuit having a resistor and a capacitor for setting a predetermined time constant, and a level detection signal which is a full-wave rectified wave signal corresponding to the level of the input signal are input to drive the time constant setting circuit. And a buffer amplifier circuit that negatively feeds back the input signal of the time constant setting circuit to the input side.

[0020]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time constant circuit of the present invention.

As shown in FIG. 1, the time constant circuit 6 of this embodiment includes a buffer amplifier 61, resistors R61 and R62,
And a capacitor C51. The buffer amplifier 61 is configured to include an operational amplifier A61 having two inputs, positive and inverting, and a transistor Q61 having a base connected to the output of the operational amplifier 61 and an emitter connected to the inverting input of the operational amplifier 61.

Next, the operation of this embodiment will be described.

The time constant circuit 6 of this embodiment is used in place of the conventional time constant circuit 5 in the level signal processing circuit which is the main part of the logarithmic compression and expansion type noise reduction system shown in FIG. is there. Therefore,
For the configuration and operation of the entire level signal processing circuit,
It is the same as the one shown in the example of the conventional technology described above,
Since the description is duplicated, it is omitted here.

FIG. 2 shows the operational amplifier A of the buffer amplifier 61.
(A) is a high frequency output waveform at point a on the input side of 61 and b point on the emitter side of the transistor Q61. FIG.

First, the input signal I from the level detection circuit 4
The level detection signal D, which is a full-wave rectified current proportional to the level of, is applied to the positive input of the operational amplifier A61 of the buffer amplifier 61. Since the point b on the emitter side of the transistor Q61 is connected to the inverting input of the operational amplifier A61,
It constitutes a negative feedback circuit of the operational amplifier A61. Therefore, the negative feedback operation of the operational amplifier A61 absorbs the change in the base-emitter voltage VBE due to the change in the emitter current of the transistor Q61 when the capacitor C61 is charged. As a result, as shown in FIG.
Since the condition that the peak position of the voltage at the point and the peak position of the voltage at the point b are equal is maintained, it is possible to perform the level control faithful to the level of the input signal I.

As a result, it is possible to significantly reduce the third harmonic distortion in the output signal O, which has been conventionally generated especially in the low frequency region.

[0028]

As described above, the time constant circuit of the present invention inputs a level detection signal to drive the time constant setting circuit, and at the same time, a buffer amplifier for negatively feeding back the input signal of the time constant setting circuit to the input side. By providing the circuit, the condition that the peak position of the input signal and the peak position of the level control signal are always equal is held, so that the level control faithful to the level of the input signal can be performed, and the output signal There is an effect that the third harmonic distortion can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a time constant circuit of the present invention.

FIG. 2 is a waveform diagram showing an example of the operation of the time constant circuit of this embodiment.

FIG. 3 is a block diagram showing an example of a level signal processing circuit in a noise reduction system using the time constant circuits of this embodiment and a conventional example.

FIG. 4 is a block diagram showing an example of a conventional time constant circuit.

FIG. 5 is a waveform diagram showing an example of operation in a conventional time constant circuit.

[Explanation of symbols]

 1 signal system filter 2 level control circuit 3 control system filter 4 level detection circuit 5,6 time constant circuit 51 current mirror circuit 61 buffer amplifier A61 operational amplifier C51, C61 capacitors Q51, Q52, Q61 transistors R51 to R53, R61, R62 resistance

Claims (2)

[Claims] 1. A time constant setting circuit having a resistor and a capacitor for setting a predetermined time constant, and a level detection signal which is a full-wave rectified wave signal corresponding to the level of an input signal is input to set the time constant. A time constant circuit comprising: a buffer amplifier circuit that drives the circuit and negatively feeds back an input signal of the time constant setting circuit to an input side. 2. The buffer amplifier circuit has a first input terminal of a first polarity for inputting the level detection signal and a second input terminal of a second polarity which is an inverted polarity of the first polarity. 2. An operational amplifier circuit having the same, and a transistor having an output terminal of the operational amplifier circuit as a base, the second input terminal connected to the emitter, and the first power source connected to the collector.
Time constant circuit described.