JPH0526773Y2 - - Google Patents
Info
- Publication number
- JPH0526773Y2 JPH0526773Y2 JP12366885U JP12366885U JPH0526773Y2 JP H0526773 Y2 JPH0526773 Y2 JP H0526773Y2 JP 12366885 U JP12366885 U JP 12366885U JP 12366885 U JP12366885 U JP 12366885U JP H0526773 Y2 JPH0526773 Y2 JP H0526773Y2
- Authority
- JP
- Japan
- Prior art keywords
- case
- overvoltage protection
- gate
- cathode
- copper post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 description 6
- 229910000833 kovar Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
Description
【考案の詳細な説明】
Ａ 産業上の利用分野
本考案は自己消弧形半導体素子の封入構造に係
り、特に素子のゲート・カソード間の過電圧防止
用ダイオードとの一体封入構造に関する。[Detailed Description of the Invention] A. Field of Industrial Application The present invention relates to an encapsulation structure for a self-arc-extinguishing semiconductor element, and particularly to an integral encapsulation structure with an overvoltage prevention diode between the gate and cathode of the element.
Ｂ 考案の概要
本考案は、自己消弧形半導体素子をケースに気
密封入するにおいて、
ケース内に一体に過電圧保護素子を圧接封入し
た構造とすることにより、
過電圧保護素子の接続、組立を容易にしながら
確実な動作、冷却を得ることができるようにした
ものである。B. Summary of the invention The present invention, when a self-arc-extinguishing semiconductor element is hermetically sealed in a case, has a structure in which the overvoltage protection element is integrally sealed in the case, thereby making it easier to connect and assemble the overvoltage protection element. However, it is possible to obtain reliable operation and cooling.
Ｃ 従来の技術
GTO（ゲートターンオフ）サイリスタや静電誘
導サイリスタ（SITh）の自己消弧形半導体素子
はゲート電極とカソード電極間の過電圧防止が重
要な課題になる。この例をGTOサイリスタの場
合について説明すると、GTOサイリスタのター
ンオフ時電圧、電流波形は第３図に示すようにな
る。図には主電流ｉ(t)、主電圧ｖ(t)、ゲート電流
ig(t)、ゲート逆電圧vg(t)を示し、ゲート逆電圧
vg(t)を印加して主電流ｉ(t)をしや断したとき、
ゲート・カソード間に発生する電圧vg(t)にはス
パイク状の高い電圧Vsにまで達し、この電圧Vs
がGTOサイリスタのカソード接合の耐圧VGKを越
えると該接合破壊になる。C. Prior Art For self-extinguishing semiconductor devices such as GTO (gate turn-off) thyristors and static induction thyristors (SITh), preventing overvoltage between the gate electrode and the cathode electrode is an important issue. To explain this example in the case of a GTO thyristor, the voltage and current waveforms at turn-off of the GTO thyristor are shown in FIG. The figure shows main current i(t), main voltage v(t), gate current
ig(t), gate reverse voltage vg(t), gate reverse voltage
When applying vg(t) and cutting off the main current i(t),
The voltage vg(t) generated between the gate and cathode reaches a spike-like high voltage Vs, and this voltage Vs
If exceeds the withstand voltage V GK of the cathode junction of the GTO thyristor, the junction will be destroyed.
そこで、従来から、第４図に示すようにGTO
サイリスタ１のゲート電極Ｇとカソード電極Ｋ間
にツエナーダイオード２と逆流阻止用ダイオード
３の直列回路を接続した過電圧保護回路が設けら
れる。このうち、ツエナーダイオード２はそのツ
エナー電圧VZがGTOサイリスタ１のゲート・カ
ソード間耐圧VGKよりも低くし（第３図参照）、
ゲート逆電圧vg(t)のスパイク部を該電圧VZにに
抑制する。ダイオード３はオンゲート電流がツエ
ナーダイオード２側でバイパスされるのを阻止す
る。 Therefore, as shown in Figure 4, GTO
An overvoltage protection circuit is provided between the gate electrode G and cathode K of the thyristor 1, in which a series circuit of a Zener diode 2 and a reverse current blocking diode 3 is connected. Among these, the Zener diode 2 has its Zener voltage V Z lower than the gate-cathode breakdown voltage V GK of the GTO thyristor 1 (see Figure 3).
The spike portion of the gate reverse voltage vg(t) is suppressed to the voltage VZ . Diode 3 prevents the on-gate current from being bypassed on the Zener diode 2 side.
Ｄ 考案が解決しようとする問題点
従来、過電圧保護用ツエナーダイオード２と逆
流阻止用ダイオード３は、第５図に示すように
PNP構造で一体構成の素子Ｚにされ、第６図に
示すように両端にリードピン４1，４2が接続され
て樹脂５によつて周辺がモールドされたものにさ
れる。D Problems to be solved by the invention Conventionally, the Zener diode 2 for overvoltage protection and the diode 3 for reverse current blocking are as shown in Fig. 5.
The element Z has a PNP structure and is integrated, and as shown in FIG. 6, lead pins 4 1 and 4 2 are connected to both ends, and the periphery is molded with resin 5.
この構造の過電圧保護素子Ｚは、GTOサイリ
スタ１のゲート電極Ｇとカソード電極Ｋ間に接続
してゲート逆電圧の過電圧を抑制できるが、
GTOサイリスタの動作周波数の増大すなわち素
子Ｚに印加される過電圧の繰り返し頻度が高くな
ると該素子Ｚの接合部温度が上昇する。従つて、
接合部の温度から動作周波数が制限され、またこ
れ以上の動作には冷却手段を必要とするしモール
ドによつて効率良い冷却ができない問題があつ
た。 The overvoltage protection element Z having this structure can be connected between the gate electrode G and the cathode electrode K of the GTO thyristor 1 to suppress the overvoltage of the gate reverse voltage.
As the operating frequency of the GTO thyristor increases, that is, the repetition frequency of the overvoltage applied to the element Z increases, the junction temperature of the element Z increases. Therefore,
The operating frequency is limited by the temperature of the joint, and further operation requires a cooling means, which poses the problem that efficient cooling cannot be achieved using a mold.
ところで、素子ＺとGTOサイリスタ１との接
続は可能な限り短い距離とすることが望まれる
が、素子Ｚとそのモールドも含めた過電圧保護素
子はその寸法構造が大きくなり、配線インダクタ
ンスによる過電圧保護機能が阻害される問題があ
つた。また、GTOサイリスタの動作周波数増大
による温度上昇を抑制するのに該過電圧保護素子
を複数個並列にして熱分散を図ることが考えられ
るが、これは上述寸法上の問題から限度がある。 By the way, it is desirable that the connection between element Z and GTO thyristor 1 be as short as possible, but the overvoltage protection element including element Z and its mold has a large dimensional structure, and the overvoltage protection function due to wiring inductance is There was a problem that prevented the Furthermore, in order to suppress the temperature rise due to an increase in the operating frequency of the GTO thyristor, it is conceivable to connect a plurality of overvoltage protection elements in parallel to achieve heat dispersion, but this is limited due to the above-mentioned size problem.
Ｅ 問題点を解決するための手段と作用
本考案は上記問題点に鑑みてなされたもので、
自己消弧形半導体素子をケースに気密封入するに
おいて、前記半導体素子のカソード側銅ポストの
内面又は該銅ポストをケースに封着する導体板の
内面に一方の電極面が固着され前記半導体素子の
ゲート・カソード間の逆電圧をバイパスする降伏
電圧にされた過電圧保護素子と、前記半導体素子
のゲート電極に接続され前記ケース外に引出され
たゲート端子と、前記ケース内で前記ゲート端子
と前記過電圧保護素子の他方の電極面との間に圧
接されるスプリング導体片とを備え、過電圧保護
素子をモールドを施すことなく銅ポスト又は導体
板を放熱フインとし、ケース内への封入時にスプ
リング導体片による圧接で銅ポスト又は導体板と
の間の組立を可能にしながら接続配線インダクタ
ンスを極めて小さくする。E Means and effects for solving the problems This invention was made in view of the above problems.
When a self-arc-extinguishing semiconductor element is hermetically sealed in a case, one electrode surface is fixed to the inner surface of the cathode-side copper post of the semiconductor element or the inner surface of a conductive plate that seals the copper post to the case. an overvoltage protection element set to a breakdown voltage that bypasses the reverse voltage between the gate and cathode; a gate terminal connected to the gate electrode of the semiconductor element and drawn out of the case; and a gate terminal connected to the overvoltage within the case. The overvoltage protection element is equipped with a spring conductor piece that is pressed into contact between the other electrode surface of the protection element, and the overvoltage protection element is not molded, but a copper post or a conductor plate is used as a heat dissipation fin, and the spring conductor piece is used when the overvoltage protection element is sealed in the case. To minimize connection wiring inductance while enabling assembly with a copper post or conductor plate by pressure welding.
Ｆ 実施例
第１図は本考案の一実施例を示す半断面図であ
り、中心線に対して対称構造にされる。GTO
サイリスタ素子本体１１は、PNPNの４層構造
のシリコン部１２と、このシリコン部１２のアノ
ード側に設けたタングステン板１３と、シリコン
部１２上のカソード側に設けたアルミ電極１４及
びゲート電極１５とからなる。このGTOサイリ
スタ素子本体１１はアノード側銅ポスト１６とカ
ソード側銅ポスト１７と絶縁用セラミツクス１８
を有する平形ケースに気密封入される。この平形
ケースにおいて、銅ポスト１６とセラミツクス１
８はコバール板１９によつて結合され、銅ポスト
１７とセラミツクス１８はコバール板２０，２１
によつて結合される。また、平形ケースのセラミ
ツクス１８には、コバールのゲート端子２２が挿
通される。ケースの気密封入はコバール板２０と
２１の周端部の溶接によつて行われる。F. Embodiment FIG. 1 is a half-sectional view showing an embodiment of the present invention, which has a symmetrical structure with respect to the center line. G.T.O.
The thyristor element body 11 includes a silicon part 12 having a four-layer structure of PNPN, a tungsten plate 13 provided on the anode side of the silicon part 12, and an aluminum electrode 14 and a gate electrode 15 provided on the cathode side of the silicon part 12. Consisting of This GTO thyristor element body 11 consists of an anode-side copper post 16, a cathode-side copper post 17, and an insulating ceramic 18.
Hermetically sealed in a flat case with In this flat case, the copper post 16 and the ceramics 1
8 are connected by a Kovar plate 19, and the copper post 17 and ceramics 18 are connected by Kovar plates 20, 21.
combined by Furthermore, a Kovar gate terminal 22 is inserted through the ceramics 18 of the flat case. The case is hermetically sealed by welding the peripheral edges of Kovar plates 20 and 21.
ここで、セラミツクス１８とGTOサイリスタ
素子本体１１との間には該素子本体１１をケース
内に位置決めする絶縁位置決めガイド２３が設け
られる。このガイド２３の上面にはゲート電極２
２に接続して又は一体にリング板２４が設けら
れ、該リング板２４は複数本のアルミ導線２５に
よつてゲート電極１５に均等に分散した位置で接
続される。カソード側銅ポスト１７は素子本体１
１のカソード電極１４に接触する面がその周辺と
は段部を持つて突出され、この段部１７Ａのうち
リング板２４に対向する部分に第５図に示す過電
圧保護素子２６が複数個均等に分散してろう付け
固着される。過電圧保護素子２６の他端電極面は
リング電極２４に分散して固着されたスプリング
導体片２７に圧接される。 Here, an insulating positioning guide 23 is provided between the ceramic 18 and the GTO thyristor element body 11 to position the element body 11 within the case. A gate electrode 2 is provided on the upper surface of this guide 23.
A ring plate 24 is provided connected to or integrally with the gate electrode 15, and the ring plate 24 is connected to the gate electrode 15 at evenly distributed positions by a plurality of aluminum conductive wires 25. The cathode side copper post 17 is the element body 1
The surface that contacts the cathode electrode 14 of 1 is projected with a stepped portion from its periphery, and a plurality of overvoltage protection elements 26 shown in FIG. Dispersed and fixed by brazing. The other end electrode surface of the overvoltage protection element 26 is pressed into contact with spring conductor pieces 27 which are dispersed and fixed to the ring electrode 24 .
こうした構造により、GTOサイリスタ素子本
体１１にはスプリング導体片２７とリング板２４
とアルミ導線２５と銅ポスト１７によつてケース
内で複数の過電圧保護素子２６が並列接続され、
配線インダクタンスは極めて小さくしかもケース
内に一体構造に構成される。そして、銅ポスト１
７及び１６はその端面に冷却フイン（図示しな
い）が圧接されて素子冷却がなされ、この冷却は
銅ポスト１７が通常80℃以下に冷却されることか
ら、過電圧保護素子２６も該温度以下に冷却され
る。即ち、過電圧保護素子２６はケース内に気密
封入されることから第５図に示すように酸化膜
SiO2の保護程度で済み、第６図に示すようなモ
ールド樹脂５を不要にして熱抵抗を極めて小さく
できることによる。 With this structure, the GTO thyristor element main body 11 includes a spring conductor piece 27 and a ring plate 24.
A plurality of overvoltage protection elements 26 are connected in parallel within the case by aluminum conductive wires 25 and copper posts 17,
The wiring inductance is extremely small and is integrated into the case. And copper post 1
7 and 16 have cooling fins (not shown) pressed against their end faces to cool the elements, and since the copper post 17 is normally cooled to below 80°C, the overvoltage protection element 26 is also cooled to below this temperature. be done. That is, since the overvoltage protection element 26 is hermetically sealed within the case, an oxide film is formed as shown in FIG.
This is because the protection of SiO 2 is sufficient, and the mold resin 5 as shown in FIG. 6 is unnecessary, and the thermal resistance can be extremely reduced.
第２図は本考案の他の実施例を示す半断面図で
ある。本実施例は比較的小容量のGTOサイリス
タに適用した場合であり、カソード側銅ポスト１
７を段無し構造とし、コバール板２０の内面に過
電圧保護素子２６を固着した構造にされる。本実
施例においても第１図のものと同等の作用効果を
得ることができる。 FIG. 2 is a half sectional view showing another embodiment of the present invention. This example is applied to a relatively small capacity GTO thyristor, and the cathode side copper post 1
7 has a stepless structure, and an overvoltage protection element 26 is fixed to the inner surface of the Kovar plate 20. In this embodiment as well, the same effects as those in FIG. 1 can be obtained.
なお、実施例においては過電圧保護素子として
PNP構造のものを示すが、これはNPN構造のも
のさらには個別のツエナーダイオードとダイオー
ド素子を直列接続したものにすることができる。 In addition, in the example, it is used as an overvoltage protection element.
Although a PNP structure is shown, it can also be an NPN structure or even a series connection of individual Zener diodes and diode elements.
Ｇ 考案の効果
以上のとおり、本考案によれば、過電圧保護素
子を自己消弧形半導体素子と共に、そのケースに
気密封入する構造とし、過電圧保護素子をモール
ドすることなく銅ポスト又は導体板に固着し他面
をスプリング導体片でゲート電極に圧接する構造
としたため、過電圧保護素子の放熱を確実にしし
かも接続配線インダクタンスを小さくし、さらに
組立、接続を容易にする効果がある。G Effect of the invention As described above, according to the invention, the overvoltage protection element is hermetically sealed in the case together with the self-arc-extinguishing semiconductor element, and the overvoltage protection element is fixed to the copper post or conductive plate without molding. However, since the other surface is pressed against the gate electrode by a spring conductor piece, it is possible to ensure heat dissipation from the overvoltage protection element, reduce connection wiring inductance, and facilitate assembly and connection.
第１図は本考案の一実施例を示す半断面図、第
２図は他の実施例を示す半断面図、第３図は
GTOサイリスタのターンオフ時の電圧、電流波
形図、第４図はGTOサイリスタの過電圧保護回
路図、第５図は過電圧保護素子の構造図、第６図
は過電圧保護素子のモールド構造図である。
１１……GTOサイリスタ素子本体、１３……
タングステン板、１４……アルミ電極、１５……
ゲート電極、１６，１７……銅ポスト、１８……
セラミツクス、２２……ゲート端子、２３……位
置決めガイド、２４……リング板、２６……過電
圧保護素子、２７……スプリング導体片。
Fig. 1 is a half-sectional view showing one embodiment of the present invention, Fig. 2 is a half-sectional view showing another embodiment, and Fig. 3 is a half-sectional view showing one embodiment of the present invention.
Figure 4 is a diagram of the voltage and current waveforms at turn-off of the GTO thyristor, Figure 4 is a diagram of the overvoltage protection circuit of the GTO thyristor, Figure 5 is a structural diagram of the overvoltage protection element, and Figure 6 is a diagram of the mold structure of the overvoltage protection element. 11...GTO thyristor element body, 13...
Tungsten plate, 14... Aluminum electrode, 15...
Gate electrode, 16, 17... Copper post, 18...
Ceramics, 22... Gate terminal, 23... Positioning guide, 24... Ring plate, 26... Overvoltage protection element, 27... Spring conductor piece.
Claims (1)
において、前記半導体素子のカソード側銅ポスト
の内面又は該銅ポストをケースに封着する導体板
の内面に一方の電極面が固着され前記半導体素子
のゲート・カソード間の逆電圧をバイパスする降
伏電圧にされた過電圧保護素子と、前記半導体素
子のゲート電極に接続され前記ケース外に引出さ
れたゲート端子と、前記ケース内で前記ゲート端
子と前記過電圧保護素子の他方の電極面との間に
圧接されるスプリング導体片とを備えたことを特
徴とする半導体素子の封入構造。 When a self-arc-extinguishing semiconductor element is hermetically sealed in a case, one electrode surface is fixed to the inner surface of the cathode-side copper post of the semiconductor element or the inner surface of a conductive plate that seals the copper post to the case. an overvoltage protection element set to a breakdown voltage that bypasses the reverse voltage between the gate and cathode; a gate terminal connected to the gate electrode of the semiconductor element and drawn out of the case; and a gate terminal connected to the overvoltage within the case. What is claimed is: 1. A structure for encapsulating a semiconductor element, comprising: a spring conductor piece that is pressed into contact with the other electrode surface of a protection element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12366885U JPH0526773Y2 (en) | 1985-08-12 | 1985-08-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12366885U JPH0526773Y2 (en) | 1985-08-12 | 1985-08-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6232555U JPS6232555U (en) | 1987-02-26 |
| JPH0526773Y2 true JPH0526773Y2 (en) | 1993-07-07 |
Family
ID=31014975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12366885U Expired - Lifetime JPH0526773Y2 (en) | 1985-08-12 | 1985-08-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0526773Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2634981B2 (en) * | 1991-10-30 | 1997-07-30 | 東洋電機製造株式会社 | Structure of composite semiconductor device |
| JP3571354B2 (en) * | 1999-01-18 | 2004-09-29 | 三菱電機株式会社 | Pressure welding type semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5791258U (en) * | 1980-11-26 | 1982-06-04 |
-
1985
- 1985-08-12 JP JP12366885U patent/JPH0526773Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6232555U (en) | 1987-02-26 |
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