JPH05267112A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the exposing accuracy of a minute pattern by preliminarily forming a groove corresponding to a boundary line in a chip region where a semiconductor integrated circuit is formed on the surface before the initial heat treatment for forming the semiconductor integrated circuit is formed, and decreasing or preventing the warp generated in heat treatment. CONSTITUTION:Grooves 3 are formed along the boundaries of a plurality of chip regions marked on the surface of a silicon wafer 1. The width is determined by the thickness of a diamond cutter for forming the groove. It is effective to select a depth d1 so that the depth is equal to or larger than the thickness of an impurity diffusing layer, which is formed later on the surface of the silicon wafer 1. The groove 3 is formed with the diamond cutter or by anisotropic etching using potassium hydroxide solution as etching agent. Thus, the accumulated stress, which causes warping, is dispersed. As a result, restoring force becomes excellent, and the warping can be decreased or eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing or preventing warpage that occurs when a substrate on which a semiconductor integrated circuit is formed is heat-treated.

[0002]

2. Description of the Related Art For example, heat treatment for diffusing impurities or forming a thermal oxide film on the surface of a silicon wafer is performed in a furnace at a high temperature of about 1000.degree. Such heat treatment is usually performed in a state where 10 to 20 wafers are stacked in a support with a gap. Therefore, since the heat radiation to each wafer surface is not always uniform,
Temperature distribution occurs on the surface. If this temperature distribution is large, thermal stress dislocations occur inside the wafer. FIG. 6 is a schematic diagram showing an X-ray topography of the (100) plane of a silicon wafer in which thermal stress dislocations have occurred. Dislocation has occurred (Tokuyama et al., "VLSI Manufacturing Technology", p.64,
Quoted from Nikkei BP).

Warpage occurs in the wafer due to thermal stress dislocation. A wafer in which dislocations having a distribution as shown in FIG. 6 have a complicated warp such as a saddle shape. As a result, for example, in the photolithography process, the wafer fixed on the exposure table does not become flat and an accurate pattern cannot be formed.
Further, since vacuum suction is not completely performed as a wafer holding means for fixing the wafer or moving it between processing steps as described above, the wafer may be displaced, the movement may fail, or the wafer may be damaged.

[0004]

The so-called ramping method is used to reduce the occurrence of thermal stress dislocations (see p.68, ibid.). That is, a step of preheating or precooling for about 10 minutes in a low temperature furnace of 800 to 900 ° C is provided in order to slow the temperature rising or cooling rate when loading and unloading wafers into and out of the furnace at a high temperature of 1000 ° C. Is the way. However, due to the ramping method described above, the temperature range 700-90
Since the time to pass 0 ° C becomes long, residual oxygen atoms in silicon are likely to precipitate, and there is a problem that dislocations and minute defects are generated by the precipitation of these oxygen atoms.

An object of the present invention is to provide a method in which a wafer does not warp even if it is directly put in or taken out of a high temperature furnace of about 1000 ° C.

[0006]

The above object is to provide a plurality of regions defined on the surface of a semiconductor substrate, each of which has a groove corresponding to a boundary line of a rectangular chip region in which a semiconductor integrated circuit is formed. A method of manufacturing a semiconductor device according to the present invention, which comprises a step of forming the semiconductor substrate on the back surface of the semiconductor substrate before the first heat treatment for forming the semiconductor integrated circuit, or, in the above, the substrate. A method for manufacturing a semiconductor device according to the present invention, characterized in that the depth of the groove with respect to the back surface is controlled to a value substantially equal to the thickness of the impurity diffusion layer formed on the surface of the substrate, or In the above, the groove corresponding to the boundary of the chip region existing in a region where warpage of a predetermined value or more may occur on the surface of the semiconductor substrate due to heat treatment in forming the semiconductor integrated circuit It is accomplished by any of a method of manufacturing a semiconductor device according to the present invention, wherein the selectively formed.

[0007]

[Function] By providing a groove on at least the surface of a substrate such as a silicon wafer, the accumulated stress that causes warpage is dispersed, and as a result, the restoring force becomes dominant and the warpage is reduced or eliminated.

[0008]

FIG. 1 is an explanatory view of the first embodiment of the present invention.
Figure (a) is a plan view, and Figures (b) and (c) are enlarged parts.
FIG. For example, a silicon wafer 1 with a diameter of 6 inches
Along the boundary line of a plurality of chip areas 2 defined on the surface of
To form the groove 3. Width (w) and depth (d) of groove 3₁) Is
They are about 100 μm and 20 μm, respectively. The width (w) is
For example, the thickness of the diamond cutter for forming the groove 3
It depends on Depth (d ₁) Is after the silicon wafer 1 surface
Greater than or equal to the thickness of the impurity diffusion layer to be formed
It is effective to choose the right one. The groove 3 can be formed, for example, with a diamond
Can be done using a hand-cutter or well-known lithographic technique.
Good. In particular, for example, etch potassium hydroxide solution
Formed by anisotropic etching used as a coating agent
Groove 3 with a V-shaped cross section as shown in Figure 1 (c)₀Also
It is effective.

FIG. 2 is a partial cross-sectional view for explaining a second embodiment of the present invention, in which grooves 3 and 4 similar to those in the above-mentioned embodiment are formed on the front surface and the back surface of a silicon wafer 1, respectively. is there. The widths and depths (d ₁ and d ₂ ) of the grooves 3 and 4 may be determined on the same basis as in the above-mentioned embodiment. Groove 3
Also for formation of 4 and 4, the same method as in the above-mentioned embodiment may be appropriately used.

FIG. 3 is a plan view for explaining a third embodiment of the present invention. For example, as described with reference to FIG. 6, regions A and B where warpage is likely to occur due to thermal stress dislocations.
This is the case where the groove 3 similar to that in the above-mentioned embodiment is formed only in (shown by the one-dot chain line). The dotted line indicates the boundary line where the groove 3 is not formed. The above-mentioned region where the groove 3 is selectively formed may be determined based on the warpage occurrence state investigated in advance.

FIG. 4 is a partial sectional view for explaining a fourth embodiment of the present invention. That is, as shown in FIG. 1, at the intersections of the grooves 3 (shown as grooves 3 ₁ and 3 _{2 in} FIG. 4 (a)) formed so as to extend in the vertical and horizontal directions on the surface of the silicon wafer 1, the silicon By forming the holes 6 penetrating the wafer 1, the stress inside the silicon wafer 1 can be more effectively dispersed. Such through holes 6, the silicon wafer 1 of the front and back surfaces of both the grooves 3 and formed of 4 (see FIG. 4 (b) grooves 4 ₁ and extending in vertical and horizontal direction on the back side in such as Fig. 2 4 ₂ )
It may be formed at the intersection.

FIG. 5 is a plan view for explaining the fifth embodiment of the present invention, in which a circular notch 7 is formed in the central portion of the silicon wafer 1. Cutout 7
Is effective when the silicon wafer 1 is spherically warped by heat treatment.

[0013]

According to the present invention, regardless of the diameter of a semiconductor substrate such as a silicon wafer, it is possible to reduce or prevent warpage caused by heat treatment, and improve the exposure accuracy of a fine pattern on a large-diameter substrate. In addition, it is possible to reliably carry the substrate. As a result, it is effective for the development of high-density and high-performance semiconductor integrated circuits and the improvement of manufacturing yield.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a second embodiment of the present invention.

FIG. 3 is an explanatory diagram of a third embodiment of the present invention.

FIG. 4 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 5 is an explanatory diagram of a fifth embodiment of the present invention.

FIG. 6 is a reference diagram for explaining conventional problems.

[Explanation of symbols]

1 Silicon Wafer 2 Chip Area 3, 30 ₀ , 3 ₁ , 3 _2, 4 Groove, 6 Through Hole 7 Notch

Claims (7)

[Claims] 1. A first region for forming a plurality of regions defined on a surface of a semiconductor substrate, each groove corresponding to a boundary line of a chip region in which the semiconductor integrated circuit is formed. A method of manufacturing a semiconductor device, which comprises a step of forming on the surface in advance before heat treatment is performed. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming another groove corresponding to the groove on the back surface of the semiconductor substrate before the first heat treatment. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the depth of the groove is controlled to a value substantially equal to the thickness of the impurity diffusion layer formed on the surface of the substrate. .. 4. The groove corresponding to the boundary of the chip region existing in a region where a warp of a predetermined value or more may occur on the surface of the semiconductor substrate by heat treatment in the formation of the semiconductor integrated circuit is selectively formed. The method for manufacturing a semiconductor device according to claim 1, wherein 5. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a hole penetrating the semiconductor substrate at an intersection of boundaries of the chip regions. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed by selectively etching the semiconductor substrate. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed by selectively cutting the semiconductor substrate.