JPH05266688A - Charge transfer device - Google Patents

Abstract

PURPOSE:To enable execution of driving without causing deterioration in a transfer efficiency even when the driving is executed by a fast clock pulse, by a structure wherein charge transfer areas just below transfer electrodes widen continuously and gradually for each transfer electrode along the direction of transfer of a charge. CONSTITUTION:Transfer electrodes 51 and 71 are disposed alternately on a P-type silicon substrate 1 with a gate insulation film 4 interlaid and clock pulses phi1 and phi2 are impressed alternately on sets of these electrodes. Transfer areas constructed of N-type diffused layers 2a and 3a divided by a field oxide film 10 and a P-type channel stopper 9 are made to have a structure wherein flat surfaces of the areas are so shaped as to widen continuously and gradually for each transfer electrode along the direction of transfer of a charge. By this structure, deterioration of a transfer efficiency can be suppressed even when driving is executed by a clock pulse of a high frequency.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to the structure of charge transfer devices.

[0002]

2. Description of the Related Art A charge transfer device is capable of accumulating information inputs such as electric signals and incident light in the form of electric charges, successively transferring the electric charges by a large number of transfer electrodes, and taking out the electric signals. It is widely used in imaging devices, memories, and other signal processing devices.

FIG. 4A shows a conventional two-phase charge coupled device (C
FIG. 4B is a plan view of CD) and FIG. 4B is a sectional view taken along line XX of FIG.

For example, a transfer electrode (barrier electrode 7i, is formed on one main surface of the P-type silicon substrate 1 via a thin gate oxide film 4).
, And storage electrodes 5i, ...) are arranged, and clock pulses φ1 and φ2 are alternately applied to the set of barrier electrode 7i and storage electrode 5i. The transfer region is the first N-type diffusion layer 2 (impurity concentration 5 × 10 ¹⁵ / cm ² ) selectively formed on the surface of the P-type silicon substrate 1.
And the second N-type diffusion layer 3 (impurity concentration 3 × 10 ¹⁵ to 4 × 10 ¹⁵ / cm ² ) below the barrier electrode. As a result, the width of the transfer area is constant.

[0005]

When the clock pulses φ1 and φ2 as shown in FIG. 5 are applied to the above-mentioned conventional charge transfer device, the surface potential ψ of the transfer region becomes as shown in FIG. 6, and time t = The charges 81 under the storage electrode 5j at t1 are transferred to the storage electrode 5k under t = t2.

By the way, in the conventional charge transfer device, since the transfer region has a structure in which the width is constant along the charge transfer direction, the potential 4 immediately below each transfer electrode is almost as shown in FIG. It is constant, but for example, 15
When a fast clock pulse of about MHz is applied, there is a drawback that the transfer efficiency deteriorates to about 90%.

[0007]

The present invention has a transfer region defined on the surface of a semiconductor substrate of one conductivity type, and a transfer electrode group for selectively covering the transfer region via a gate insulating film. In the charge transfer device, the width of the transfer region is not yet spread along the charge transfer direction for each of the transfer electrodes.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1A shows an embodiment of the present invention 2
FIG. 1 is a plan view showing a phase-driven charge-coupled device (CCD).
1B is a sectional view taken along line Xa-Xb of FIG. 1A, and FIG.
FIG. 2 is a sectional view taken along the line YY of FIG.

A first N-type diffusion layer 2a having an impurity concentration of 5.0 × 10 ¹⁵ / cm ² is provided on the surface of the P-type silicon substrate 1, and a transfer electrode is arranged on the surface thereof via a gate oxide film 4. Has been done. That is, pairs of barrier electrodes 7i and storage electrodes 5i are alternately arranged, and clock pulses φ1 and φ2 are alternately applied to these pairs. Barrier electrode 7i,
7j, ... has an impurity concentration of 3.0 × 10 ¹⁵ to 4.
A second N-type diffusion layer 3a of 0 × 10 ¹⁵ / cm ² is provided.

The transfer region is divided into a field oxide film 10 and a P ⁺ -type channel stopper 9 below the first and second transfer regions.
The N-type diffusion layer has a structure in which its planar shape is such that it gradually and continuously spreads along with the charge transfer direction for each transfer electrode. The first and second N-type diffusion layers have a bottom length W1 =
7.5 μm, upper side length W2 = 5 μm, height L = 4 μm
It has a trapezoidal shape.

FIG. 2 shows the distribution of the surface potential ψ in the transfer region when a constant voltage is applied to the transfer electrode. The horizontal axis is the width direction of the transfer area (direction parallel to the YY line)
For

The surface potential ψ along the direction perpendicular to the transfer direction (Xa-Xb line direction) is deep at the center of the transfer region, but becomes shallower as it moves away from the center due to the effect of the narrow channel effect.

Also, the wider the transfer area, the less likely it is to be affected by the narrow channel effect, and the deeper it is as a whole.

As a result, the surface potential ψ1 of the wide portion is
A potential difference Δψ occurs between the surface potential ψ2 and the surface potential ψ2 of the narrow portion. Therefore, an acceleration electric field is generated in the charge transfer direction.

In FIG. 3, a clock pulse φ is applied to each transfer electrode.
6 shows the surface potential in the charge transfer direction when 1 and φ2 (shown in FIG. 5) are applied. Clock pulse φ1, φ
When the pulse height of 2 is 5 V, an accelerating electric field of about 0.25 V / μm is generated. As in the conventional example, the electric charges 81 under the storage electrode 5j at the time t1 are transferred to the storage electrode 5k under the time t2.

In the present embodiment, the same wave number of 1.5 times that of the conventional one is 15
No deterioration in transfer efficiency was observed even when driven by a MHz clock pulse.

[0018]

As described above, the present invention has a structure in which the charge transfer region immediately below the transfer electrode is gradually and gradually widened for each transfer electrode along the charge transfer direction. Even if it drives with a high frequency clock pulse, it has the effect that the deterioration of the transfer efficiency can be suppressed.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention (see FIG.
(A)), sectional view taken along line Xa-Xb of FIG.
(B)) and the YY line sectional view of FIG.
(C)).

FIG. 2 is a diagram showing a surface potential distribution in a width direction of a transfer region according to an embodiment of the present invention.

FIG. 3 is a potential diagram used for explaining the operation of the embodiment of the present invention.

FIG. 4 is a plan view showing a conventional two-phase drive CCD (see FIG.
It is (a)) and sectional drawing (FIG.4 (b)).

FIG. 5 is a timing diagram showing clock pulses of a two-phase drive CCD.

FIG. 6 is a potential diagram used for explaining the operation of a conventional two-phase driving CCD.

[Explanation of symbols]

1 P-type silicon substrate 2, 2a First N-type diffusion layer 3, 3a Second N-type diffusion layer 4 Gate insulating film 5i, 5j, 5k Storage electrode 6 Inter-layer insulating film 7i, 7j, 7k Barrier electrode 81, 82 Charge 9 P ⁺ type channel stopper 10 Field oxide film φ1, φ2 Clock pulse ψ Surface potential

Claims (2)

[Claims] 1. A charge transfer device comprising: a transfer region partitioned into a surface portion of a one-conductivity-type semiconductor substrate; and a transfer electrode group selectively covering the transfer region via a gate insulating film. The charge transfer device is characterized in that the width of each of the transfer electrodes does not spread along the charge transfer direction. 2. The charge transfer device according to claim 1, wherein the transfer region is an impurity diffusion layer of another conductivity type in which a surface portion of the one conductivity type semiconductor substrate is selectively formed.