JPH05266605A - Data recording/reproducing circuit for magnetic recorder and data recording/reproducing method - Google Patents

Abstract

PURPOSE:To realize accurate discrimination even of a low quality signal by a constitution wherein a Viterbi decoder performs discrimination processing through the use of a VFO clock produced from a converted digital signal through a variable frequency generating means. CONSTITUTION:A recovered waveform signal, read out from a magnetic recording medium 11 through a magnetic head 12, is amplified through a preamplifier 1, equalized through an equalizer 2 and then fed to a peak detecting pulsating circuit 3, a delay circuit 4, and a VFO circuit 5. A peak pulse produced from the circuit 3 is employed as the clock for an A/D converter 6 while an equalized waveform, which is timed to the peak pulse through the delay circuit 4, is fed to the A/D converter 6. An amplitude data, subjected to A/D conversion, is fed to a latch circuit 7 and timed to a VFO clock produced from the circuit 5 and then fed to a Viterbi decoder 8. The circuit 8 performs Viterbi decoding based on a minimum pulse on a time series state transition diagram.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recording / reproducing circuit and a data recording / reproducing method for a magnetic recording device, and more particularly to a data recording / reproducing circuit and data suitable for reproducing low quality signals due to waveform distortion and low S / N. Recording and reproducing method.

[0002]

2. Description of the Related Art Generally, a data recording / reproducing circuit of a magnetic recording apparatus reproduces read data by discriminating a reproduced waveform signal read from a magnetic recording medium by a magnetic head by a phase discrimination system. With this phase discrimination method, a convex gate signal obtained by cutting the reproduced waveform signal of the waveform at plus and minus slice levels, and a pulse signal having a peak at its zero-cross point by differentiating the reproduced waveform signal, The presence of the pulse signal in the gate signal (AND is taken) extracts a peak pulse, and the read pulse is reproduced by aligning the timing of the peak pulse with a VFO clock from a VFO (variable frequency oscillator). There is.

As an example of improving the discrimination performance in this phase discrimination system, a data recording / reproducing circuit described in JP-A-63-153705 has been proposed. This data recording / reproducing circuit is provided with a plurality of slice levels when the gate signal is made, and uses a gate and a level determination circuit corresponding to each slice level to reduce an error caused by a drop in amplitude or a spring out. Is.

On the other hand, an example in which a Viterbi decoder is used as a discriminating circuit is eye. E. E. E-Transactions on Communications Vol. 34, No. 5 (IEEE T
RANSATIONS ON COMMUNICATI
ONS, VOL. COM-34, NO5, MAY 19
86), pages 454 to 461.
The discrimination circuit described in this document is a method for discriminating reproduced waveform signals using waveform amplitude data by symbol rate sampling, that is, an amplitude discrimination method, which is essentially different from the phase discrimination method. It has been shown that this Viterbi decoder has an effect of improving the discrimination performance of 3 dB in S / N as compared with a normal bit-by-bit decoder.

[0005]

In recent years, in the data recording / reproducing circuit of the magnetic recording apparatus, the necessity of correctly discriminating even low-quality signals is increasing with the increase in data recording density. Although the conventional phase discrimination method has been devised to improve the discrimination performance as in the above-mentioned example, it is necessary to further improve the performance. On the other hand, the amplitude discrimination method has an advantage that the Viterbi decoding method can be used, but since the discrimination is performed only with the amplitude data sampled at the VFO clock timing, the discrimination performance may be significantly deteriorated due to the deviation of the sample timing. Therefore, it is necessary to solve this problem when the Viterbi decoding method is used as the signal discrimination method.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and a data recording / reproducing circuit and a signal reproducing method of a magnetic recording apparatus capable of more accurately discriminating even a low quality signal. Is to provide.

[0007]

To achieve the above object, a data recording / reproducing circuit of a magnetic recording apparatus according to the present invention comprises:
Peak detecting means for detecting a peak pulse of the reproduced waveform signal read from the recording medium, variable frequency generating means for generating a VFO clock having a variable frequency based on the reproduced waveform signal, and peak pulse detected by the peak detecting means. The first feature is that it is provided with an A / D conversion means for converting the reproduced waveform signal into a digital signal at the timing of 1) and a Viterbi decoder for inputting the digital signal and performing a discrimination process by a VFO clock.

The data recording / reproducing circuit according to the present invention is
A data modulation circuit for converting the digital data into a run length limited code at the time of digital data recording, a peak detecting means for detecting a peak pulse of the reproduced waveform signal read from the magnetic recording medium, and a variable frequency based on the reproduced waveform signal. Variable frequency generating means for generating a certain VFO clock, A / D converting means for converting the reproduced waveform signal into a digital signal at the timing of the peak pulse detected by the peak detecting means, and the VFO clock with the digital signal as input. A second feature is that it is provided with a Viterbi decoder that performs discrimination processing by the above and outputs read data, and a data demodulation circuit that demodulates the read data based on a run length limited code and outputs digital data. To do.

Further, the data recording / reproducing circuit according to the present invention is
A third feature is that the coding rate of the data modulation and demodulation circuit is a 2/3 coding rate for converting 2-bit data into a 3-bit code, and 8-bit data is converted into a 9-bit code. A fourth characteristic is that the coding rate is 8/9.

The signal reproducing method of the magnetic recording apparatus according to the present invention performs digital conversion of the reproduced waveform signal based on the peak pulse of the reproduced waveform signal read from the magnetic recording medium,
The fifth step is to reproduce the read data by performing the Viterbi decoding type discrimination processing on the digitally converted digital signal based on the VFO clock obtained from the reproduced waveform signal.
It is a feature of.

The data recording / reproducing method according to the present invention is
At the time of data recording, the digital data is converted into a run length limited code, the reproduced waveform signal is digitally converted based on the peak pulse of the reproduced waveform signal read from the magnetic recording medium, and the digitally converted digital signal is reproduced. A sixth feature is that the Viterbi decoding type discrimination processing is performed based on the VFO clock obtained from the waveform signal to reproduce the read data, and the reproduced read data is demodulated into a run length limited code into digital data.

Further, the data recording / reproducing method according to the present invention is
The seventh feature is that the coding rate of the run-length limited coding is a 2/3 coding rate for converting 2-bit data into a 3-bit code, and 8-bit data is converted into a 9-bit code. An eighth characteristic is that the coding rate is 8/9.

[0013]

In the data recording / reproducing circuit of the magnetic recording apparatus according to the first feature, the reproduced waveform signal is converted into a digital signal by the A / D converting means at the timing of the peak pulse detected by the peak detecting means, and the digital signal is converted. The Viterbi decoder performs the discrimination processing by the VFO clock generated by the variable frequency generating means, so that the read data with improved level margin and phase margin can be reproduced.

Further, the data recording / reproducing circuit of the magnetic recording device according to the second feature limits the inter-signal distance of the reproduced signal read from the magnetic recording medium by using the run length limited encoding at the time of data recording, The discrimination performance of the Viterbi decoder can be improved. Further, the data conversion circuit according to the third and fourth features can reproduce the read data with the improved phase margin by encoding the data with a high encoding rate.

In the data recording / reproducing method of the magnetic recording apparatus according to the fifth feature, the reproduced waveform signal read from the magnetic recording medium is converted into a digital signal at the timing of its peak pulse, and the digital signal is reproduced. By performing the Viterbi decoding type discrimination processing based on the VFO clock obtained from the signal, it is possible to reproduce the read data with an improved level margin.

In the data recording / reproducing method according to the sixth feature, the run length limited code is used at the time of data recording to limit the inter-signal distance of the reproduced waveform signal read from the magnetic recording medium, and to perform the Viterbi decoding. Performance can be improved. Further, in the data recording / reproducing method according to the seventh and eighth characteristics, the read data having the improved phase margin can be reproduced by converting the coding rate of the run length limited coding into a code having a high coding rate. it can.

[0017]

First, the principle of the present invention will be described. Generally, well-known quantities for evaluating the discrimination performance in the phase discrimination method include a level margin and a phase margin. In order to improve the discrimination performance, it is necessary to make these two margin amounts large and well balanced. ..

The present invention is intended to improve the level margin by using a Viterbi decoder even though it is essentially a phase discrimination system. In a system with originally small level margin, this directly leads to improvement of the discrimination performance, and the phase discrimination performance is improved. Encoding that increases the discrimination window width in a system with a small margin, in other words, by selecting a code with a large encoding rate,
The discrimination performance can be improved. The method of using the Viterbi decoder for the phase discrimination method can be realized by using the peak pulse of the reproduced waveform as a clock for capturing the reproduced waveform amplitude. This method is essentially a phase discrimination method in the sense that it uses a peak pulse to capture the waveform and a VFO clock to align the data timing.

By using the above-described principle, the present invention can avoid the problem of discrimination performance deterioration due to deviation of sample timing peculiar to the amplitude discrimination method in that the waveform peak value can be always taken in as amplitude data. Also,
The maximum margin can be increased by performing maximum likelihood decoding with a Viterbi decoder for a pseudo peak and a drop in amplitude caused by noise, medium defects, and the like. On the other hand, although it is not possible to increase the phase margin by using this method, it is possible to comprehensively improve the discrimination performance by selecting the encoding that reduces the imbalance between these two margin amounts.

An embodiment of the data recording / reproducing circuit of the magnetic recording apparatus according to the present invention will be described below in detail with reference to the drawings. 1 is a diagram showing a main configuration of a data recording / reproducing circuit according to the present embodiment, FIG. 2 is a diagram showing a circuit configuration of a Viterbi decoder shown in FIG. 1, and FIG. 3 is a configuration diagram of a logical operation circuit 36 shown in FIG. Figure 4
FIG. 5 is a diagram for explaining signal processing, and FIG. 5 is a configuration diagram of the shift register 39 in FIG.

The data recording / reproducing circuit according to this embodiment is shown in FIG.
As shown in FIG. 3, a data modulation circuit 13 for converting the user data into a run length limited code, a preamplifier 1 for amplifying a reproduced waveform signal read from the magnetic recording medium 11 by the magnetic head 12, and a preamplifier 1 for the amplified reproduced waveform signal. An equalizer 2 for removing interference between waveforms, a peak detection pulse conversion circuit 3 for detecting a peak of this waveform, a delay circuit 4 for delaying a waveform signal from the equalizer 2 for a predetermined time, and a waveform signal based on the waveform signal. VFO that generates the Zuki VFO clock (VFOCLK)
A circuit 5, an A / D converter 6 for A / D converting the output signals of the peak detection pulse converting circuit 3 and the delay circuit 4, and the output signal of the converter 6 is latched by the VFO clock from the VFO circuit 5. Latch circuit 7, a Viterbi decoder 8 that decodes the reproduction signal read from the latch circuit 7 at the timing of the VFO clock and outputs read data, and the read data that is the run-length limited code is converted into user data. It is composed of a data sub-length circuit 14. The equalizer is, for example, a transversal filter including a delay circuit with a tap and an adder, and removes inter-waveform interference by adjusting the tap coefficient. The peak detection pulse converting circuit 3 is composed of, for example, a differentiating circuit, a zero level detecting circuit, and a pulse converting circuit. The data modulation circuit 13 and the data demodulation circuit 14 are composed of, for example, a ROM (read-on memory) in which data modulation rules are recorded, a shift register circuit, and the like.

When performing data recording, the data recording / reproducing circuit configured as described above converts user data into a predetermined run-length limiting code, which will be described later, in the data modulating circuit 13 and, via the magnetic head 12, the magnetic recording medium. 11
To record. When performing data reproduction, this circuit amplifies a reproduction waveform signal read from the magnetic recording medium 11 via the magnetic head 12 in the preamplifier 1 and equalizes the reproduction waveform by the equalizer 2 (see the upper part of FIG. 4). After that, it is input to the peak detection pulse conversion circuit 3, the delay circuit 4, and the VFO circuit 5. The peak pulse (see FIG. 4) generated by the peak detection pulse conversion circuit 3 is used as a clock for the A / D converter 6, while the delay circuit 4 produces an equalized waveform whose timing is aligned with the peak pulse. It is input to the converter 6. A / D converted amplitude data (A / D OUT,
(See FIG. 4) enters the latch circuit 7 and is output to the Viterbi decoder 8 after the timing is adjusted by the VFO clock generated by the VFO circuit 5. FIG. 2 shows the circuit configuration of the Viterbi decoder 8. The Viterbi decoding method operated by the circuit 8 is a sample value time series {X _K | K = 0,
, N} and the ideal value time series {YK | K = 0, ..., n} to obtain the ideal value time series having the minimum Euclidean distance shown in the following equation 1, a time series transition is performed. The minimum path in the figure (trellis diagram) is found, and Viterbi decoding is performed based on this pulse.

[0023]

[Equation 1]

According to the aforementioned IEEE publication, two states 1 and 0 (1 is a state in which a positive signal is received, 0 is a state in which a negative signal is received) are defined.
It is known that the path that finally survived becomes the maximum likelihood path by repeating the path selection algorithm shown in (1) at each time and discarding the path that is interrupted in the middle.

[0025]

[Table 1]

Here, A is the waveform amplitude average value, and the paths corresponding to the numbers (I), (II), and (III) are shown in FIG. 6 in the trellis diagram between times k-1 and k. It is the path shown. In FIG. 6, path (I) is a combination of a path whose state is 0 at time k−1 and a state of 1 at time k, and a path whose state is 0 at time k−1 and whose state is 0 at time K. In the table, the state at time k−1 is set to 0. Path (II) represents a combination of a path having a state of 1 at time k−1 and a state of 1 at time k, and a path having a state of 0 at time k−1 and a state of 0 at time k. I have to. Further, the path (III) has a state of 1 at time k−1 and a state of 1 at time k, and a state of 1 at time k−1.
In the table, combinations of paths whose state is 0 at time k are defined as 1, and the state at time k−1 is fixed at 1. The Viterbi decoder 8 is basically configured to execute this algorithm.

The Viterbi decoder 8 subtracts the data Xk (see FIG. 4) latched at the time k in the latch circuit 7 and the data Xp (see FIG. 4) latched at the time p (p <k) in the latch circuit 31. After calculating with the calculator 32,
It sends to the comparators 33 and 34. The comparators 33 and 34 check the magnitude relation between the data and the output data M1 and M2 of the memory 35. The memory 35 changes its output according to an output Q (see FIG. 4) of a logical operation circuit 36 described later, and when Q = 0,
Outputs M1 = A, M2 = 0, and when Q = 1, M1 = 0,
Outputs M2 = -A (see FIG. 4). However, A is stored in the memory 35 as the average value of the reproduced waveform amplitude,
The value in the memory is updated according to the change in the average amplitude value.

The comparator 33 outputs the data C1 by the following comparison. When Q = 0, when Xk−Xp> A, “1” When Xk−Xp ≦ A, “0” When Q = 1, Xk−Xp If> 0, then “1” (see FIG. 4) If Xk−Xp ≦ 0, then “0”. Comparator 34 outputs data C2 by the following comparison. When Q = 0, if Xk−Xp <0, then “1”. If Xk−Xp ≧ 0, then “0” Q = 1. If Xk−Xp <−A, then “1”. If Xk−Xp ≧ −A, then “0”. Therefore, the outputs of the comparators 33 and 34 are C1 =. 1, C2 = 0
If so, path (I) is selected at that time, and C1
= 0, C2 = 0, path (II) is selected, C1 = 0,
If C2 = 1, the path (III) is selected.

The binary data C1 and C2 output from the comparator 33.34 are input to the logical operation circuit 36. From the selected path information C1 and C2, the logical operation circuit 36 uses the memory 35
Of the AND circuit 54, 55, 57 as shown in FIG. 3, for example, as shown in FIG.
, Exclusive logic circuit sum circuits 56 and 58, and a flip-flop circuit 59. Here, the output signal NO is a pulse output by the exclusive OR circuit 58 when C1 or C2 is 1, that is, when the selected path is (I) or (III), and this is the latch of the latch circuit 7. Used as a timing clock. On the other hand, the output signal W1 is supplied to the AND circuits 54 and 57 and the exclusive OR circuit 5
When C1 and C2 are alternately set to 1 by 6, the pulse is output when the selection path changes from (I) to (III) or (III) to (I). The output when used as the clock of 59 becomes Q, and this becomes the output selection signal of the memory 35.
However, it should be noted that this output Q is not the signal itself representing the above "state".

The 3-bit counter circuit 37 shown in FIG. 2 uses VFOCLK-P as an input clock and outputs the signals S0, S1 and S2 using the signal NO as a reset signal.
That is, the time is counted only when the selected path is (II), and the selected path is (I) or (III).
When it becomes, the counted value is reset. When the selection path is (II), the signal discrimination value at that time is "at that time regardless of the selection paths before and after that.
Since it is known that the value is set to 0 ", the counter circuit 37 eventually counts the number of signal discrimination values" 0 ". Outputs S0, S1, S2 of the 3-bit counter circuit 37
(See FIG. 4) is used as a select signal for the demultiplexer circuit 38, while the signal W1 is also used as an enable signal for the demultiplexer circuit 38. Therefore,
The demultiplexer circuit 38 has a selection path from (I) to (I
II), or the number of signal discrimination value "0" until immediately before the change from (III) to (I) is received. And
The output data of the demultiplexer circuit 38 is sent to the shift register circuit 39.

The shift register circuit 39 is composed of a plurality of OR circuits 52 and a flip-flop circuit 53 as shown in FIG. 5, for example, and is different from a normal shift register (which is composed only of flip-flop circuits). Register outputs (Q1, Q2, Q3) and external inputs (P2,
Since the sum of P3 and P4) is used as the subsequent input signal, the register information is rewritable by external input. The shift register circuit 39 operates by using VFOCLK-N as a clock, and outputs temporary discrimination data "0" to the output data (P1, P1) of the demultiplexer circuit 38 as necessary.
2, P3, P4) to rewrite as "1". That is,
When the selection path changes from (I) to (III) or from (III) to (I), the discrimination data “1” is changed to the shift register circuit according to the number of the signal discrimination value “0” until immediately before that. Data is rewritten in the shift register circuit 39 by inputting from the input location of 39 (P1 or P2 or P3 or P4). Therefore, the shift register circuit 3
The final discrimination value (read data) is obtained at the output of 9. Here, the read data is obtained according to the change of the "state", in other words, according to the "finally survived path".

The number of shift stages of the shift register circuit 39 is at least the longest number of run lengths of the code being used plus 1, and in the case of (8/9) encoding for converting 8-bit data into 9-bit data. In the case of (1,7) encoding for converting 4-stage 2-bit data into 3-bit data, 8 stages are enough. In FIG. 2, a 4-stage shift register is configured for 8-9 encoding.

Further, as the data recording code applied to the data recording / reproducing circuit according to the present embodiment, it is preferable to use a coding rate such that the discrimination window width becomes large at the time of reproducing.
Since the discrimination window width is represented by Rc × Tb with respect to the user bit interval Tb and the coding rate Rc, the discrimination window width can be increased by using a code having a large coding rate. Specifically, a code having a coding rate of ⅔ or more is effective in that it balances the level margin and the phase margin in this system. Table 2 shows an example of run-length limited code satisfying this condition, its coding rate, discrimination window width,
Indicates run length. The coding rate is represented by (user data length / code length) as shown in Table 2. For example, the coding rate of a code for converting 2-bit data into a 3-bit code is expressed as (2/3). To be done. The run length is the number of consecutive "0" regulated by the code rule,
For example, in (1,7) encoding, encoding is performed so that the shortest length of the code is 1 and the longest number is 7, that is, the number of "0" s after encoding is 1 to 7.

[0034]

[Table 2]

FIG. 4 shows a time chart showing the circuit operation of the embodiment. Here, the average value of the waveform amplitude is 2.0
The calculation is executed as. It will be sequentially described along this flow. First, from the reproduced waveform signal, the A / D converter 6
Outputs the DOUT value and outputs VFO from the reproduced waveform signal.
The circuit 5 outputs VFOCLK-N and VFOCLK-P. After that, the steps shown below and A to E are executed. In this specification, the exclusive OR symbol is @
It has been described as.

[0036]: VFOCLK-P rises at X _K is a change in: so to satisfy the X _K -X _P <M2 conditions, C2 is "
Change to 1 ”: W1 = (C1 · reverse Q) @ (C2 · Q) W
1 changes to “1”: Q changes from “1” to “0” when W1 rises: M1 and M2 change due to Q change: NO = (C1 @ C2) · VFOCLK-N changes NO Change to “1”: X _P changes at the rise of NO: X _K −X _P ≧ M2 Since the condition is satisfied, C2 is “0”
Change: W1 changes to "0" by the conditional expression of W1 NO changes to "0" by the conditional expression of NO A: S0, S1, S2 changes at the rise of VFOCLK-P B: W1 changes to "1" At this time, select signals (S0, S1,
P1 becomes “1” according to S2) = (0,1,0) C: The value in the shift register shifts at the rising edge of VFOCLK-N (Q2 is “1”) D: Counter when NO is “1” E: P1 to P4 change to "0" when W1 is "0" However, the demultiplexer 38 related to the operations of B and E has the enable signal (EN) of "1", and (2 ⁰ , 2 ^{1, 2} 2) = (1, 0, 0) when P1 = 1, P2 = P3 = P4 = 0 (2 0, 2 1, 2 2) = P2 = 1 when (0,1,0), When P1 = P3 = P4 = 0 (2 ⁰ , 2 ¹ , 2 ² ) = (1,1,0) P3 = 1, P1 = P2 = P4 = 0 (2 ⁰ , 2 ¹ , 2 ² ) = ( when the P4 = 1, P1 = P2 = P3 = 0 the EN is "0" when the 0,0,1) (2 ^0, 2 ^1, 2 ²⁾ regardless of the value of, P1 = P2 = P3 And outputs the P4 = 0.

As described above, the signal reproducing apparatus of the magnetic recording apparatus according to the present embodiment converts the reproduced waveform signal into a digital signal by the A / D conversion means for converting the reproduced waveform signal into the digital signal by the VFO clock. By performing the Viterbi decoder discrimination processing, it is possible to always capture the waveform peak value as amplitude data and prevent the discrimination performance from deteriorating due to the deviation of the sample timing peculiar to the amplitude discrimination method. In addition, the maximum margin can be increased by performing maximum likelihood decoding with the Viterbi decoder even for pseudo peaks and amplitude drop caused by noise, medium defects, etc. On the other hand, this method is used. As a result, it is possible to comprehensively improve the discrimination performance by selecting the encoding that reduces the imbalance of the level and the phase margin amount.

[0038]

According to the present invention, the peak value of the reproduced waveform signal is captured as the amplitude data, so that the reproduced signal of low quality (waveform distortion, low S / N, etc.) which has conventionally caused a read error can be corrected. It becomes possible to reproduce. In particular, it has a performance improvement effect of up to 3 dB in S / N as compared with the conventional phase discriminator using a single gate level.

[Brief description of drawings]

FIG. 1 is a diagram showing a data recording / reproducing circuit of a magnetic recording apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a circuit configuration of a Viterbi decoder in FIG.

FIG. 3 is a diagram showing an example of a configuration of a logical operation circuit 36 in FIG.

FIG. 4 is a time chart for explaining the operation of the circuit of this embodiment.

5 is a diagram showing an example of a configuration of a shift register 39 in FIG.

FIG. 6 is a diagram showing classification of paths in Viterbi decoding.

[Explanation of symbols]

1: Preamplifier, 2: Equalizer, 3: Peak detection pulse conversion circuit, 4: Delay circuit, 5: VFO circuit, 6: A / D converter, 7: Latch circuit, 8: Viterbi decoder, 11: Magnetic Recording medium, 12: magnetic head, 13: data modulation circuit, 1
4: data demodulation circuit, 31: latch circuit, 32: subtractor, 33, 34: comparator, 35: memory, 36: logical operation circuit, 37: counter circuit, 38: demultiplexer circuit, 39: shift register circuit , 53, 59: flip-flop circuits, 54, 55, 57: AND circuits, 5
6, 58: Exclusive OR circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideki Sawaguchi 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (8)

[Claims] 1. A peak detecting means for detecting a peak pulse of the reproduced waveform signal in a data recording / reproducing circuit of a magnetic recording device for reading an analog reproduced waveform signal from a magnetic recording medium and reproducing read data from the reproduced waveform signal. ,
Variable frequency generating means for generating a VFO clock having a variable frequency based on the reproduced waveform signal; and A / D conversion means for converting the reproduced waveform signal into a digital signal at the timing of the peak pulse detected by the peak detecting means. A data recording / reproducing circuit of a magnetic recording device, comprising: a Viterbi decoder which receives the digital signal as input and performs discrimination processing by a VFO clock. 2. A data recording / reproducing circuit of a magnetic recording apparatus for recording digital data on a magnetic recording medium and reproducing the digital data from the magnetic recording medium, wherein the digital data is converted into a run length limited code at the time of recording digital data. A data modulation circuit, a peak detecting means for detecting a peak pulse of a reproduced waveform signal read from a magnetic recording medium, and a variable frequency V based on the reproduced waveform signal.
A variable frequency generating means for generating an FO clock, and A for converting the reproduced waveform signal into a digital signal according to the timing of the peak pulse detected by the peak detecting means.
/ D conversion means and the digital signal as input, and VFO
A magnetic recording characterized by comprising a Viterbi decoder for discriminating processing by a clock and outputting read data, and a data demodulation circuit for demodulating the read data based on a run length limited code and outputting digital data. Data recording / reproducing circuit of the device. 3. The coding rate of the data modulation and demodulation circuit is 2/3 for converting 2-bit data into 3-bit code.
The data recording / reproducing circuit of the magnetic recording device according to claim 2, wherein the data recording / reproducing circuit is a code rate. 4. The coding rate of the data modulation and demodulation circuit is 8/9 for converting 8-bit data into a 9-bit code.
The data recording / reproducing circuit of the magnetic recording apparatus according to claim 2, wherein the data recording / reproducing circuit is a code rate. 5. A signal reproducing method of a magnetic recording apparatus for reading an analog reproduced waveform signal from a magnetic recording medium and reproducing read data from the reproduced waveform signal, wherein the reproduced waveform signal is based on a peak pulse of the reproduced waveform signal. Data of the magnetic recording apparatus, wherein the read data is reproduced by performing the Viterbi decoding type discrimination processing on the basis of the VFO clock obtained from the reproduced waveform signal. Recording and playback method. 6. A data recording / reproducing method of a magnetic recording apparatus for recording digital data on a magnetic recording medium and reproducing the digital data from the magnetic recording medium, wherein the digital data is converted into a run length limited code at the time of recording the data. The reproduced waveform signal is converted and digitally converted based on the peak pulse of the reproduced waveform signal read out from the magnetic recording medium, and the digitally converted digital signal is Viterbi decoding system based on the VFO clock obtained from the reproduced waveform signal. The data recording / reproducing method for a magnetic recording device, characterized in that the read data is reproduced by discriminating the read data, and the reproduced read data is demodulated into a run length limited code into digital data. 7. The coding rate of the run-length limited coding is 2/3, which converts 2-bit data into a 3-bit code.
The data recording / reproducing method of the magnetic recording device according to claim 6, wherein the data is a code rate. 8. The code rate of the run-length limited encoding is 8/9 for converting 8-bit data into a 9-bit code.
The data recording / reproducing method of the magnetic recording device according to claim 6, wherein the data is a code rate.