JPH05265921A - Data transfer system and circuit - Google Patents

Abstract

PURPOSE:To attain the speed-up of a data transfer clock frequency by delaying a data transfer clock inputted to an address counter, and decreasing a difference between the delay amounts of the clock and those of transfer data transmitted from an I/O card. CONSTITUTION:A control by a microprocessor is operated and plural I/O cards 11 are connected through bus extension cards 9 and 10, and a data transfer of a direct access memory system is operated between a CPU mounting circuit and a CPU non-mounting circuit. At the time of transferring data from a memory 19 on the I/O card 11 to a memory 13 on a CPU disc 8, a data transfer clock is delayed by a clock selecting circuit 17 by using a delayed clock (a) as the clock of an address counter 16, and the delay amounts of the data transfer clock and the transfer data are reduced. Thus, the data transfer using the high speed clock frequency can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microprocessor.
(Hereinafter abbreviated as CPU) CPU-equipped package (hereinafter abbreviated as CPU board) and CP in a device under control
U-uninstalled package (hereinafter referred to as I / O package)
The present invention relates to a data transfer system between the two and its circuit.

With the recent demand for high speed CPU control devices, high-speed data transfer is required between input / output devices (I / O cards) inside the device. For this reason, a so-called direct memory access method (hereinafter abbreviated as DMA method) for transferring data between the main storage device and each input / output device is used independently of the operation of the CPU.

According to this DMA system, when a CPU executes an input / output command, a command is given to a channel or a mechanism corresponding thereto, and data is controlled by the channel according to the command. Therefore, during DMA transfer, it is apparently disconnected from the bus, and high-speed data transfer is possible by directly transferring data between the memory and the input / output device. However, in order to perform higher speed data transfer, it is desired to increase the data transfer clock frequency.

[0004]

2. Description of the Related Art FIG. 5 shows a data transfer system of a conventional CPU controller. In the conventional CPU control device, data is transferred by a clock inside the CPU board 8. When the clock is transferred, as shown in the time chart of FIG. 6, the drivers and receivers of the bus expansion cards 9 and 10 are received. I / O card 1 due to internal delay
When data is DMA-transferred from the memory 19 on 1 to the memory on the CPU board 8, that is, the data returned from the I / O card 11 is delayed.

FIG. 6A shows the timing of the clock CLK at the position (a) shown in FIG. (b) is data on the transmitting side at the position (b) shown in FIG. 5, and is output based on the timing of the clock CLK. Also (c)
Indicates the received data at the position (c) shown in FIG. 5, and has a delay amount of TD with respect to the clock CLK.

[0006]

Since the conventional data transfer method has a delay as described above, it becomes impossible to secure a margin when the frequency of the clock is increased, which causes a decrease in the frequency of the data transfer clock. The upper limit is limited by the amount of delay of transfer data. Therefore, there has been a problem that it is impossible to transfer data at a higher speed. The present invention has been made in view of the above circumstances, and provides a data transfer system and a circuit therefor capable of speeding up a data transfer clock frequency as compared with a conventional data transfer system.

[0007]

FIG. 1 is a block diagram schematically showing the principle configuration of the present invention. FIG. 2 is a block diagram showing the basic configuration of the CPU board, bus expansion card and I / O card. Referring to FIG. 1, a first data transfer system according to the present invention is a system for controlling data by a microprocessor and connecting a plurality of I / O cards for data transfer by a direct memory access system.
The data transfer clock input to the side address counter 16 is delayed to reduce the difference in delay amount between the clock and the transfer data sent from the I / O card 11, thereby increasing the data transfer speed. It is characterized by making it possible.

The second data transfer method of the present invention is
As shown in FIG. 2, when data is transferred in the bus expansion card 10 in a system in which control is performed by a microprocessor, a plurality of I / O cards are connected through the bus expansion card, and data is transferred by a direct memory access system. By folding back the transfer clock, the difference in the delay amount between the data transfer clock and the transfer data sent from the I / O card 11 is reduced, thereby making it possible to increase the data transfer speed. ..

Further, the data transfer circuit for realizing the data transfer system of the present invention is controlled by a microprocessor, and a plurality of I / O cards 11 are connected via the bus expansion cards 9 and 10 to form a CPU. On-board circuit and CPU
In a data transfer circuit for performing data transfer between non-mounted circuits by the direct memory access method, when data is transferred from the memory 13 in the CPU mounted circuit to the memory 19 in the non-CPU mounted circuit, the first selection signal is output, and On the contrary, when transferring, when the selection signal output circuit which outputs the second selection signal and the internal clock of the CPU mounted circuit when the first selection signal is received and when the second selection signal is received And a clock selection circuit 17 for selecting a data transfer clock obtained by folding back the bus expansion card 10 and inputting it to an address counter 16 in a CPU mounting circuit.

[0010]

According to the present invention, when data is transferred from the memory 19 on the I / O card 11 to the memory 13 on the CPU board 8, the delayed clock (a) is set by the clock selection circuit 17. By delaying the data transfer clock by using it as the clock of the address counter 16 and reducing the delay amount between the data transfer clock and the transfer data, data transfer using a high-speed clock frequency is enabled.

[0011]

The present invention will be described in detail below based on the embodiments shown in the drawings. The present invention is not limited to this. FIG. 3 shows a data transfer circuit which is an embodiment of the present invention. In the figure, 8 is a CPU board on the side of the CPU mounted circuit, 9 and 10 are bus expansion cards, and 11 is an I / O card as an input / output device on the side of the circuit not equipped with the CPU.

The data in the memory 13 of the CPU board 8 is
When data is transferred to the memory of the I / O card 11, the address counter 16 that points to the address of the memory 13 operates according to the clock output from the clock selection circuit 17,
Specific data in the memory 13 is read out, and the data is transferred from the control bus interface of the I / O card 11 to the memory 19 via the control bus interface, the bus expansion card 9, the connection cable, and the bus expansion card 10. It In addition, from the memory 19 of the I / O card 11 to the CPU
When transferring data to the memory 13 of the panel 8,
The route is the reverse of the above.

Register 21 set by CPU 12
The clock selection circuit 17 is switched depending on the value of
When data is transferred from the memory 13 on the CPU board 8 to the memory 19 on the I / O card 11, the data is transferred by inputting the clock CLK1 to the address counter 16. In addition, from the memory 19 on the I / O card 11 to the CP
When transferring data to the memory 13 on the U board 8, the data is transferred by inputting the clock CLK2 to the address counter 16.

When switching the clock, the CP
U12 is identified where to access the I / O card in the same shelf or the I / O card in another shelf via the bus expansion card and register 21 The selection is made at.

The clock CLK1 represents an internal clock generated by the oscillator 14 and further converted into a predetermined frequency by the frequency dividing circuit 15. Also, the clock CLK2
Indicates a data transfer clock having a delay obtained by folding back the bus expansion card 10. That is, the clock selection circuit 17 is configured so that the clock of the address counter 16 can be selected from the internal clock of the CPU board 8 or the looped-back clock of the bus expansion card 10.

FIG. 4 is a flow chart showing the operation of the above data transfer circuit. (A) in the figure is (a) in FIG.
The position data transfer clock is shown. In the figure, (b) shows the return clock at the position (b) in FIG. In the figure, (c) shows the transfer data at the position (c) in FIG. In the figure, (d) shows the transfer data at the position (d) in FIG. As shown in FIG. 4, when data is transferred from the I / O card 11 to the CPU board 8, (b)
Since a clock having a delay is used as shown in, the delay amount between the data transfer clock and the transfer data is reduced as a result.

Next, in the data transfer, a case where the bus expansion card is not used (data transfer to an I / O card in the same shelf) and a case where the bus expansion card is used (I / O in a different shelf)
The operation of (data transfer to the card) will be described.

(1) CP without a bus expansion card
The clock selection circuit 17 switches the output of the frequency dividing circuit 15 inside the CPU board 8 directly to the address counter 16 according to the setting in the register 21 of the U12.

(2) When the bus expansion card is used, as described above, by the setting in the register 21 of the CPU 12,
The clock selection circuit 17 switches so as to select the clock returned from the bus expansion card 10. Therefore, it is possible to deal with I / O cards having different delays.

[0020]

As described above, according to the present invention, the transfer clock frequency can be increased as compared with the conventional data transfer system, thereby enabling the data transfer at a higher speed than the conventional one. Further, it greatly contributes to the performance improvement of the CPU control device to which this type of data transfer method is applied.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing the principle of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of FIG.

FIG. 3 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the embodiment.

FIG. 5 is a block diagram showing a conventional data transfer method.

FIG. 6 is a time chart showing a conventional operation.

[Explanation of symbols]

 1 Basic shelf 2 Expansion shelf 3 Bus expansion board 4 Bus expansion board 5,8 CPU board 6 I / O card 7,13 CPU board memory 9,10 Bus expansion card 11 I / O card 12 CPU 16 Address counter 17 Clock selection Circuit 18 Clock return circuit 19 I / O card internal memory

Claims (3)

[Claims] 1. Control by a microprocessor,
In addition, in the method of connecting a plurality of input / output devices and performing data transfer by the direct memory access method, the data transfer clock input to the address counter on the side of the CPU mounting circuit is delayed, and the data is sent from the clock and the input / output device. A data transfer method that enables faster data transfer speeds by reducing the difference in the amount of delay from the transfer data that is transferred. 2. Control by a microprocessor,
In addition, in a method in which a plurality of input / output devices are connected via a bus expansion card and data transfer is performed by the direct memory access method, the data transfer clock and the input / output device are turned off by folding the data transfer clock in the bus expansion card. A data transfer method that enables a higher data transfer speed by reducing the difference in the amount of delay from the transferred data that is sent out. 3. Control by a microprocessor,
Moreover, in the data transfer circuit for connecting the plurality of input / output devices (11) via the bus expansion card and performing the data transfer between the CPU mounted circuit and the non-CPU mounted circuit by the direct memory access method, the memory in the CPU mounted circuit ( A selection signal output circuit (21) which outputs a first selection signal when data is transferred from 13) to a memory (19) of a circuit not equipped with a CPU, and outputs a second selection signal when data is transferred in the opposite direction. And when the first selection signal is received, the internal clock of the CPU mounting circuit is selected, and when the second selection signal is received, the data transfer clock obtained by folding back the bus expansion card (10) is selected to mount the CPU. Clock selection circuit to be input to the address counter (16) in the circuit
(17) A data transfer circuit comprising: