JP3137036B2 - Emulation microcomputer and in-circuit emulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation microcomputer and an in-circuit emulator, and more particularly to an emulation microcomputer and an in-circuit emulator for emulating an interface signal when a power supply voltage fluctuates.

[0002]

2. Description of the Related Art Conventionally, in a system using a microcomputer, as shown at 17 in FIG. 8, a microcomputer 18 operating on a wide range of power supply voltage (5 V to 1.8 V) and a user system 19 are interfaced (see FIG. 8). I /
F) A configuration is generally used in which the control signal 22 and the bus 23 are connected to perform data transfer.

In this system, the microcomputer 18 adjusts the timing by using a delay circuit 20 to satisfy an AC specification (SPEC) such as a setup time and a hold time between the microcomputer 18 and a user system 19, and an interface by a logic circuit 21. In this configuration, a control signal 22 is generated and transmitted to the user system 19. Here, the number of the delay circuits 20 is m (m
(An integer of 2 or more) indicates a configuration in which inverters 24 _{1 to} 24 _m are connected in cascade.

Conventionally, such an emulation of the microcomputer 18 having a wide range of operating power supply voltage has a delay circuit 31 for timing adjustment and a logic circuit 32 as shown in FIG. A microcomputer for emulation (hereinafter, referred to as EVA CHIP) 28 that operates with a changed power supply has a wide range of power supply voltage (5 V to 5 V) through a level shifter 29.
About 1.8V) to the user system 19,
This is performed by the configuration 27 in which data transfer between the two is performed using the interface control signal 33 and the bus 34.

In the conventional emulation configuration 27, a circuit module which should be originally built in one chip is realized by combining an EVA CHIP 28 with a plurality of chips. Since the circuit modules connected in one chip are realized by a plurality of chips, when emulating the operation at high speed, the access timing of these interconnections may be a bottleneck. Therefore, it is necessary to operate the EVA CHIP 28 at a high power supply voltage of about 5V.

[0006]

However, in the actual conventional system configuration 17 shown in FIG. 8, the power supply voltage of the microcomputer 18 changes in accordance with the power supply voltage of the user system 19, so that the microcomputer 1
The delay time of the delay circuit 20 in FIG. For this reason, the timing of the interface control signal 22 also changes with a change in the power supply voltage of the user system 19.

FIGS. 11A, 11B, and 11C show that the power supply voltage VDD of the user system 19 is 5.0 V, respectively.
The waveform of the interface control signal 22 when it changes to 3.0V and 1.8V is shown. As described above, the interface control signal 22 changes with the fluctuation of the power supply voltage VDD.

On the other hand, in the conventional emulation configuration 27 shown in FIG. 10, since the power supply voltage on the EVACHIP 28 side is fixed to a constant value, even if the power supply voltage VDD of the user system 19 fluctuates, the EVA CHIP
The delay time of the delay circuit 31 in 28 is always a constant value. Therefore, even when the power supply voltage VDD of the user system 19 changes to 5.0 V, 3.0 V, and 1.8 V,
As shown in FIGS. 12A, 12B and 12C, the interface control signal 33 is constant regardless of the change in VDD.

For these reasons, EVA CHIP
In the conventional emulation configuration 27 shown in FIG. 10 using the configuration 28, there is a problem that the timing of the interface control signal 22 of the actual system configuration 17 shown in FIG. 8 cannot be correctly emulated.

[0010] The present invention has been made in view of the above points,
It is an object of the present invention to provide an emulation microcomputer and an in-circuit emulator that can emulate an interface control signal with accurate timing.

[0011]

In order to achieve the above object, an emulation microcomputer according to the present invention operates on a wide range of power supply voltages that adjusts timing by a delay circuit and outputs an interface control signal by a logic circuit. Microcomputer for emulating a microcomputer to be emulated,
Use the delay time of the delay circuit as the delay time according to the power supply voltage.
The delay time variable means which can be set by the user emulates a delay time according to the operating power supply voltage.

Further, in order to achieve the above object, the in-circuit emulator of the present invention has an emulation microcomputer for emulating a microcomputer operating on a wide range of power supply voltages, and an output interface control signal of the emulation microcomputer. And an in-circuit emulator connected to the user system by a bus, the emulation microcomputer generates an interface control signal by a logic circuit based on the signal adjusted by the delay circuit, and controls the delay time of the delay circuit of the user system. It has a configuration having means for variably controlling by the user according to the power supply voltage.

In the emulation microcomputer and the in-circuit emulator of the present invention, the delay time of the delay circuit in the emulation microcomputer is variably controlled according to the power supply voltage.
The timing of the output interface control signal can be varied according to the power supply voltage.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a data transmission system having one embodiment of an emulation microcomputer and an in-circuit emulator according to the present invention. This emulation configuration 1 includes a microcomputer for emulation (hereinafter referred to as EVA).
CHIP) 2, a level shifter 3, and a user system 4, which are connected via an interface control signal 11 and a bus 12. Also, EVA CHI
P2 and the level shifter 3 constitute an in-circuit emulator.

[0015] EVA CHIP2 is, n (n is an integer of 2 or more) and number of delay circuits 6 ₁ to 6 _n, from among the output signal of the delay circuit 6 ₁ to 6 _n, in response to the selection signal 8 one And a logic circuit 9 to which an output signal of the selection circuit 7 is input to generate and output an interface control signal. The selection signal 8 can be arbitrarily set by the user. The level shifter 3 is provided to absorb a difference between the power supply voltages of the EVA CHIP 2 and the user system 4.

Here, it is assumed that the user system 4 is a memory having an address data time division bus, and EVA C
The interface control signal 11 with the HIP 2 is an address strobe (ASTB) and a write enable signal (W
R) and a read enable signal (RD). The bus 12 is a time-division bus for address and data.

Next, regarding the operation of this embodiment, E
This will be described with reference to a timing chart showing the access timing of data transfer between the VA CHIP 2 and the user system 4. When data is called from the user system 4, first, the state of the ASTB goes high as shown in FIG. 2B in synchronization with the clock CLK shown in FIG. 2A, and an access address from the EVA CHIP2 to the bus 12 is obtained. Is output, and when ASTB changes from the high level to the low level, the user system 4 latches the data on the bus 12 as an address.

Next, when the RD signal goes high as shown in FIG. 2D, the data corresponding to the address previously latched from the user system 4 to the bus 12 is read as shown in FIG. It is read out and output as shown.
When the RD signal changes from a high level to a low level, the EVA CHIP 2 takes in data on the bus 12 input via the level shifter 3 as read data.

In the above access operation, when the RD signal changes from low level to high level, the bus 12
, The data collision may occur on the bus 12. Therefore, delaying the rise of the RD signal using a delay circuit 6 ₁ to 6 _n in EVA CHIP2, it has a configuration to avoid collision of the bus 12.

FIG. 3 is a circuit diagram of an emulation microcomputer according to an embodiment of the present invention. 2, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. 3, consists of a delay circuit 6 ₁ to 6 _n is an even number, respectively inverters and having different delay values from each other, delayed signal RD ORG signal as an input signal 5 is the original are input to the RD signal Occurs.

Each output signal of the delay circuits 6 _{1 to} 6 _n is supplied to a corresponding two-input AND circuit 14 ₁ to ₁ in the selection circuit 7.
4 _n is input to one input terminal of the AND circuit 14 ₁ where the AND circuit 14 ₁
Selection signal input to the other input terminal of ~14 _n 8 ₁ ~8 _n
Is ANDed with Here, ₁ to 8 _n selection signal 8, not become a high level at the same time, also a signal for the user to arbitrarily selected depending on the voltage of the user system 4.

[0022] Thus, the delay signal output from any one of the AND circuit of the AND circuit 14 ₁ to 14 _n are,
Logic circuit 9 through n-input OR circuit 15 in selection circuit 7
Is supplied to the AND circuit 16 in the R, and R shown in FIG.
It is ANDed with the DORG signal. Thereby, AN
The rise of RD ORG signal from D circuit 16, delayed by the delay time of the selected delay signal by the selection signal _{8 (8 1 ~8 n),} RD signal shown in FIG. 2 (D) is output,
Data collision on the bus 12 is avoided.

The actual system 1 shown in FIG.
7, the operating frequency is 10 MHz, and the EVA CHI
Data output delay from P18 to bus 23 is 2 ns, data output delay from user system 19 to bus 23 is 2 ns
clock when the operating power supply voltage of the EVA CHIP 18 is 5 V and the delay time of the delay circuit 20 is 2 ns;
The ASTB signal, the RD ORG signal, the RD signal, and the AD signal are shown in FIGS. 4A, 4B, 4C, and 4D, respectively.
It is assumed as shown in FIG.

In the actual system 17 shown in FIG. 8, the operating frequency is 5 MHz and the EVA CHIP 18
The data output delay from the user system to the bus 23 is 8 ns, the data output delay from the user system 19 to the bus 23 is 5 ns,
When the operating power supply voltage of the VA CHIP 18 is 1.8 V and the delay time of the delay circuit 20 is 8 ns, the clock A
The STB signal, RD ORG signal, RD signal, and AD signal are assumed as shown in FIGS. 5A, 5B, 5C, and 5D, respectively.

As can be seen from FIGS. 4 and 5, in the actual system 17, when the operating power supply voltage falls from 5V to 1.8V, the delay time of the delay circuit 20 is reduced from 2 ns to 8 ns. Because of the lower frequency, data collisions do not occur in real systems.

On the other hand, in the conventional emulation configuration 27, since the power supply voltage VDD of the EVA CHIP 28 is fixed to about 5 V, as described above, even if the power supply voltage of the user system 19 changes, the delay circuit 31 If the delay time does not change and the delay time is 8 ns, the emulation can be performed correctly when the power supply voltage of the user system 19 is 1.8 V.
In the case where the power supply voltage is 5 V, as shown in FIG. 6, the setup time of the RD signal for the clock of FIG. Cannot be emulated correctly as shown in FIG.

On the other hand, the delay time of the delay circuit 31 is set to 2
ns, the power supply voltage of the user system 19 is 5 V
Can be correctly emulated, but when the power supply voltage of the user system 19 is 1.8 V, as shown in FIG. 7, as compared with the actual system, the fall of the ASTB signal of FIG. Since the time difference between the rising edges of the RD signal of D) is only 2 ns, the user system 19 starts to output data before the output becomes high impedance after the EVA CHIP 28 outputs the address data. As shown in (1), data collide on the bus 34.

[0028] In contrast, according to this embodiment, by switching the selection signal 8 ₁ to 8 _n in accordance with the voltage of the user system 4, it can be adjusted to an optimum value the delay time of the RD signal So that accurate emulation is always possible. For example, 2 ns delay time of the delay circuit 6 _1,
If designed delay time of the delay circuit 6 _n to be 8 ns, when the voltage of the user system 4 is 5V selects the output delay signal of the delay circuit 6 _1, the voltage of the user system 4 1.8V In this case, by selecting the selection signal 8 so as to select the output delay signal of the delay circuit 6 _n , the timing of the actual interface control signal 22 can be accurately emulated without causing data collision on the bus 12. can do.

[0029]

As described above, according to the present invention,
The timing of the output interface control signal is varied according to the power supply voltage by variably controlling the delay time of the delay circuit in the emulation microcomputer according to the power supply voltage. The timing of the control signal can be accurately emulated.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data transmission system having one embodiment of the present invention.

FIG. 2 is a timing chart illustrating the access timing of FIG.

FIG. 3 is a circuit diagram of an emulation microcomputer according to an embodiment of the present invention.

FIG. 4 is a timing chart of access timing at a first power supply voltage in an actual system.

FIG. 5 is a timing chart of access timing at a second power supply voltage in an actual system.

FIG. 6 shows a first example of a conventional emulation system.
6 is a timing chart of access timing at the power supply voltage of FIG.

FIG. 7 shows a second example of the conventional emulation system.
6 is a timing chart of access timing at the power supply voltage of FIG.

FIG. 8 is a block diagram of an example of a data transmission system using a microcomputer.

FIG. 9 is a circuit diagram of an example of a delay circuit.

FIG. 10 is a block diagram of an example of a data transmission system having an example of a conventional in-circuit emulator.

FIG. 11 is a diagram showing a relationship between an interface signal and a power supply voltage of an actual data transmission system.

12 is a diagram showing a relationship between an interface signal and a power supply voltage of the data transmission system of FIG.

[Explanation of symbols]

1 A system having an embodiment of the present invention 2 A microcomputer for emulation (EVA
CHIP) 3 shifter 4 User System 5 delay circuit input signal 6 ₁ to 6 _n delay circuits 7 Selection circuit 8, 8 ₁ to 8 _n selection signal 9 the logic circuit 11 interface (I / F) control signal 12 bus 14 ₁ to 14 _n , 16 AND circuit 15 OR circuit

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/26 G06F 15/78

Claims (4)

(57) [Claims] 1. An emulation microcomputer which emulates a microcomputer which operates on a wide range of power supply voltage and adjusts timing by a delay circuit and outputs an interface control signal by a logic circuit, wherein the delay time of the delay circuit is controlled by the power supply. At delay according to voltage
A microcomputer for emulation, comprising delay time variable means that can be set by a user, and emulating a delay time according to the operating power supply voltage. 2. The method according to claim 1, wherein the delay time varying means includes a plurality of delay circuits having different delay times, and an output signal based on a selection signal selected by the user from output signals of the plurality of delay circuits. 2. A microcomputer for emulation according to claim 1, further comprising a selection circuit for selecting a selected one of the logic circuits and inputting the selected data to the logic circuit. 3. The emulation microcomputer according to claim 1, wherein each of the plurality of delay circuits has a cascade configuration of an even number of different inverters. 4. An in-circuit emulator having an emulation microcomputer for emulating a microcomputer operating on a wide range of power supply voltages and connected to a user system via an output interface control signal of the emulation microcomputer and a bus. Emulating microcomputer, while generating the interface control signal by a logic circuit based on the signal timing adjusted by the delay circuit,
An in-circuit emulator comprising means for variably controlling a delay time of the delay circuit by a user according to a power supply voltage of the user system.