JPH05265579A - Voltage dropping circuit - Google Patents

Abstract

PURPOSE:To facilitate the adjusting work of an output voltage by storing an output value from a sequence generation circuit when the output voltage coincides with a target value in a PROM circuit in a test mode, and adjusting the output voltage with a trimming circuit by conforming to a stored output value in an ordinary operation. CONSTITUTION:Clock signals phi1, phi2 are inputted to a counter circuit 5 in the test mode, and the count value of the circuit is inputted to the trimming circuit 8 via a selector circuit unit 7. The output voltage VL to a reference potential VR is adjusted corresponding to the count value, and the count value when the output potential VL coincides with a target value VT is stored in a PROM element 6. In an ordinary mode, the value stored in the PROM element 6 is outputted to the trimming circuit 8 via the selector circuit 7, and the output potential VL that coincides with the target value VT conforming to the count value stored in the PROM element 6, is outputted. Thereby, it is possible to facilitate the adjusting work of the output potential at a manufacturing stage, which improves productivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage drop circuit which facilitates adjustment work of an output voltage built in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 1 shows the IEEE Journal of Solid State Ci.
rcuits Vol.25, No.5, October 1990 1129 to 1130 is a circuit diagram of a voltage drop circuit in a conventional semiconductor integrated device, in which 8 is a trimming circuit for adjusting an output voltage V _L , 9 Is a differential amplifier, and 10 is a reference voltage generating circuit.

The reference voltage generating circuit 10 includes P-channel MOS field effect transistors (hereinafter simply referred to as P-channel MOSFETs) 101 and 102, the drains of which are current sources.
The source of the former is connected to the power source through 103, the source of the former is directly connected to the source of current, and the source of the latter is directly grounded. The gate and source of the P-channel MOSFET 101 are connected to the gate of the N-channel MOSFET 109 of the differential amplifier 9. The differential amplifier 9 is a P-channel MOSFET 105,10.
6. A current mirror composed of N-channel MOSFETs 108 and 109 and a P-channel MOSFET 107 are provided. P channel
The drains of the MOSFETs 105 and 106 are connected to the power source, and the sources thereof are grounded via the N-channel MOSFETs 108 and 109 and the current source 110, respectively.

The gates of both P-channel MOSFETs 105 and 106 are connected to each other, while the gate of N-channel MOSFET 108 is connected to trimming circuit 8 and the gate of N-channel MOSFET 109 is connected to reference voltage generating circuit 10 as described above. P
The drain of the channel MOSFET 107 is connected to the power supply, the source is connected to the output line 111 of the trimming circuit 8, and the gate is connected to the source of the channel MOSFET 106.

The trimming circuit 8 is the P of the differential amplifier 9.
An output line 111 connected to the source of the channel MOSFET 107 and a line 112 connected to the gate of the N-channel MOSFET 108 of the differential amplifier 9 are provided. A series circuit in which P-channel MOSFETs 113 and 114 and P-channel MOSFETs 115 and 116 are respectively connected in series is connected in parallel between the output line 111 and a line 112, and between the source of the P-channel MOSFET 114 and the line 112. Is provided with a fuse F ₁ . The gates of the P-channel MOSFETs 113 and 115 are connected to the source side thereof, and the gates of the P-channel MOSFETs 114 and 116 are connected to the line 112, respectively.

On the other hand, a plurality of P-channel MOSFETs 117 to 120 are connected in parallel between the line 112 and the ground. Fuses F ₂ , F ₃ , and F ₄ are provided between the P-channel MOSFETs 117 to 119 and the ground, respectively.

Next, the operation of such a conventional voltage drop circuit will be described. The potential of the node N1 of the reference voltage generation circuit 10 is V _TH2 when the threshold of the p-channel MOSFET 102 is V _TH2.
V _TH2 | The applied voltage V _R to the gate of the N-channel MOSFET 109 of the differential amplifier 9 which is the output voltage of the reference voltage generation circuit 10 is p-channel MOSFET 101 higher than that of the node N1.
The absolute value of the threshold | V _TH1 | because only low applied voltage V _R
= | V _TH2 | − | V _TH1 |.

Since the channel portion of the p-channel MOSFET 102 has a larger amount of n-type impurity ion implantation than the channel portion of the p-channel MOSFET 101, the absolute value of the threshold value | V _TH2 |
The absolute value of the threshold value of the SFET 101 is larger than | V _TH1 | and the applied voltage V _R is a value such as 1.1 V.

Further, in the differential amplifier 9, due to its current mirror, when the applied voltage V _F to the gate of the n-channel MOSFET 108 is lower than the applied voltage V _R to the gate of the n-channel MOSFET 109, the potential of the node N2 lowers accordingly and P The channel MOSFET 107 conducts more strongly, the output voltage V _L rises, and the applied voltage V _F rises accordingly. On the contrary, when the applied voltage V _R is lower than the applied voltage V _F , the potential of the node N2 rises accordingly, and the P-channel MOSFET
The resistance of 107 increases and the output voltage V _L decreases, which causes the potential of the applied voltage V _F to decrease and finally V _R.
= V _F is settled.

On the other hand, the trimming circuit 8 is constructed so that the output voltage V _L is resistance-divided to generate the applied voltage V _F. For example, when the division ratio is k, both of them are V _F = kV _L , in other words, the output voltage. The relationship is V _L = 1 / k · V _R. Therefore, as described above, when V _R = 1.1 V, for example, V _L = 3.3
In order to obtain V, k = 1/3 may be set. This is because, for example, the channel width W of the P-channel MOSFETs 113 to 120 is set to the P-channel MOSFETs 112 and 115 and the P-channel MO as shown in FIG.
Assuming that the total channel width of each of the SFETs 114 and 116 and the P-channel MOSFETs 117 to 120 is 112 μm, when the fuses F _{1 to} F ₄ are all conductive, the P of the channel width 112 μm is set.
The output voltage is 3.3 V because it corresponds to one stage of the three stages of channel MOSFETs connected in series.

By the way, a slight variation is inevitable in the manufacturing process of each of such elements, and the P-channel MOSFET 101
The difference in the threshold with 102 is not necessarily 1.1V. Thus adjusted by In the conventional blowing resistance division ratio k of the trimming circuit 8 fuses F ₁ to F _4, i.e. larger k to melt the fuse F _1, the fuse F ₂ to F
_The output voltage V _L is adjusted by fusing ₄ to reduce k.

[0012]

However, in such a conventional device, the output voltage V _L is measured and compared with a predetermined target value. If the output voltage V _L is different from the target value, the fuse F ₁ or F _{2 is used.} It is necessary to repeat the work of melting F ₄ to F ₄ , and there is a problem that productivity is poor. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a voltage drop circuit in which the adjustment of the output voltage is automated and the production efficiency can be improved.

[0013]

A voltage drop circuit according to the present invention includes a sequence generator, a trimming circuit that adjusts the output voltage according to an output value of the sequence generator in a test mode, and the output voltage. A PROM circuit that stores the output value from the sequence generator when it matches the target value, and an output value from the sequence generator that outputs a voltage corresponding to the output value stored in the PROM circuit in the normal mode. In place of the above, a switching means for inputting the output value from the PROM circuit to the trimming circuit is provided.

[0014]

According to the present invention, a sequence generator and a trimming circuit are provided, the output voltage is compared with a target value in the test mode, and the resistance division ratio of the trimming circuit is adjusted according to the output value of the sequence generator. The output value from the sequence generation circuit when the output voltage matches the target value is stored in the PROM circuit, and the trimming circuit is made to correspond to the output value stored in this PROM circuit during normal operation. The output voltage can be automatically set by adjusting the output voltage.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 2 is a block diagram of a voltage drop circuit according to the present invention, in which 1 denotes a comparator. In the test mode, the target value V _{T which} is the target voltage and the output voltage V _L fed back to the other input end are input to the comparator 1 in the test mode, and the difference signal V _T −V _L = φ _S Are three-input AND gates 2 and 3, respectively
Is input to each one of the input terminals.

The clocks CL ₀ and CL ₁ are input to the other input ends of the AND gates 2 and 3, respectively, and the test mode activation signal TE is input to the other input ends thereof. The three output terminals are connected to a counter circuit 5 which is a sequence generating circuit, and output clock signal signals φ ₁ and φ ₂ to the counter circuit 5, respectively.

4 is a power-on reset (referred to as POR)
Power supply voltage V _CC is input to the input terminal of the circuit,
Further, its output end is connected to the counter circuit 5 and the PROM circuit 6 and outputs the reset signal φ _R to them.

The counter circuit 5 is configured to be capable of counting from 0 to 7, and counts the clock signals φ ₁ and φ ₂ from the AND gates 2 and 3, and count signals A ₀ and A displayed in 3 bits. ₁ and A ₂ are output to the PROM circuit 6 and the selector circuit unit 7.

The PROM circuit 6 receives the count signal A input from the counter circuit 5 at the end of the test mode, that is, when the output voltage V _L coincides with or exceeds the target value V _T.
0 , A ₁ , A ₂ are stored, and the count signals A ₀ , A ₁ , A ₂ stored during normal operation are stored as signals B ₀ , B ₁ , B ₂
Is output to the selector circuit unit 7. In the test mode, the selector circuit unit 7 receives the count values A ₀ , A ₁ , which are the inputs from the counter circuit 5,
A ₂ and the signals B ₀ , B ₁ and B ₂ which are the inputs from the PROM circuit 6 during normal operation are output to the trimming circuit 8, respectively.

The specific configuration of each circuit will be described below. FIG. 3 is a circuit diagram showing a specific configuration of the POR circuit. Resistor 21 and capacitor connected in series to power supply voltage V _CC
22 and an inverting amplifier 23 having a cathode connected between the resistor 21 and the capacitor 22, and when the power is turned on, the potential of the node N3 gradually rises to a high level according to the time constant of the resistor 21 and the capacitor 22. It becomes “H” and the inverting amplifier
The reset signal φ _R of high level “H” is output for a predetermined time until the threshold value of 23 is exceeded.

FIG. 4 is a circuit diagram showing a specific configuration of the counter circuit 5, which includes register circuits 31, 32, 33. Each register circuit 31, 32, 33 includes a flip-flop 34 and a flip-flop 35 with reset, and each C contact of each flip-flop 34 is connected to the output terminal of the AND gate 2 and the clock signal φ ₁ Is input, and the S contacts are respectively the exclusive OR 36, 37, the output terminal of the inverting amplifier 38,
Further, each D contact is connected to the S contact of the corresponding flip-flop with reset 35.

On the other hand, each C contact of each flip-flop with reset 35 is connected to the output terminal of the AND gate 3 and the reset terminal R is connected to the output terminal of the POR circuit, respectively, and the clock signal φ ₂ , reset signal φ _R is input respectively.

The D terminal of the flip-flop 35 with reset is connected to the selector circuit unit 7 and outputs the count signals A ₀ , A ₁ and A ₂ , respectively, and the flip-flop 35 with reset in the register circuit 31 is exclusive. Of the exclusive OR gate 36, the D terminal of the flip-flop with reset 35 in the register circuit 32 is connected to one of the input terminals of the exclusive OR gate 37 and the AND gate 39, and the reset in the register circuit 33 is performed. With flip-flop
The D terminal of 35 is an inverting amplifier 38 and the exclusive OR gate.
37, and connected to the other input terminal of the AND gate 39, respectively. The output terminal of the AND gate 39 is connected to the other input terminal of the exclusive OR gate 36.

FIG. 5 is a circuit diagram showing the details of the latch circuit in the register circuit 31. The S terminal of the flip-flop 34 is an N-channel MOS field effect transistor (hereinafter simply referred to as N-channel MOSFET), P-channel MOS.
It is connected to a transmission gate 41 configured by combining a field effect transistor (hereinafter simply referred to as P-channel MOSFET), inverting amplifiers 42 and 43, and a transmission gate 44 connected in parallel with these inverting amplifiers 42 and 43, and The output terminal of the inverting amplifier 43 is connected to the D terminal, and this D terminal is connected to the S terminal of the flip-flop with reset 35.

The S terminal of the flip-flop with reset 35 is a transmission gate 46 which is also composed of an N-channel MOSFET and a P-channel MOSFET, inverting amplifiers 47 and 48, and a transmission gate 49 which is connected in parallel with these inverting amplifiers 47 and 48. The output terminals of the transmission gate 49 and the inverting amplifier 48 are connected to the D terminal.

The C terminal of the flip-flop 34 is directly or indirectly connected via an inverting amplifier 45 to the gate terminals of the transmission gates 43 and 44, and the clock signal φ ₁ is input to each of them. There is.

Similarly, the C terminal of the flip-flop with reset 35 is directly or indirectly connected to each gate terminal of the transmission gates 46 and 49 through the inverting amplifier 50, and the clock signal φ ₂ is input to them. It is supposed to do.

The R terminal of the flip-flop with reset 35 has an N channel whose drain is connected to each input terminal of the inverting amplifier 47 and transmission gate 49 and whose source is grounded.
It is connected to the gate of the MOSFET 51 and is adapted to give a reset signal φ _R to it. Other register circuits 32,3
Although 3 is not specifically shown, it is substantially the same.

In such a counter circuit 5, when the reset signal φ _R becomes high level “H”, the N channel
The MOSFET 51 is turned on, and the count signals A ₂ , A ₁ ,
All of A ₀ are zero. On the other hand, when the clock signals φ ₁ and φ ₂ are input in this state, the count values A ₂ , A ₁ and A _2
0 is counted up by 1 respectively, and thereafter, the count value is gradually increased each time the clock signals φ ₁ and φ ₂ are input.

FIG. 6 is a circuit diagram showing a specific configuration of the PROM circuit, which is provided with a plurality of semiconductor memory blocks 52, 53, 54 having substantially the same configuration, and the block 52 is specifically shown. In the figure, 55 and 56 are N-channel MOSFETs respectively, the former drain is connected to a normal power supply, the latter drain is connected to the high power supply voltage V _PP , and the sources are both fuses 57.
Is connected to one end of. The other end of the fuse 57 is grounded via an N-channel MOSFET 58, a resistor 59 and an N-channel MOSFET 60, respectively.

Further, the drain of the N-channel MOSFET 61 is connected between the fuse 57 and the resistor 59, and the source thereof is connected to the output terminal through the inverting amplifier 62, and the inverting amplifier 63 and the N-channel MOSFET 64 are interposed. Then, it is connected to the input terminal side of the inverting amplifier 62.

The output terminal of the counter circuit 5 is connected to the gate of the N-channel MOSFET 58, and the count value A _{0 is provided} here.
Is applied, and the gates of the N-channel MOSFETs 55, 60, 61, 64 are connected to the output terminal of the POR circuit 4 described above, and the reset signal φ _R or the inverted reset signal φ _R bar is input respectively. There is.

In such a PROM circuit 6, when the count value A ₀ from the counter circuit 5 is, for example, "1", the reset signal φ _R is low level "L" and the high power supply voltage V _PP is high. If set to high potential, N-channel MOSF
The ET 56 is turned on, a large current flows through the fuse 57, and the fuse 57 is blown. On the other hand, when the count value A ₀ from the counter circuit 5 is “0”, for example, the reset signal φ
_{Even if R is set} to the low level “L” and V _PP is set to the high potential, the N-channel MOSFET 58 remains off, and the fuse 57 is not blown.

When the power source of the semiconductor integrated circuit is turned on,
The reset signal φ _R of the POR circuit 4 stays at the high level “H” for a certain period of time, and the N-channel MOSFETs 55, 60, 61 are all turned on, but the resistance value of the fuse 57 is smaller than that of the resistor 59. When the value A ₀ is programmed with "0" and the fuse 57 is not blown, the potential of the node N4 becomes high level "H" and the output signal B ₀ becomes zero. On the other hand, when the count value A ₀ is programmed with "1" and the fuse 57 is blown, the potential of the node N4 becomes zero and the output signal B ₀ becomes "1".

FIG. 7 is a circuit diagram showing a specific configuration of the selector circuit unit 7, which comprises a plurality (three in the drawing) of selector circuits 65, 66, 67. Each selector circuit 65-67
Have substantially the same structure, and only the selector circuit 65 is shown. Selector circuit 65 is an N channel MOSFET, P channel MO
It has two sets of transmission gates 68 and 69 composed of SFETs. The count value A ₀ is at the input end of the transmission gate 68, and the output signal B ₀ from the PROM circuit 6 is at the input end of the transmission gate 69. It is supposed to be entered.

The test mode activating signal TE is inputted to the gate terminals of the transmission gates 68 and 69 directly or through the inverting amplifier 70. In the test mode, the test mode activation signal TE becomes high level “H”, the count value A ₀ of the counter circuit 5 becomes low, and in the normal operation, the test mode activation signal TE becomes low level “L”, and the PROM circuit 6 The output signal B ₀ is output as the output signal C ₀ to the trimming circuit 8 selectively.

FIG. 8 is a circuit diagram showing a concrete configuration of the trimming circuit 8, and a plurality of (8 in the drawing) 3-terminal ANDs.
Gates 71-78 and N-channel MOSFETs 81-88 are provided.
The signals C ₀ , C ₁ , C ₂ from the selector circuit unit 7 are directly input to the respective input terminals of the AND gates 71 to 78, or the inverted signals C ₀ bar, C ₁ bar, C are provided via the inverting amplifier 80.
₂ bars are designed to be entered. Each AND gate
The output terminals of 71 to 78 are connected to the gates of N-channel MOSFETs 81 to 88.

The drains of the N-channel MOSFETs 81 to 88 have resistors R _{2 to} R ₈ interposed therebetween, and one end thereof has a resistor R ₁ interposed therebetween so that the P of the differential amplifier 9 shown in FIG.
It is connected to the source of the channel MOSFET 91, and the other end is grounded via a resistor R ₉ . Furthermore, each N channel
The sources of the MOSFETs 81 to 88 are also N in the differential amplifier 9.
It is connected to the gate of the channel MOSFET 94.

Assuming that the resistance values of the resistors R _{2 to} R ₈ are R, the resistance value of the resistor R ₁ is 15R and the resistance value of the resistor R ₉ is 8R.
If signals C ₀ , C ₁ and C are set respectively,
_In response to each change of ₂ from "0" to "1", each AN
Since the output signals of the D gates 71 to 78 are high level “H”, the applied voltage V _F fed back to the gate of the N-channel MOSFET 94 of the differential amplifier 9 is 15/30 · V _L to 8/30.
_-Vary between V _L.

Next, the operation of the voltage drop circuit according to the present invention will be described with reference to the timing chart shown in FIG. Now, at time t ₁ , when the power supply voltage V _CC is applied to the semiconductor integrated device and the test mode is set as shown in FIGS. 9A and 9B, the power supply voltage V _CC is applied to the POR circuit 4. Reset signal φ _R becomes high level "H" for a predetermined time as shown in FIG. 9 (b).

When there is a difference between the target value V _T and the output voltage V _L in the comparator 41, the output φ _S is shown in FIG. 9 (f).
As shown in, the high level becomes “H” and the clock signal C
AND gates 2 and 3 each time L ₀ and CL ₁ go high
Of the clock signals φ ₁ and φ ₂ which are outputs of the counter circuit 5
Count up with, and output V _{F of} trimming circuit 8
Is k _{1 VL} . The count value is output to the trimming circuit 8 via the selector circuit unit 7. V _F 15
In the range of / 30 · _VL to 8/30 · _VL , the count values A ₀ , A ₁ , and A ₂ from the counter circuit 5 are sequentially changed, and the output voltage V is changed as shown in FIG. 9 (e). _L is getting higher.

For example, when the count values A ₀ , A ₁ , A ₂ from the counter circuit 5 are "0", the trimming circuit 8
Output signal V _F of k ₀ V _L , and thus V _R = V _F = k ₀ V
_The output voltage V _L becomes (1 / k ₀ ) V _R.

Generally, the count value of the counter circuit 5 is i
Then, the applied voltage V _F output from the trimming circuit 8 becomes k _{i VL} , but k _i decreases as the count value increases, so the output voltage V _L = (1 / k _i ) V
On the contrary, the value of _R increases. For example, the counter circuit 5
When the count value of 4 becomes 4 (cycle 4) in FIG. 9 (i), the output voltage V _L becomes equal to or larger than the target value V _T as shown in FIG. 9 (e). 1
, The output φ _S of the comparator 1 becomes zero, so that even if the clocks CL1 and CL2 are input thereafter, the AND gates 2 and 3
Outputs φ ₁ and φ ₂ are maintained at the low level “L”, the counter circuit 5 is in the idle state, and the count value does not change and remains in the state of V _L ≈V _T.

When 8 cycles have passed in this state,
The counter circuit 5 overflows, and at time t ₂ , a high voltage is applied to V _PP as shown in FIG.
As shown in FIG. 6, the count values A ₀ , A ₁ and A _{2 of the} counter circuit 5 are stored in the respective semiconductor memory blocks 52, 53 and 54 of the PROM circuit 6 by the fusing or non-fusing of the step-down circuit to form the step-down circuit program. It

After the programming is finished, the test mode activation signal as shown in FIG.
Set TE so that it is always at low level "L". The selector circuit unit 7 shown in FIG. 1 replaces the count values A ₀ , A ₁ and A ₂ of the counter circuit 5 with the output value B of the PROM circuit 6.
₀ , B ₁ and B ₂ are output to the trimming circuit 8 as output signals C ₀ , C ₁ and C ₂ .

The output signals C ₀ , C ₁ and C ₂ are signals B which store the count values A ₀ , A ₁ and A ₂ of the counter circuit 5.
₀ , B ₁ and B ₂ . Therefore, in the actual operation, the output voltage V _L is output as a value V _L ≈V _T close to the target value V _T. The configuration of the reference voltage generating circuit 10 is substantially the same as that of the conventional circuit shown in FIG.

The programming described above is not limited to the number of pins of the package if it is carried out during a wafer test, for example, and the test mode activating signal TE, the high power supply voltage V _PP and the target value V _T are externally applied by a probe. Is possible. Clock signals φ ₁ and φ _{2 of the} counter circuit 5
May use address pins, for example. Also, the test mode activation signal TE, the high power supply voltage V _PP and the target value V _T may be multiplexed with other signal pins.

Further, the comparator 1 of FIG. 1 is on-chip on the same semiconductor integrated circuit chip as the other regions 11, and the output pad of the output voltage V _{L and} the pad for inputting the signal φ _S are the same semiconductor integrated circuit chip. The comparator 1 installed on the tester and provided on the tester may be used. In this case,
Only the area 11 surrounded by the dotted line will be on-chip.

[0049]

As described above, according to the present invention, the output voltage can be adjusted automatically, the work of adjusting the output potential in the manufacturing stage is facilitated, and the productivity is improved. It is effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a conventional voltage drop circuit.

FIG. 2 is a circuit diagram of a circuit of the present invention.

FIG. 3 is a circuit diagram showing a specific configuration of a POR circuit used in the circuit of the present invention.

FIG. 4 is a circuit diagram showing a specific configuration of a counter circuit used in the circuit of the present invention.

5 is a circuit diagram showing a specific configuration of a latch circuit in the counter circuit shown in FIG.

FIG. 6 is a circuit diagram showing a specific configuration of a PROM circuit used in the circuit of the present invention.

FIG. 7 is a circuit diagram showing a specific configuration of a selector circuit unit used in the circuit of the present invention.

FIG. 8 is a circuit diagram showing a specific configuration of a trimming circuit used in the circuit of the present invention.

FIG. 9 is a timing chart showing the operation of the circuit of the present invention.

[Explanation of symbols]

 1 comparator 2, 3 AND gate 4 POR circuit 5 counter circuit 6 PROM circuit 7 selector circuit unit 8 trimming circuit 9 differential amplifier 10 reference voltage generation circuit

Claims (1)

[Claims] 1. A sequence generator circuit, a trimming circuit that adjusts an output voltage corresponding to an output value of the sequence generator circuit in a test mode, and a sequence generator circuit when the output voltage matches a target value. A PROM circuit for storing the output value, and a trimming circuit for the output value from the PROM circuit instead of the output value from the sequence generating circuit to output a voltage corresponding to the output value stored in the PROM circuit in the normal mode. And a switching means for inputting to the voltage drop circuit.