JPH05265400A - Driving method for liquid crystal display and its device - Google Patents

Abstract

PURPOSE:To enable displaying the prescribed half tone data by preventing occurrence of flicker and degradation of characteristics of a liquid crystal display panel. CONSTITUTION:Character data read out from a display memory 10 becomes display data 9 in a display data generating circuit 6, and supplied to a gate circuit 17. A counting value of a frame pulse signal 18 from a frame counter 14 and a counting value of a line pulse signal from a line counter 15 are supplied to a display control circuit 16, and a display inhibiting signal 21 is generated by using an attribute signal 20 from an attribute memory 11. Thus, a gate 17 inhibits passing of a display data 9 with the prescribed interval line in one frame, and changes successively a line which is inhibited to pass every frame. Therefore, flicker is inconspicuous and the prescribed half tone display can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a liquid crystal display device capable of displaying halftone and a device therefor.

[0002]

2. Description of the Related Art As a halftone display method in a liquid crystal display device, there is known a method realized by using a high speed blink display as disclosed in Japanese Patent Laid-Open No. 58-57192.

The conventional technique will be described below with reference to FIGS. FIG. 7 is a block diagram showing a conventional liquid crystal display device, in which 1 is a display address generating circuit, 2 and 3 are memories, 4 is a switching signal generating circuit, 5 is a memory switching circuit, 6 is a display data generating circuit, and 7 is a display data generating circuit. Is a liquid crystal display panel.

In the figure, the display address 8 from the display address generating circuit 1 is simultaneously input to the memories 2 and 3, and the character codes are output from the memories 2 and 3. A switching signal is supplied from the switching signal generation circuit 4 to the memory switching circuit 5, and the switching signal is at a “high” level (hereinafter,
"H"), the character code read from the memory 2 is sent to the display data generation circuit 6 via the memory switching circuit 5, and conversely, when the character code is "low" level (hereinafter "L"), the memory The character code read from 3 is supplied to the display data generating circuit 6 via the memory switching circuit 5. The level of the switching signal is inverted to “H”, “L”, “H”, ... For each display period of one screen on the liquid crystal display panel 1, and therefore the first screen (first frame) If the contents of the memory 2 are selected by the memory switching circuit 5 and supplied to the display data generating circuit 6 during the display of the same), the contents of the memory 3 are switched during the display of the next second frame. It is selected by the circuit 5 and supplied to the display data generation circuit 6. In the display data generation circuit 6,
The supplied character code is converted into a character pattern and output as display data 9 to the liquid crystal display panel 7.

On the other hand, assuming that the characters displayed on the liquid crystal display panel 7 are "A", "B", and "C", and the character "B" is to be displayed in halftone, the memory 2 is shown in FIG.
As shown in FIG. 8A, codes A, B, and C, which are codes representing the characters “A”, “B”, and “C”, are stored. In the memory 3, the codes are shown in FIG. 8B. Thus, the codes A and C, which are the codes representing the characters "A" and "C", are stored, but the code B representing the character "B" to be displayed in halftone is not stored. Therefore, when the memory switching circuit 5 alternately selects the outputs of the memories 2 and 3 for each frame as described above, in the liquid crystal display panel 7, in the first frame, as shown in FIG. The letter "A",
“B” and “C” are displayed respectively. In the second frame,
As shown in FIG. 9B, the characters “A” and “C” are displayed, but the character “B” is not displayed.

As described above, the characters "A" and "C" are displayed in all the frames, but the character "B" is repeatedly displayed and hidden for each screen. As a result, FIG. 9C is displayed. As shown, the letter "B" is displayed in halftone.

[0007]

However, if the frequency of the screen display is 60 Hz, the character "B" will be displayed repeatedly at 30 Hz, and halftone display will occur.
There was a drawback that flicker called flicker was noticeable.

Further, in order to prevent the characteristic deterioration due to the application of the DC voltage, the liquid crystal display panel 7 must be supplied with an AC-converted display data signal. Therefore, although not shown in FIG. 7, an alternating signal is applied to the liquid crystal display panel 7 to convert the polarity of the display data signal for each frame. That is, as shown in FIG.
An alternating signal is applied so that the display data signal having the polarity “+” is applied to the liquid crystal display panel 7 in the fifth frame and the display data signal having the polarity “−” in the second, fourth, and sixth frames.

On the other hand, in the conventional liquid crystal display device shown in FIG. 7, the character "B" to be displayed in halftone is displayed.
As for the display area of No. 2, since the display data signal is not output in the even frames, the polarities of the display data signals applied to the liquid crystal are “+”, “± 0”, and It becomes "+", "± 0", and "+".
Therefore, since the voltage is applied to the liquid crystal only in the odd frames and the polarity of the voltage is constant as “+”, the direct current voltage is applied to the liquid crystal due to the integration effect, which shortens the life of the liquid crystal panel. There was a problem of making it short.

An object of the present invention is to solve the problems of the prior art, to prevent the occurrence of flicker and the deterioration of the characteristics of the liquid crystal panel, and to realize a predetermined halftone display, and a method of driving the liquid crystal display device and a device therefor. To provide.

[0011]

In order to achieve the above object, the present invention has a liquid crystal display panel in which a large number of display block groups each having a plurality of display blocks arranged in the vertical direction are arranged and are continuous. In a method of driving a liquid crystal display device for displaying a display pattern according to the display data in a predetermined halftone over a plurality of frames, at least one display data of the display blocks in each display block group is displayed in one frame. The display pattern is displayed in a predetermined halftone by hiding the display data and displaying the display data of at least two display blocks that are vertically adjacent to each other.

Further, according to the present invention, a large number of display block groups having a plurality of display blocks arranged in the vertical direction are arranged, and a liquid crystal display panel for supplying display data to the plurality of display blocks is provided and is continuous. In a driving device of a liquid crystal display device that displays a display pattern according to display data in a predetermined halftone using a plurality of frames, a display block group in each frame for displaying the display pattern in a predetermined halftone A unit for controlling display / non-display of display data in units and the number of display blocks to be hidden in two consecutive frames in which at least one display data is hidden in each display block group. And a means for setting the number smaller than the number of blocks forming the display block.

[0013]

According to the present invention described above, at least one display data of display blocks is hidden in each display block group in each of a plurality of consecutive frames,
In order to display the display data of at least two display blocks that are vertically adjacent to each other, all display blocks are displayed in a plurality of consecutive frames, regardless of what halftone the predetermined halftone is, or Since there is no non-displayed frame, flicker called flicker does not occur, and a predetermined halftone can be obtained without flicker.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a method for driving a liquid crystal display device according to the present invention and an embodiment of the device, wherein 10 is a display memory, 11 is an attribute memory, 12 is an oscillator, 13 is a timing signal generating circuit, and 14 is a timing signal generating circuit. Is a frame counter, 1
Reference numeral 5 is a line counter, 16 is a display control circuit, 17 is a gate circuit, and parts corresponding to those in FIG.

In FIG. 1, the display memory 10 stores a code representing a character to be displayed, and the attribute memory 11 stores data representing whether or not halftone display should be performed for each character code in the display memory 10. Remembered Display address generation circuit 1 in synchronization with the clock from the oscillator 12.
The display address 8 is output from and is supplied to the display memory 10 and the attribute memory 11. A character code for a character to be displayed is output from the display memory 10 according to the display address 8 and supplied to the display data generation circuit 6 to generate display data 9 representing a pattern of characters corresponding to the character code. Further, an attribute signal 20 indicating whether or not the display data 9 output from the display data generating circuit 6 should be displayed in halftone is read from the attribute memory 11.
The attribute signal 20 is "H" for a character to be displayed in halftone and "L" for a character to be normally displayed.

On the other hand, the timing signal generating circuit 13 outputs a frame pulse signal 18 indicating the start of the screen and a line pulse signal 19 indicating the start of the line from the timing signal generating circuit 13 in response to the clock from the oscillator 12. Now, assuming that the number of screen lines on the liquid crystal display panel 7 is 200, for example, the line pulse signal 19 from the timing signal generation circuit 13 is 2
The frame pulse signal 18 is output every time 00 signals are output. The frame pulse signal 18 and the line pulse signal 19 are supplied to the liquid crystal display panel 17 to perform display in synchronization with them, and the frame pulse signal 18 is transmitted to the frame counter 14 and the line pulse signal 1
9 are supplied to the line counter 15, respectively.

Frame counter 14, line counter 1
The count value of 5 is supplied to the display control circuit 16. The display control circuit 16 uses the attribute signal 2 from the attribute memory 11.
When 0 becomes "H", the line number determined by the above count value is designated, and the display data 9 of the line corresponding to this line number of the character to be displayed in halftone is synchronized with the timing output from the display data generation circuit 6. And outputs the display prohibition signal 21. As a result, the gate circuit 17 is turned off, and the display data 9 of the designated line is not supplied to the liquid crystal display panel 7.

The line in which the display data 9 is blocked by the gate circuit 17 is different for each frame, and the character designated by this is displayed in halftone.

FIG. 2 shows the frame counter 1 in FIG.
4 is a block diagram showing a specific example of the line counter 15, the display control circuit 16, and the gate circuit 17,
Is a quarter divider circuit, 24 is a setting shift register, and 25
1 is a frame shift register, 26 to 29 are logical product circuits, 30 is a logical sum circuit, 31 is a negative logical output logical product circuit, 32 is a line shift register, and 33 is a logical product circuit, corresponding to FIG. The parts are given the same reference numerals.

Next, the operation of this specific example will be described with reference to FIG. 3. Here, the number of lines of one character is 8, and the display data 9 generated by the display data generation circuit 6 is 8.
It shall be composed of bits. Shift register 2
Each of 4, 25 and 32 has four output terminals and outputs a 4-bit structured value.

Now, the frame pulse signal 18 of P1 is input, and as shown in FIG.
It is assumed that the clock 44 is output from. This clock 4
4, the value stored in the initial value setting shift register 24 is set and initialized in the frame shift register 25. In this case, it is assumed that the output 36 of the frame shift register 25 is initialized to "H" and the outputs 37 to 39 are initialized to "L". Therefore, at this time, the output 34 of the initial value setting shift register 24 is "H" and the others are "L", but after the above initialization of the frame shift register 25, the clock 44 is used to set the initial value setting shift register. 24 is shifted by one step, its output 34 is inverted from "H" to "L", output 35 is inverted from "L" to "H", and the remaining outputs remain "L" to prepare for the next initialization. Is performed. Frame shift register 25
The output levels 36 to 39 are maintained until the next frame pulse signal 18 is input.

In this way, the frame pulse signal 1 of P1
8 is input and the frame shift register 25 is initialized. Then, when the line pulse signal 19 of P1 is input, the output 40 of the line shift register 32 is changed as shown in FIG. Other outputs 41 to 4 at "H"
3 becomes "L", at this time, the output 36 of the frame shift register 25 is "H" and the outputs 37 to 39 are
Is "L", only the output of the AND circuit 26 in the display control circuit 16 becomes "H", and the logical sum circuit 30 outputs the signal 45 of "H". In the line shift register 32, an output of "H" circulates every time four line pulse signals 19 are supplied. Therefore, 1, 5, ...
When the (1 + 4 × N) th line pulse signal 19 is supplied, the output of the AND circuit 26 becomes “H”, and the OR circuit 30 outputs the “H” signal 45.

On the other hand, the attribute memory 11 should be used for halftone display.
(FIG. 1) is outputting the attribute signal 20 of "H", the negative logical output AND circuit 31 outputs the first line, fifth, ..., (1 + 4 × N) of the first frame. ) The display prohibition signal 21 is output during the line display period. As a result, the display data 9 is not output to the liquid crystal panel 17 by the logical product circuit 33 of the gate circuit 17, and as shown in FIG. 5 lines are not displayed.

Next, as shown in FIG. 3 (a), when the frame pulse signal 18 of P2 is input, the frame shift register 25 shifts by one step, and its output 37 is "H", output 36, 38 and 39 are "L". When the line pulse signal 19 of P1 is input in this state, as shown in FIG.
As shown in (c), in the line shift register 32, the output 40 is "H" and the outputs 41 to 43 are "L". As a result, the AND circuit 26 of the display control circuit 16-
19 outputs an "L" signal.

However, the next P2 line pulse signal 19
Is input, the output 4 of the line shift register 32
Since 1 is "H" and outputs 40, 42, 43 are "L", the AND circuit 27 of the display control circuit 16 outputs a signal of "H" and the output 45 of the OR circuit 30 is "H". Becomes
The line shift register 32 receives the four line pulse signals 19 so as to make one cycle of "H" of the outputs 40 to 43. Therefore, the line of the logical sum circuit 30 of the 2, 6 ,. The output 45 becomes "H". At this time, since the attribute signal 20 of "H" is output from the attribute memory 11 for halftone display, the logical AND circuit 31 for outputting the negative logical product outputs the second, sixth, ..., Of the second frame. Second (2 + 4
The display prohibition signal 21 is output during the display period of the (N) line. As a result, as shown in FIG. 4B, in the second frame, the second and sixth lines of the pattern of the character A are not displayed.

Similarly, when the P3 and P4 frame pulse signals 18 are input (FIG. 4 (a)), in the third frame, as shown in FIG. 4 (c), the third and seventh lines are In the fourth frame, as shown in FIG.
The line is not displayed.

As described above, by changing the line that is not displayed for each frame, the character A is displayed in halftone as shown in FIG. 4 (e). Moreover, since the display of a part of the character pattern is turned off, the flicker becomes inconspicuous.

The above is for four frame periods. Next,
When the frame pulse signal 18 of P5 is input, as shown in FIG.
As shown in (a), a clock 44 is output from the 1/4 frequency dividing circuit 23. The clock 44 transfers the value stored in the initial value setting shift register 24 to the frame shift register 25, and as a result, the output 3
7 is "H", and outputs 36, 38, 39 are initialized to "L". Further, the clock 44 shifts the initial value setting shift register 24 by one step,
Preparations are made for the next initialization.

The operation of the line shift register 32 in the fifth frame thereafter is exactly the same as that described above.
As shown in FIG. 3C, the line pulse signal 19 of P1
Then, the output 40 of the line shift register 32 is "H".
Therefore, the output 41 of the line pulse signal 19 of P2 becomes "H". Therefore, similarly to the above, in the fifth frame, the output 41 of the line shift register 32 is "H" at the second, sixth, ..., (2 + 4 × N) th line.
Then, the display prohibition signal 21 is output from the display control circuit 16. As a result, as shown in FIG.
In the frame, the second and sixth lines of the pattern of the letter A are not displayed. Similarly, in the sixth frame, the third and seventh lines (FIG. 5B), in the seventh frame, the fourth and eighth lines (FIG. 5C), and in the eighth frame, The first and fifth lines (Fig. 5 (d)) are not displayed, respectively, and the character "A" is displayed in halftone as shown in Fig. 5 (e).

As described above, the halftone display of the character A can be performed while the relationship between the non-displayed frame number and the line number is sequentially changed every four frames.

Next, in this embodiment, it will be described with reference to FIG. 6 that no DC component is applied to the liquid crystal display panel as in the conventional liquid crystal display device shown in FIG.

Now, description will be made focusing on a specific line (first line). The alternating signal is alternately given as "+" and "-" for each frame, as in the case of the conventional technique. In the first frame, the AC signal is "+", but since it is hidden by the gate circuit 17 (FIG. 1), neither "+" nor "-" is applied to the liquid crystal display panel 7. In the next second frame, the alternating signal is "-" and the gate circuit 7 is turned on for display. Therefore, the display data signal of "-" polarity is applied to the liquid crystal display panel 7. In this way, the liquid crystal display panel 7 is applied with the display data signals of "+", "-", or "± 0".

However, as shown in FIG. 6, the alternating signal "+" and "-" makes one round in two frames, but the display ("±"
0 ") is one cycle every 5 frames and 5 frame periods, and the frames that are not displayed alternate between the frames where the alternating current should be" + "and the frames where it should be"-". Therefore, the voltage applied to the liquid crystal is "±
Therefore, the DC component is not applied to the liquid crystal display panel 7.

Although one embodiment of the present invention has been described above, in this embodiment, when attention is paid to a specific line, halftone display is performed once for every four frames. However, the present invention is not limited to this, and by changing the above conditions such as hiding twice in four frames, or hiding once in five frames, the above example is different from the luminance. It is possible to display different halftones.

[0035]

As described above, according to the present invention,
It is possible to realize a predetermined halftone display in which flicker is not noticeable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a method for driving a liquid crystal display device according to the present invention and the device.

FIG. 2 is a block diagram showing a specific example of a main part in FIG.

FIG. 3 is a timing chart for explaining the operation of the specific example of FIG.

FIG. 4 is an explanatory diagram showing an example of halftone display contents on a liquid crystal display panel.

FIG. 5 is an explanatory diagram showing another example of halftone display contents on a liquid crystal display panel.

6 is an explanatory diagram showing a polarity of an applied voltage in the liquid crystal display panel in FIG.

FIG. 7 is a block diagram showing an example of a conventional liquid crystal display device.

8 is a schematic diagram showing contents stored in respective memories in FIG. 7. FIG.

9 is an explanatory diagram showing an example of halftone display according to the conventional technique shown in FIG. 7. FIG.

10 is an explanatory diagram showing a polarity of an applied voltage in the liquid crystal panel in FIG.

[Explanation of symbols]

 1 Display Address Generation Circuit 6 Display Data Generation Circuit 7 Liquid Crystal Display Panel 10 Display Memory 11 Attribute Memory 13 Timing Signal Generation Circuit 14 Frame Counter 15 Line Counter 16 Display Control Circuit 17 Gate Circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Terumi Takashi Inventor Terumi Takashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Microelectronics Equipment Development Laboratory

Claims (4)

[Claims] 1. A liquid crystal display panel in which a large number of display block groups each having a plurality of display blocks arranged in a vertical direction are arranged, and the display data is displayed in a predetermined halftone over a plurality of consecutive frames. In a method of driving a liquid crystal display device displaying a display pattern, at least one of the display data of the display block is hidden in each of the display block groups in one frame, and at least two of the display blocks adjacent in the vertical direction are A method of driving a liquid crystal display device, wherein the display data of a display block is displayed to display the display pattern in the halftone. 2. The display block group according to claim 1, wherein in each of the display block groups, the number of the display blocks to be hidden in two consecutive frames in which at least one of the display data is hidden is the display. A method of driving a liquid crystal display device, characterized in that the number of blocks is smaller than the number of blocks. 3. A liquid crystal display panel in which a large number of display block groups having a plurality of display blocks arranged in the vertical direction are arranged, and display data is supplied to the plurality of display blocks, and a plurality of continuous frames are provided. In a driving device of a liquid crystal display device for displaying a display pattern according to the display data in a predetermined halftone, using the display block group in each frame in order to display the display pattern in the predetermined halftone. And means for controlling display / non-display of the display data, and the display to be hidden in two consecutive frames in which at least one of the display data is hidden in each of the display block groups. And a means for setting the number of blocks to be smaller than the number of blocks forming the display block. 4. The display unit according to claim 3, wherein in the display frame in which at least one of the display data is hidden, at least two display blocks that are vertically adjacent to each other in each display block group. 2. A drive device for a liquid crystal display device, wherein the display data of (1) is displayed.