JP3054149B2 - Liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of halftone display. 2. Description of the Related Art As a halftone display method in a liquid crystal display device, for example, as disclosed in Japanese Patent Application Laid-Open No. 58-57192, a method of realizing a high-speed blink display is known. . Hereinafter, such a conventional technique will be described with reference to FIGS. FIG. 7 is a block diagram showing a conventional liquid crystal display device, wherein 1 is a display address generation circuit, 2 and 3 are memories, 4 is a switching signal generation circuit, 5 is a memory switching circuit, 6 is a display data generation circuit, 7 Denotes a liquid crystal display panel. In FIG. 1, a display address 8 from a display address generating circuit 1 is inputted to memories 2 and 3 simultaneously.
Character codes are output from these memories 2 and 3. A switching signal is supplied from the switching signal generating circuit 4 to the memory switching circuit 5, and the switching signal is set to a "high" level (hereinafter, referred to as "high" level).
At the time of “H”, the character code read from the memory 2 is supplied to the display data generating circuit 6 via the memory switching circuit 5 and, conversely, at the “low” level (hereinafter, referred to as “L”).
At this time, the character code read from the memory 3 is supplied to the display data generation circuit 6 via the memory switching circuit 5. The level of the switching signal is inverted to “H”, “L”, “H”... In each display period of one screen on the liquid crystal display panel 7, so that the first screen (first screen) If the contents of the memory 2 are selected by the memory switching circuit 5 and supplied to the display data generation circuit 6 during the display of a frame (hereinafter the same), the contents of the memory 3 will be stored in the display of the next second frame. The data is selected by the switching circuit 5 and supplied to the display data generating circuit 6. In the display data generation circuit 6,
The supplied character code is converted into a character pattern and output to the liquid crystal display panel 7 as display data 9. On the other hand, assuming that the characters displayed on the liquid crystal display panel 7 are "A", "B", and "C" and that the character "B" is to be displayed in halftone, the memory 2 shown in FIG.
As shown in (a), codes A, B, and C, which are codes representing the characters "A", "B", and "C", are stored. In the memory 3, as shown in FIG. As described above, codes A and C representing codes "A" and "C" are stored, but code B representing character "B" to be displayed in halftone is not stored. Therefore, when the memory switching circuit 5 alternately selects the outputs of the memories 2 and 3 for each frame as described above, the liquid crystal display panel 7 displays the first frame of FIG.
As shown in (a), characters "A", "B", and "C" are displayed respectively. In the second frame, characters "A" and "C" are displayed as shown in FIG.
Is not displayed. As described above, the characters "A" and "C" are displayed in all frames, but the display and non-display of the character "B" are repeated for each screen. As a result, FIG. As shown, the letter "B" is a halftone display. [0008] However, if the frequency of the screen display is 60 Hz, the character "B" will be displayed at 30 Hz repetition, and although the halftone display will be performed,
There is a drawback that flicker called flicker is noticeable. Further, in order to prevent the characteristic deterioration due to the application of the DC voltage, the liquid crystal display panel 7 must be supplied with an alternating display data signal. For this purpose, although omitted in FIG. 7, an alternating signal is supplied to the liquid crystal display panel 7 to convert the polarity of the display data signal for each frame. That is, as shown in FIG.
In the frame, the display data signal having the polarity “+” is
In the 4th and 6th frames, an alternating signal is applied so that the display data signal having a polarity of "-" is applied to the liquid crystal display panel 7, respectively. On the other hand, in the liquid crystal display device according to the prior art shown in FIG.
Regarding the display area of FIG. 10, since the display data signal is not output in the even frame, as shown in FIG.
The polarity of the display data signal applied to the liquid crystal is “+”, “± 0”, “+”, “± 0”, and “+” for each frame. Therefore, a voltage is applied to the liquid crystal only in the odd-numbered frames, and the polarity of the voltage is fixed at "+". Therefore, a DC voltage is applied to the liquid crystal by an integration effect, and the life of the liquid crystal panel is reduced. There was a problem of shortening. It is an object of the present invention to provide a liquid crystal display device which solves the above-mentioned problems of the prior art, prevents the occurrence of flicker, and enables halftone display. In order to achieve the above object, the present invention provides at least one of a plurality of display blocks of a liquid crystal panel in each frame for displaying a predetermined halftone. The display data is hidden in the display block, the display data is displayed in the display block different from the hidden display block, and each of the display blocks is periodically switched every predetermined number of frames. A structure including a driving means for driving so as to perform non-display is adopted. According to the above-described structure, a halftone corresponding to the number of display times of the display data of each display block can be obtained, and each of the display blocks is periodically non-displayed every predetermined number of frames. Content flicker is not noticeable. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a liquid crystal display device according to the present invention, in which 10 is a display memory, 11 is an attribute memory, 12 is an oscillator, 13 is a timing signal generation circuit, 14 is a frame counter, and 15 is a line. A counter, 16 is a display control circuit, 17 is a gate circuit, and portions corresponding to those in FIG. In FIG. 1, a code is stored in a display memory 10 so as to represent a character to be displayed, and an attribute memory 11 stores data indicating whether or not halftone display is to be performed for each character code in the display memory 10. It is remembered. The display address 8 is output from the display address generation circuit 1 in synchronization with the clock from the oscillator 12 and supplied to the display memory 10 and the attribute memory 11. A character code for a character to be displayed is output from the display memory 10 in accordance with the display address 8 and supplied to the display data generating circuit 6 to generate display data 9 representing a character pattern corresponding to the character code. Also, from the attribute memory 11, an attribute signal 2 indicating whether or not the display data 9 output from the display data generating circuit 6 should be displayed in halftone.
0 is read. The attribute signal 20 is "H" for a character to be displayed in halftone and "L" for a character to be displayed normally. On the other hand, the timing signal generating circuit 13 outputs a frame pulse signal 18 indicating the start of a screen and a line pulse signal 19 indicating the start of a line by the clock from the oscillator 12. For example, if the number of lines on the screen of the liquid crystal display panel 7 is 200, the timing signal generation circuit 13 outputs a line pulse signal 19
Are output every time 200 are output. The frame pulse signal 18 and the line pulse signal 19 are supplied to the liquid crystal display panel 17, and display is performed in synchronization with the liquid crystal display panel 17. The frame pulse signal 18 is supplied to the frame counter 14, and the line pulse signal 19 is supplied to the line counter 15 Respectively. Frame counter 14, line counter 1
The count value of 5 is supplied to the display control circuit 16. When the attribute signal 20 from the attribute memory 11 becomes "H", the display control circuit 16 designates a line number determined by the count value, and displays display data of a line corresponding to the line number of a character to be displayed in halftone. 9 is a display data generation circuit 6
Display inhibit signal 21 in accordance with the timing output from
Is output. As a result, the gate circuit 17 is turned off,
The display data 9 of the designated line is not supplied to the liquid crystal display panel 7. The line where the display data 9 is cut off by the gate circuit 17 differs for each frame, and the designated character is displayed in halftone. FIG. 2 shows the frame counter 1 in FIG.
4, a block diagram showing a specific example of a line counter 15, a display control circuit 16, and a gate circuit 17, wherein 23 is a 1/4 frequency dividing circuit, 24 is a setting shift register, 25 is a frame shift register, 26 To 29 are AND circuits,
30 is a logical sum circuit, 31 is a logical product circuit of negative logic output, 3
2 is a line shift register, and 33 is a logical product circuit, and portions corresponding to those in FIG. Next, the operation of this specific example will be described with reference to FIG. 3. Here, the number of lines of one character is eight, and the display data 9 generated by the display data generation circuit 6 is eight.
It is assumed that it is composed of bits. Each of the shift registers 24, 25 and 32 has four output terminals,
Outputs the bit configuration value. Now, it is assumed that the frame pulse signal 18 is inputted and a clock 44 is outputted from the 1/4 frequency dividing circuit 23 as shown in FIG. This clock 44
Accordingly, in the frame shift register 25, the value stored in the initial value setting shift register 24 is set and initialized. In this case, it is assumed that the output 36 of the frame shift register 25 is initialized to “H” and the outputs 37 to 39 are initialized to “L”. Therefore, at this time,
Although the output 34 of the initial value setting shift register 24 is "H" and the others are "L", the initial value setting shift register 24 is shifted by one step by the clock 44 after the initialization of the frame shift register 25. Then, the output 34 is inverted from “H” to “L”, the output 35 is inverted from “L” to “H”, and the other outputs are kept at “L”, and preparations for the next initialization are made. Output 3 of frame shift register 25
The levels of 6 to 39 are held until the next frame pulse signal 18 is input. As described above, the frame pulse signal 18
Is input to initialize the frame shift register 25. When the subsequent line pulse signal 19 is input, as shown in FIG. 3B, the output 40 of the line shift register 32 becomes "H". If the other outputs 41 to 43 become "L", the output 36 of the frame shift register 25 is "H" and the outputs 37 to 39 are "L". Then, only the output of the AND circuit 26 becomes "H", and the "H" signal 45 is output from the OR circuit 30. In the line shift register 32, the output of “H” circulates every time the four line pulse signals 19 are supplied.
When the (1 + 4 × N) th line pulse signal 19 is supplied, the output of the AND circuit 26 becomes “H”, and the OR circuit 30 outputs the “H” signal 45. On the other hand, the attribute memory 11 is used to display halftones.
(FIG. 1) outputs the attribute signal 20 of "H", the AND circuit 31 of negative logic output outputs the first line of the first frame, the fifth line,..., (1 + 4 × N) The display inhibit signal 21 is output during the display period of the line. as a result,
The display data 9 is calculated by the AND circuit 33 of the gate circuit 17.
Is not output to the liquid crystal display panel 17, and as shown in FIG. 4A, the first and fifth lines of the pattern of the character A are not displayed in the first frame. Next, as shown in FIG. 3 (a), when the frame pulse signal 18 is input, the frame shift register 25 shifts by one step, the output 37 thereof becomes "H", and the outputs 36 and 38. , 39 become “L”. When the line pulse signal 19 in this state is input, FIG.
As shown in (c), in the line shift register 32, the output 40 is “H” and the outputs 41 to 43 are “L”. As a result, the AND circuits 26 to 26 of the display control circuit 16
29 outputs an "L" signal. However, when the next line pulse signal 19 is input, the output 41 of the line shift register 32 is output.
Becomes "H" and the outputs 40, 42 and 43 become "L".
The AND circuit 27 of the display control circuit 16 outputs a signal of “H”, and the output 45 of the OR circuit 30 becomes “H”. The line shift register 32 has four line pulse signals 19
, The output 45 of the OR circuit 30 becomes "H" in the (2 + 4.times.N) -th line in order to make "H" of the outputs 40 to 43 make a full circuit. At this time, since the attribute signal 20 of "H" is output from the attribute memory 11 to display the halftone,
The negative AND output AND circuit 31 outputs the display inhibition signal 21 in the second, sixth,..., And (2 + 4 × N lines) display periods of the second frame. As a result, FIG.
As shown in (2), in the second frame, the second and sixth lines of the pattern of the character A are not displayed. Similarly, the frame pulse signal 18
Is input (FIG. 3A), in the third frame,
As shown in FIG. 4C, the third and seventh lines are not displayed in the fourth frame, and as shown in FIG. 4D, the fourth and eighth lines are not displayed. As described above, by making the non-displayed line different for each frame, the character A is displayed in halftone as shown in FIG. In addition, since the display of a part of the character pattern is turned off, flicker becomes inconspicuous. The above is a 4-frame period.
When the frame pulse signal 18 of FIG.
As shown in (a), a clock 44 is output from the 1/4 frequency dividing circuit 23. The value stored in the initial value setting shift register 24 is transferred to the frame shift register 25 by the clock 44, and as a result, the output 3
7 is initialized to "H" and outputs 36, 38 and 39 are initialized to "L". Further, the initial value setting shift register 24 is shifted by one step by the clock 44,
Preparations for the next initialization are performed. The operation of the line shift register 32 in the subsequent fifth frame is exactly the same as the operation described above.
As shown in FIG. 3C, in the line pulse signal 19, the output 40 of the line shift register 32 becomes “H”, and in the line pulse signal 19, the output 41 becomes “H”. Therefore, as described above, in the fifth frame, when the output 41 of the line shift register 32 becomes “H” in the second, sixth,..., (2 + 4 × N) -th lines, the display is performed. The display prohibition signal 21 is output from the control circuit 16. As a result, as shown in FIG.
In the frame, the second and sixth lines of the character A pattern are not displayed. Similarly, in the sixth frame, the third and seventh lines are (FIG. 5B), and in the seventh frame,
The fourth and eighth lines are (FIG. 5 (c)), and in the eighth frame, the first and fifth lines (FIG. 5 (d)) are not displayed, respectively, and as shown in FIG. "A" is displayed in halftone. As described above, the halftone display of the character A can be performed while the relationship between the undisplayed frame number and the line number is sequentially changed every four frames. Next, in this embodiment, the fact that no DC component is applied to the liquid crystal display panel 7 as in the conventional liquid crystal display device shown in FIG. 7 will be described with reference to FIG. Now, description will be made focusing on a specific line (first line). The alternating signal is provided alternately with "+" and "-" for each frame, as in the case of the prior art. In the first frame, the alternating signal is “+”, but since it is not displayed by the gate circuit 17 (FIG. 1), neither “+” nor “−” is applied to the liquid crystal display panel 7. In the next second frame, the alternating signal is “−”, and the gate circuit 17 is turned on for display. Therefore, a display data signal of “−” polarity is applied to the liquid crystal display panel 7. As described above, the display data signal of “+”, “−”, or “± 0” is applied to the liquid crystal display panel 7. However, as shown in FIG. 6, although the alternating signal has one cycle of "+" and "-" in two frames, it is displayed ("±").
“0”) is one cycle in five frames and a period of five frames, and the non-displayed frames are alternated between frames in which the alternating current should be “+” and frames in which the alternating current should be “−”. Therefore, the voltage applied to the liquid crystal averages “±
0 ", and no DC component is applied to the liquid crystal display panel 7. The embodiment of the present invention has been described above.
In this embodiment, when attention is paid to a specific line, non-display is performed once in four frames, and halftone display is performed. But,
In the present invention, the brightness is different from the above-described example by changing the above-described condition, such as not displaying twice in four frames or not displaying once in five frames. It is possible to perform halftone display. Therefore, for example, by preparing a plurality of types of non-display times and the like and combining them, a plurality of types of gradation display can be performed. That is, the first gradation is once every four frames, the second gradation is once every five frames, and the third gradation is twice every four frames. By selecting, a plurality of types of gradation display can be performed. As described above, according to the present invention,
Since each display block is not displayed periodically every predetermined number of frames, it is possible to realize a halftone display in which flicker is inconspicuous.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a liquid crystal display device according to the present invention. FIG. 2 is a block diagram showing a specific example of a main part in FIG. FIG. 3 is a timing chart for explaining the operation of FIG. 2; FIG. 4 is an explanatory diagram showing halftone display contents on a liquid crystal display panel. FIG. 5 is an explanatory diagram showing halftone display contents on a liquid crystal display panel. 6 is an explanatory diagram showing the polarity of an applied voltage in the liquid crystal display panel in FIG. FIG. 7 is a block diagram illustrating an example of a conventional liquid crystal display device. FIG. 8 is a schematic diagram showing contents stored in respective memories of FIG. 7; FIG. 9 is an explanatory diagram showing an example of a halftone display according to the prior art shown in FIG. 7; FIG. 10 is an explanatory diagram showing a polarity of a voltage in a liquid crystal display pulse in FIG. 7; [Description of Signs] 1 display address generation circuit 6 display data generation circuit 7 liquid crystal display panel 10 display memory 11 attribute memory 13 timing signal generation circuit 14 frame counter 15 line counter 16 display control circuit 17 gate circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Terumi Takashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Yokohama, Japan Microelectronics Equipment Development Laboratory Hitachi, Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) ) G09G 3/36 G02F 1/133 G09G 3/20

Claims (1)

(57) [Claims] The liquid crystal display panel includes a plurality of display blocks, and for each of a plurality of continuous frames, includes a liquid crystal display panel to which display data is supplied to the plurality of display blocks, and the plurality of display blocks of the liquid crystal display panel include: In a liquid crystal display device that displays a display pattern corresponding to the display data by alternately applying a voltage corresponding to the display data of the positive polarity and a voltage corresponding to the display data of the negative polarity for each frame, To show the key, in each frame:
The display data is hidden in at least one of the plurality of display blocks, the display data is displayed in another display block different from the hidden display block, and the display block is Each of the display blocks periodically becomes non-display every predetermined number of frames, and in each of the display blocks, the non-display frames are evenly distributed between a frame to which a positive voltage is applied and a frame to which a negative voltage is applied. A liquid crystal display device. 2. 2. The liquid crystal display device according to claim 1, wherein the driving unit is capable of changing a ratio of the display block to be displayed and the display block to be non-displayed according to a halftone to be displayed.