JPH05264670A - Method for narrowing down faulty position of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily and precisely detect a true electric fault position by using DFI image in a time interval shorter than that of a test pattern. CONSTITUTION:When a fault position of a LSI chip is narrowed by DFI (Dynamic Fault Imaging) method which is one of electric beam probing methods, the generating timing of fault is caught at the precision of the time width of a test pattern (test vector). By reviewing the test pattern back in time (t), for example, fault suspected positions 10, 11 can be detected in the test pattern corresponding to time t0. It is not recognized which position is a true fault position. Thus, the time t0 is divided into (n), times t01, t02,...ton, and DFI images are picked up at the divided time intervals. Consequently, the suspected position 11 is extinguished at the time t02 where 'detection' is shown, and only the suspected position 10 is left. Thus, the pseudo electric fault generating position 11 can be discriminated from the true electric fault generating position 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test / analysis of a semiconductor integrated circuit by a probing method.

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to electron beam probing, when analyzing defective or defective semiconductor integrated circuits.
The present invention relates to a method of narrowing down a failure location by using a probing method such as laser beam probing.

[0003]

2. Description of the Related Art DFI (Dynamic Fault Image), which is one of electron beam probing techniques, is used.
The conventional technique will be described by taking a method called "ng)" as an example. The DFI method obtains an image (fault image) of the difference between strobe images (potential distribution images by the strobe method) of both a defective product or a defective product (hereinafter, defective product) and a non-defective product corresponding to the defective product or the defective product. By clearly indicating the electrical failure point and investigating the failure image, the electrical failure occurrence point is detected,
It is a method for supporting the detection of physical failure points. Normally, acquisition and editing of DFI images (defective product image, non-defective product image, failure image) are performed on a workstation. Conventionally, D
When narrowing down the failure point by the FI method, the occurrence timing of the failure is grasped with the accuracy of the time width of the test pattern (test vector).

FIG. 2 shows the concept of narrowing down by the conventional method. The vertical axis is the axis (X, Y) that represents the two-dimensional surface of the chip surface in one dimension, the upper part is the bonding pad part 3 on the chip, and the lower part is the central part 4 on the chip. The horizontal axis is the time axis (t). The arrow 6 indicates the flow direction of the test pattern (test vector), and the arrow 7 indicates the flow direction of the narrowing down by DFI. 10 and 11 are DFI
It is the position on the space-time coordinates where it is judged from the image that an electrical failure has occurred (failure occurrence recognition time t _o ), 10 is the true electrical failure occurrence point, and 11 is the pseudo electrical failure occurrence. The location is shown.

In this device, an electrical failure point reached a bonding pad in a test pattern corresponding to t _f on the time axis in the figure, and it was detected as a failure from a lead terminal of a package of an integrated circuit. In the conventional method, by tracing back this test pattern to the younger one, the suspected failure location could be detected in the test pattern corresponding to time t _o . Since the failure occurrence time that can be detected by the conventional method has a width corresponding to the time width of the test pattern, not only the true electrical failure occurrence location 10 but also the pseudo electrical failure occurrence location 11 is detected as the suspected failure location. Has been done. It was necessary to use other means to determine which of these locations was the true failure location.

[0006]

As described above, DF
When narrowing down the failure points by the I method, the timing of failure occurrence is captured with the accuracy of the time width of the test pattern (test vector). A breakdown occurs,
It was difficult to distinguish from the true failure point.

It is an object of the present invention to provide a method for narrowing down a failure part of a semiconductor integrated circuit, which solves the above problems.

[0008]

A method of narrowing down a failure point of a semiconductor integrated circuit according to the present invention is a failure analysis method using a probing result of a non-defective product, a defective product and a difference obtained by using a probing method of a semiconductor integrated circuit chip. When narrowing down, the failure source test pattern is further divided into sub phases to narrow down the failure points closer to the source.

[0009]

The purpose of the present invention is to use a DFI image at a time interval shorter than the test pattern. By using a DFI image at a time interval shorter than the test pattern, a true electrical failure point can be found. Like

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A faulty device, which is used in the description of the prior art and has a method of generating and transmitting a fault as shown in FIG. As described above, according to the conventional method, by tracing back this test pattern to a younger time, the suspected failure portion can be detected in the test pattern corresponding to the time t _o . In the example of FIG. 2, three locations are detected as failure suspected locations. It was necessary to use other means to determine which of these locations was the true failure location.

FIG. 1 shows an example of narrowing down true electrical failure occurrence points according to the present invention. After narrowing down to the stage of FIG. 2 with the same device as that of FIG. 2, the time t _{o is changed} to the time t as shown in FIG.
_{o1, t o2, t o3,} t o4, ··· t and _On and n division, it took the DFI image in divided time width. As a result, "discovery" is shown in the figure.
At time t _O2 described above, the other two fault suspected points disappeared and only one point remained. In this way, it becomes possible to distinguish the pseudo electric failure occurrence point 11 from the true electric failure occurrence point 10.

[0012]

As described above, in the conventional method, the presence / absence of an electrical failure is grasped with the accuracy of the time width of the test pattern (test vector). Therefore, even in a location other than the electrical failure location within the same time width. When an electrical failure occurred, it was difficult to distinguish it from the true failure point. In the present invention, by using the failure information at a time interval shorter than the test pattern, the true electrical failure location can be found more easily and accurately than before.

As a result, the efficiency and success rate of failure analysis of the integrated circuit are significantly improved, and the development / design / manufacturing /
Significant improvements can be made in all aspects of delivery / accuracy / cost in all phases of shipping / claim handling from users.

[Brief description of drawings]

FIG. 1 illustrates the concept of narrowing down the DFI according to the method of the present invention.

FIG. 2 shows a concept of narrowing down by a conventional method of DFI.

[Explanation of symbols]

 2 Time axis (t) 3 Bonding pad part on chip 4 Central part on chip 6 Direction of flow of narrowing down by DFI 7 Direction of flow of test pattern (test vector) 10 True electrical failure occurrence point 11 Pseudo electric Location of static failure

Claims (1)

[Claims] 1. A failure source test pattern is further divided into sub phases when narrowing down a failure analysis by using a probing result of a non-defective product, a defective product, and a difference between them obtained by a probing method of a semiconductor integrated circuit chip. By doing so, a method of narrowing down the fault location closer to the source.