JPH0526218B2 - - Google Patents
Info
- Publication number
- JPH0526218B2 JPH0526218B2 JP1338898A JP33889889A JPH0526218B2 JP H0526218 B2 JPH0526218 B2 JP H0526218B2 JP 1338898 A JP1338898 A JP 1338898A JP 33889889 A JP33889889 A JP 33889889A JP H0526218 B2 JPH0526218 B2 JP H0526218B2
- Authority
- JP
- Japan
- Prior art keywords
- cache
- memory
- line
- buffer
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
- 
        - G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
 
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Information Transfer Systems (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| US29771289A | 1989-01-13 | 1989-01-13 | |
| US297712 | 1989-01-13 | 
Publications (2)
| Publication Number | Publication Date | 
|---|---|
| JPH02226448A JPH02226448A (ja) | 1990-09-10 | 
| JPH0526218B2 true JPH0526218B2 (OSRAM) | 1993-04-15 | 
Family
ID=23147428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date | 
|---|---|---|---|
| JP1338898A Granted JPH02226448A (ja) | 1989-01-13 | 1989-12-28 | 入出力キヤツシユ | 
Country Status (3)
| Country | Link | 
|---|---|
| EP (1) | EP0377971B1 (OSRAM) | 
| JP (1) | JPH02226448A (OSRAM) | 
| DE (1) | DE68921869T2 (OSRAM) | 
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title | 
|---|---|---|---|---|
| US5842041A (en) * | 1994-05-20 | 1998-11-24 | Advanced Micro Devices, Inc. | Computer system employing a control signal indicative of whether address is within address space of devices on processor local bus | 
| JP2748862B2 (ja) * | 1994-06-15 | 1998-05-13 | 日本電気株式会社 | バスインタフェースアダプタ | 
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title | 
|---|---|---|---|---|
| US4481573A (en) * | 1980-11-17 | 1984-11-06 | Hitachi, Ltd. | Shared virtual address translation unit for a multiprocessor system | 
- 
        1989
        - 1989-12-11 EP EP89312897A patent/EP0377971B1/en not_active Expired - Lifetime
- 1989-12-11 DE DE68921869T patent/DE68921869T2/de not_active Expired - Fee Related
- 1989-12-28 JP JP1338898A patent/JPH02226448A/ja active Granted
 
Also Published As
| Publication number | Publication date | 
|---|---|
| EP0377971A3 (en) | 1991-03-20 | 
| DE68921869T2 (de) | 1995-10-12 | 
| EP0377971B1 (en) | 1995-03-22 | 
| EP0377971A2 (en) | 1990-07-18 | 
| JPH02226448A (ja) | 1990-09-10 | 
| DE68921869D1 (de) | 1995-04-27 | 
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