JPH05260110A - Receiver for digital communication - Google Patents

Abstract

PURPOSE:To reduce the circuit constitution, to simplify the design and the adjustment, and to make a device small-sized and low-cost. CONSTITUTION:In-phase and orthogonal components obtained by demodulating a received digital phase modulated signal by a demodulator 1 are subjected to A/D conversion by A/D converters 2 and 3, and digitized in-phase and orthogonal components are equalized by an equalizer 4 to reproduce digital data. A detecting circuit 5 detects the envelope of the digital phase modulated signal to detect the amplitude of this signal. A/D converters 2 and 3 subject in-phase and orthogonal components to A/D conversion with the amplitude detected by the detecting circuit 5 as a reference voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication receiver, and more particularly to a digital communication receiver for receiving a digital phase modulation signal.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional communication device for digital communication.

In the figure, a high frequency signal of a 4-phase digital phase modulated signal (QPSK signal) received by an antenna 11 is separated by a bandpass filter 12, amplified by a low noise amplifier 13, and then a down converter (DC) 14 Then, the frequency is converted into a low frequency band and is supplied to an automatic gain control circuit (AGC) 15, where the amplitude is kept constant. This QPSK signal is branched into two in the hybrid 16 and supplied to the QPSK demodulation circuit (DEM) 17, and the carrier wave reproduced here and the carrier wave obtained by phase-shifting it by π / 2 are synchronously detected, The I and Q signals are reproduced. I, Q
The signals are digitized by the AD converters (A / D) 18 and 19, respectively, and then the transmission distortion is compensated by the adaptive equalizer (EQ) 20 and output from the terminal 21 as a digital signal.

[0004]

When this receiver is used for mobile communication, the AGC 15 is affected by fading and the amplitude and phase of the received wave fluctuate randomly.
Is used to control the amplitude of the QPSK signal to be constant.

However, when the AGC 15 is added, the circuit scale becomes large, and there is a problem that its design and adjustment are difficult and time-consuming.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a small-sized and low-cost digital communication receiver which has a small circuit configuration, simplifies design and adjustment.

[0007]

FIG. 1 shows the principle of the present invention.

In the figure, the in-phase component and the quadrature component obtained by demodulating the received digital phase modulation signal by the demodulator 1 are analog / digital converted by the AD converters 2 and 3, respectively.
The digitalized in-phase component and quadrature component are equalized by the equalizer 4 to reproduce digital data.

The detection circuit 5 envelope-detects the digital phase modulation signal to detect the amplitude of the digital phase modulation signal.

The AD converters 2 and 3 perform analog / digital conversion of the in-phase component and the quadrature component, respectively, using the amplitude detected by the detection circuit 5 as a reference voltage.

[0011]

In the present invention, since the in-phase component and the quadrature component are AD-converted using the amplitude of the digital phase modulation signal obtained by the detection circuit as the reference voltage, the reference voltage fluctuates according to the variation of the amplitude, and the in-phase component and the quadrature component The components are normalized by the amplitude, and digital data with constant amplitude can be obtained.

[0012]

2 is a block diagram of an embodiment of the receiver of the present invention. In the figure, those parts which are the same as those corresponding parts in FIG. 4 are designated by the same reference numerals, and a description thereof will be omitted.

In FIG. 2, the QPS output from the DC 14
The K signal is branched into two in the hybrid 30, and one of them is further branched into two in the hybrid 31. Hybrid 31
The QPSK signal split into two by the QPSK demodulation circuit (DE
M) 32, and an AD converter (A / D) 2 for obtaining an I signal and a Q signal by synchronously detecting the carrier wave reproduced here and the carrier wave which has been phase-shifted by π / 2
3 and 24 are supplied respectively. Further, the DEM 23 reproduces a clock having a frequency twice that of the 1 signal and the Q signal and supplies the clock to the AD converters (A / D) 23 and 24.

On the other hand, the QP branched by the hybrid 30
The SK signal is supplied to the envelope detector 35, and the amplitude is detected by performing the envelope detection here. This amplitude detection signal is phase-shifted by the phase shifter 36 so as to have the same phase as the I signal and the Q signal output from the DEM 32, and is further amplitude-adjusted by the amplifier 37 to serve as a reference voltage for the terminals of the A / D 33 and 34, respectively. It is supplied to 33a and 34a. The amplifier 37 is provided because the output of the envelope detector 35 is small.

The A / Ds 33 and 34 have terminals 33a and 34, respectively.
a The reference voltage supplied to each a is equally divided to generate 2 ⁿ -1 threshold values, and when the clock is input, the I signal and the Q signal are compared with the plurality of threshold values to generate an n-bit digital I signal. , Q signals are obtained, and these digital I signals and Q signals are supplied to the EQ 20.

Here, the QPSK signal g (t) is an in-phase component gc (t) which is an I signal and a quadrature component gs which is a Q signal.
It is expressed by the following equation by (t).

[0017] g (t) = gc (t ) cos (ωt) + gs (t) sin (ωt) = E (t) cos (ω 0 t + θ (t)) ... (1) where the amplitude E (t), The phase θ (t) is expressed as follows.

[0018]

[Equation 1]

The conventional AGC 15 is automatically adjusted so that the amplitude E (t) represented by the equation (2) is constant. On the other hand, in this embodiment, the envelope detector 35 uses the amplitude E
(T), I signal gc (t) with this amplitude E (t),
Each Q signal gs (t) is normalized. As a result, digital I and Q signals with constant amplitude are obtained.

The envelope detector 35, the phase shifter 36, and the amplifier 37 are simpler in structure than the conventional AGC 15.
Moreover, the design and adjustment can be simplified.

By the way, since the phase shifter has a simpler structure when the frequency of the phase-shifted signal is higher, the QPSK signal is phase-shifted as shown in FIG. 4 instead of the phase shifter 36 shown in FIG. A phase shifter 46 may be provided. Further down converter 14
Envelope detection of the high frequency signal supplied to
May be detected.

In the above embodiment, the present invention has been described by taking four-phase PSK signals as an example. However, the present invention is not limited to four-phase, and other PSK signals such as 16-phase and 64-phase may be used. It is not limited to the embodiment.

[0023]

As described above, according to the receiver for digital communication of the present invention, the circuit configuration is small, the design and adjustment are simplified, the size and cost are reduced, and it is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a receiver of the present invention.

FIG. 3 is a block diagram of a receiver of the present invention.

FIG. 4 is a block diagram of a conventional receiver.

[Explanation of symbols]

 1,32 Demodulator 2,3,33,34 AD converter 4 Equalizer 5 Detection circuit 36 Envelope detection circuit

Claims (1)

[Claims] 1. In-phase and quadrature components obtained by demodulating a received digital phase-modulated signal are converted from analog to digital, and equalization processing is performed from the digitized in-phase and quadrature components to obtain digital data. In a receiver for digital communication for reproduction, a detection circuit for detecting the amplitude of the digital phase modulation signal by envelope detection of the digital phase modulation signal, and the in-phase component and the quadrature component with the amplitude detected by the detection circuit as a reference voltage. A receiver for digital communication, comprising an AD converter that performs analog / digital conversion of each component.