JPH05260035A - Frame synchronizing pattern detector - Google Patents

Abstract

PURPOSE:To reduce erroneous detection and detection failour in the case of synchronizing pattern detection. CONSTITUTION:Serial received signals are converted to parallel signals by a shift register 2 and outputted to a pattern detection circuit 3. The parallel outputs or those inverted signals are impressed from the shift register 2 to AND circuits A1-A6 by the pattern detection circuit 3 and when bit error is generated only at the change point of a synchronizing pattern, a synchronizing pattern detection signal at an H level is outputted from any one of AND circuits A1-A6. Thus, synchronizing pattern detection is performed while permitting one bit error at the change point, and the generation of erroneous detection is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization pattern detecting device used in digital communication equipment, digital recording / reproducing equipment and the like.

[0002]

2. Description of the Related Art In recent years, due to the demand for higher sound quality and higher image quality, a digital system has been adopted which causes less signal deterioration during signal transmission or recording / reproduction. For example, as a device for magnetically recording a digital signal, there are a DAT (digital audio tape) for recording an audio signal, a broadcasting D-1, D-2 VTR for recording a video signal, and the like. In the digital system, it is sufficient that the receiving side or the reproducing side can distinguish "1" from "0", and a reproduced signal of high S / N can be obtained by an error correction technique based on the code theory.

In the digital transmission system, an analog signal is converted into parallel digital data for various processing, and then converted into serial data. In this case,
A frame synchronization pattern is inserted to identify the delimiter of each parallel data on the receiving side (reproducing side). The frame synchronization pattern is composed of a pattern of several bits that can be distinguished from the pattern of the main signal data, and is usually inserted at a predetermined interval for every several parallel data. This frame synchronization pattern is first detected at the time of reproduction, and has a role of dividing the main signal data according to the detected timing. Since the frame synchronization pattern is added to several parallel data at a rate of one, if the frame synchronization pattern cannot be detected, the main signals for several parallel data cannot be detected, and the main signal data The mistake is big. However, unlike the main signal data, an error correction code for correcting an error in the reproduced data cannot be added to the frame synchronization pattern.

Therefore, in the conventional frame synchronization pattern detecting apparatus, a method of comparing the pattern of the reproduced data with the synchronization pattern, allowing a difference within a predetermined number of bits, and determining that the synchronization pattern is detected is adopted. There is something to do (Reference 1 "Technology of PCM communication" by Takashi Kaneko
(Detailed in Kobunsho Publishing 1983.6.10).

That is, the admissibility of error is determined only by the number of bit errors, and does not depend on other factors. For example, a pattern which differs from the 8-bit frame synchronization pattern shown in FIG.
As shown by the underlines in (b) to (i), there are eight ways. Therefore, when the frame synchronization pattern is detected while allowing a 1-bit error, a total of 9 bits in FIGS.
The exact bit pattern will be determined as the synchronization pattern. According to Reference 1, the number P of detection patterns in the case of allowing k errors in the m-bit synchronization pattern can be expressed by the following equation (1). As is clear from the equation (1), the number P of detection patterns rapidly increases as the number of error-allowed bits k increases.

[0006] By the way, the error characteristics of the transmission system or the recording system differ depending on the transmission system, the modulation system, the recording system, the data stream, and the like. However, as described above, conventionally, error tolerance is simply based on the number of error bits. For this reason, there is a problem that a bit, which originally has a relatively low error probability, is allowed as a bit error, and the probability of error detection in the synchronization determination is relatively high.

[0007]

As described above, in the above-described conventional frame synchronization detecting apparatus, since the error bit number is the only criterion for error detection in the synchronization pattern detection, the probability of false detection is relatively high. There was a problem.

The present invention has been made in view of the above problems, and reduces the probability of erroneous detection of a synchronization pattern by performing error allowance according to the error characteristics of the transmission system in the synchronization pattern detection. It is an object of the present invention to provide a frame synchronization detection device that can perform the above.

[0009]

A frame synchronization pattern detecting apparatus according to a first aspect of the present invention receives an input digital signal and allows only an error at a bit change point of a synchronization pattern included in the input digital signal. And a pattern detection circuit that outputs a synchronization pattern detection signal when a pattern that is the same as the synchronization pattern or a pattern that is different from the synchronization pattern only in the change point is input. The frame synchronization pattern detecting apparatus according to claim 2 of the present invention receives an input digital signal, allows only an error at a bit change point of a synchronization pattern included in the input digital signal, and changes each of the synchronization patterns. For each point, calculate the coefficient based on the run length before the change point and the run length after the change point. A pattern detection circuit that outputs a degree of error occurrence based on a coefficient corresponding to a predetermined error bit, and a threshold circuit that outputs a synchronization pattern detection signal by comparing the degree of error occurrence with a predetermined threshold value. It is equipped.

[0010]

According to the first aspect of the present invention, the pattern detection circuit allows an error only at a bit change point of the synchronization pattern and does not allow an error at a non-change point. This prevents a pattern other than the synchronization pattern from being erroneously detected as a synchronization pattern.

In the second aspect of the present invention, the pattern detection circuit obtains from the coefficient set based on the run length before and after the change point of the sync pattern when an error bit occurs at the bit change point of the sync pattern. The degree of error occurrence is output. The threshold circuit detects the synchronization pattern by comparing a predetermined threshold with the degree of error occurrence. As a result, for example, it is possible to determine whether or not the error can be allowed based on the difference in run length before and after the change point, and it is possible to detect the synchronization pattern corresponding to the error characteristic.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a frame synchronization pattern detecting device according to the present invention. In this embodiment, an 8-bit frame synchronization pattern is detected.

A serial reception signal is input to the input terminal 1 and supplied to the shift register 2. The shift register 2 has the number of bits of the synchronization pattern length, bit-shifts the input reception signal, and outputs at the output terminals Q1 to Q1.
Output from 8 in parallel. This parallel output is given to the pattern detection circuit 3. The pattern detection circuit 3 assumes that the frame synchronization pattern is "11111011" and allows the 1-bit error to detect the synchronization pattern.

FIG. 2 is an explanatory diagram for explaining the frame detection circuit 3 in FIG. FIG. 2A shows a frame synchronization pattern (“11111011”), and FIG.
(C) shows a pattern in which the bit error is 1 bit.

The frame detection circuit 3 is a change point of the sync pattern from "0" (negative level) to "1" (positive level) or a change point from "1" to "0" in sync pattern detection. Considering whether or not. Now, it is assumed that the digital signal which changes stepwise is recorded on a magnetic tape or the like. In this case, the magnetization reversal of the tape does not have an ideal step shape, but becomes a mountain-shaped pulse waveform with a widened skirt (hereinafter referred to as an isolated reproduction waveform). Therefore, intersymbol interference is likely to occur between adjacent data. That is, the error occurrence probability is high at the change point of the reproduction level.

FIG. 2B is a pattern in which the 7th bit is different from the synchronization pattern, and FIG. 2C is a pattern in which the 3rd bit is different from the synchronization pattern. Figure 2 (a)
As shown in, the bits before and after the third bit of the synchronization pattern are all "1". On the other hand, in the 7th bit of the synchronization pattern, the levels of the preceding and following bits are different, the previous bit is “0”, and the subsequent bit is “1”. It is empirically known that, in this synchronization pattern, the probability of error in the third bit is low. vice versa,
At the transition point from “0” to “1” or the transition point from “1” to “0”, an error is relatively likely to occur as described above. For this reason, in the pattern detection circuit 3 of the present embodiment, only the error at the change point of the sync pattern is allowed and the error at the other portions is not allowed. Bits that can be a change point in the synchronization pattern of FIG. 2A are the first, fifth, sixth, seventh and eighth bits.
It is the bit of the bit.

That is, the pattern detection circuit 3 has inverters I1 to I8, AND circuits A1 to A8 and an OR circuit 4, and the output terminals Q1 to Q8 of the shift register 2 are connected to the inverters I1 to I8, respectively. There is.
The AND circuit A1 outputs a high level (hereinafter referred to as "H") synchronization pattern detection signal when the parallel output from the shift register 2 has the same pattern as the synchronization pattern shown in FIG. That is, parallel outputs from the terminals Q1 to Q5, Q7, Q8 of the shift register 2 are input to the AND circuit A1, and the output of the terminal Q6 is inverted and input by the inverter I6. The AND circuit A2 outputs a sync pattern detection signal of "H" when the parallel output differs from the sync pattern only in the first bit, and the terminals Q1 and Q6 of the shift register 2 are output.
The bit outputs from the inverters I1 and I6, respectively, are inverted and provided, and the other terminals Q2, Q3 and Q6 are supplied.
The bit outputs from 4, Q5, Q7 and Q8 are given as they are.

The bit output from the terminals Q5 and Q6 of the shift register 2 is applied to the inverter I5 in the AND circuit A3.
, I6 are inverted and given, and the outputs from the other terminals Q1 to Q4, Q7 and Q8 are given as they are.
The outputs from all the terminals Q1 to Q8 of the shift register 2 are given to the AND circuit A4 as they are. Similarly, only the outputs of the terminals Q6 and Q7 are connected to the inverter I in the AND circuit A5.
6 and I7 are inverted and given, and AND circuit A6
Only the outputs of terminals Q6 and Q8 are connected to inverters I6 and I8.
It is inverted and given by. In this way, the AND circuits A2 to A8 have the first, fifth, sixth, seventh,
The synchronization pattern is detected by allowing the error of the 8th bit.
The outputs of the AND circuits A1 to A8 are given to the OR circuit 4, and the OR circuit 4 calculates the logical sum of the outputs of the AND circuits A1 to A8 and outputs the sync pattern detection signal which allows a 1-bit error to the output terminal 5. Is becoming

Next, the operation of the embodiment thus constructed will be described.

Now, the received signal is input to the shift register 2 via the input terminal 1, and the output terminal Q of the shift register is input.
It is assumed that the parallel output "01111011" from 1 to Q8 is input to the pattern detection circuit 3. That is,
This received signal pattern differs from the synchronization pattern only in the first bit. The bit outputs from the terminals Q1 and Q6 are inverted by the inverters I1 and I6, and the inputs of the AND circuit A2 are all "H". As a result, the AND circuit A2
Is output to the output terminal 5 as a synchronization detection signal via the OR circuit 4. Thus, the 1-bit error of the first bit is allowed. Similarly, the synchronization pattern and the fifth, sixth
When the received signals having different patterns only in the 7th and 8th bits are input, the AND circuit A 3 to A 6 outputs the sync pattern detection signal of “H” through the OR circuit 4.

On the other hand, it is assumed that the pattern "11011011", which is different from the synchronization pattern by one bit, is output from the shift register 2. The bit output from the terminal Q3 is supplied to the AND circuits A1 to A8 without being inverted. Therefore, in this case, AND circuits A1 to A8
Are all at a low level (hereinafter referred to as "L"), and the sync pattern detection signal does not appear at the output terminal 5.

As described above, in the present embodiment, even if the pattern differs from the synchronization pattern by 1 bit, a bit error occurs in a portion other than the change point from "0" to "1" or "1" to "0". Is not permitted, and the synchronization pattern detection signal is not output. That is, the error tolerance is performed according to the error characteristic, the occurrence of erroneous detection of the synchronization pattern is reduced, and the accurate error detection is enabled.

FIG. 3 is a block diagram showing another embodiment of the present invention. In FIG. 3, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In the embodiment shown in FIG. 1, only the error at the change point of the signal is allowed. In the present embodiment, the pattern length difference at the change point, that is, the difference in run length before and after the change point of the synchronization pattern is also taken into consideration. Note that, for example, the synchronization pattern is “10111000.
The pattern length difference at the change points of the fifth bit and the sixth bit in the case of "001" is 3 for the run length before the fifth bit and 5 for the run length after the sixth bit. As described above, the reproduced waveform from the magnetic tape becomes a mountain-shaped isolated reproduced waveform, and intersymbol interference is likely to occur. Therefore, the amplitude of the isolated reproduced waveform at the identification point of another code is usually changed. The equalization is performed so as to be “0.” However, the greater the pattern length difference at the change point, the more difficult the equalization is. For this reason, in the present embodiment, only when the pattern length difference is large. Bit error is allowed.

The parallel output from the shift register 2 is R
It is input to the pattern detection circuit 11 composed of OM or the like.
The pattern detection circuit 11 has a synchronization pattern of “1111101.
The sync pattern is detected as "1", and an error at the change point is allowed, and a coefficient based on the pattern length difference between the patterns before and after the change point is output to the threshold circuit 12. That is, when the synchronization pattern and the first, fifth, sixth, seventh and eighth bits are different, a predetermined coefficient based on the pattern length of the error bit is used as the pattern detection circuit.
It is output from 11, and 0 is output when other bits are different.

A predetermined threshold value is input to the threshold circuit 12 via the terminal 13. If the coefficient from the pattern detection circuit 11 is larger than the threshold value, the threshold circuit 12 determines that the synchronization pattern has been detected. The detection signal is output to the output terminal 14. As the threshold value, a value based on the error characteristic of the transmission system or the recording system is set.

The pattern length difference must consider the bit outputs before and after the synchronization pattern. However, since the bit output before and after the synchronization pattern is unknown, in the present embodiment, when obtaining the pattern length difference between the most significant bit and the least significant bit of the synchronization pattern, both run lengths of the bit outputs before and after the synchronization pattern are determined. 4 and the run length of the bit output before and after the synchronization pattern is 2 when the pattern length difference of other bits is obtained.
That is, in the first bit of the synchronization pattern “11111011”, the pattern length difference is set to 1 on the assumption that 4-bit “0” is continuous immediately before the synchronization pattern. Similarly, the fifth, sixth, seventh, eighth
The pattern length differences at the bitth are 6, 6, 3, and 2, respectively.

The pattern detection circuit 11 sets the coefficient value based on the pattern length difference as shown in Table 1 below. The coefficient value corresponds to the probability of error occurrence. Here, for example, in FIG.
If the immediately preceding bit of the synchronization pattern in (a) is "0", the first bit is the changing point, but if it is "1", the first bit is not the changing point. With this in mind,
The pattern detection circuit 11 multiplies the coefficient in Table 1 by 0.5 and outputs it when the pattern length difference is obtained by assuming the run lengths of the bit outputs before and after the synchronization pattern.

[0029]

[Table 1] The pattern detection circuit 11 outputs 1 as a coefficient when a pattern matching the synchronization pattern is input. Further, as described above, the pattern detection circuit 11 can be configured by the ROM. Table 2 below shows an example of ROM addresses and stored coefficient values in this case.

[0030]

[Table 2] In this embodiment, a 2-bit error may be allowed. Since the probability that a 2-bit error will occur is the probability that a 1-bit error will occur repeatedly, the pattern detection circuit 11
Outputs a coefficient obtained by multiplying the coefficients based on the pattern length of each error bit to the threshold circuit 12. In this way, for example, the coefficient is set for a pattern up to a 5-bit error.

Next, the operation of the embodiment thus constructed will be described with reference to the explanatory views of FIGS. 4 and 5. 4A shows a synchronization pattern, and FIGS. 4B to 4F.
Indicate patterns in which only the 1st, 5th, 6th, 7th, and 8th bits are different from the synchronization pattern. In addition, FIG.
Shows a synchronization pattern, and FIGS. 5B to 5K show patterns in which 2 bits underlined are different from the synchronization pattern.

Now, it is assumed that a threshold value of 0.1 is applied to the threshold circuit 12 via the terminal 13 and that the pattern "11111111" is input via the input terminal 1. In this case, the pattern length difference is 6 as shown in FIG. As described above, in general, the larger the difference in the lengths of the recording waveforms (the larger the difference in the pattern lengths), the larger the non-linear distortion and the more likely an error occurs, the pattern detection circuit 11 has a relatively large coefficient. The value 0.32 is output to the threshold circuit 12 (see Table 1).
That is, the coefficient indicates the probability that this bit is erroneous when there is a bit different from each bit of the synchronization pattern in each bit output input to the pattern detection circuit 11, and in this case, the comparison is performed. Since it is a relatively large value, the sixth bit is very likely to be a bit error in the synchronization pattern.

The threshold circuit 12 compares the coefficient with a threshold. Since the coefficient is larger than the threshold, the threshold circuit 12 determines that the input pattern is the synchronization pattern and outputs the synchronization pattern detection signal to the output terminal 14.

Further, according to the setting of this threshold value, 2-bit error may be allowed. Now, it is assumed that the pattern "11110111" shown in FIG. 5 (f) is input through the input terminal 1. This pattern differs from the synchronization pattern in the 5th and 6th bits. The pattern length difference of the 5th bit is 6, and the pattern length difference of the 6th bit is also 6. Therefore, from the pattern detection circuit 11, the coefficient 0.102 (=
0.32 × 0.32) is output to the threshold circuit 12. Since the coefficient is greater than the threshold, in this case the threshold circuit
12 outputs a sync pattern detection signal to the output terminal 14. When the other patterns shown in FIGS. 5B to 5E and 5G to 5K are input, a coefficient smaller than 0.1 is output from the pattern detection circuit 11. If the threshold is set to 0.1, these 2 bit errors are not allowed.

If the threshold value is set to 0.2, for example,
Even if there is a 1-bit error at the change point, FIG.
Only four patterns (c), (d) and (e) are detected as the synchronization pattern.

As described above, in this embodiment, the allowable error bits are limited to the changing points, and the synchronization pattern is detected by comparing the coefficient based on the pattern length difference of the error bits with a predetermined threshold value. As compared with the embodiment shown in FIG. 1, it is possible to perform detection in accordance with the error characteristics, and it is possible to reduce false detection of the synchronization pattern and omission of detection, and perform accurate synchronization pattern detection. For example, in recording / reproducing, by setting the threshold value in the special reproduction to be smaller than that in the normal reproduction, it is possible to increase the error tolerance in the special reproduction and enable the reliable detection of the synchronization pattern. Although the coefficient is generated based on the pattern length difference in the present embodiment, the coefficient may be generated based on the pattern length ratio.

By the way, in order to perform high-density recording, when a digital tape is recorded by using a magnetic tape having a vertical alignment characteristic, the isolated reproduction waveform becomes asymmetric, and the asymmetry should be removed by equalization. I can't. In this case, "1" at the transition point from "0" to "1"
Often an error occurs with "0"
At the transition point from "1" to "0", an error in which "0" is set to "1" often occurs. For this reason, the pattern detection circuits 3 and 11 allow the error from the positive level to the negative level and the error from the negative level to the positive level at the change point where the received signal changes from the negative level to the positive level. Alternatively, at the change point where the received signal changes from the positive level to the negative level, the error from the negative level to the positive level may be allowed and the error from the positive level to the negative level may not be allowed.

Further, a shift register having a bit number equal to or larger than the synchronization pattern length may be adopted for the reason of obtaining the preceding and following pattern lengths.

[0039]

As described above, according to the present invention, error detection and omission of detection of a synchronization pattern can be reduced by performing error allowance in accordance with an error characteristic of a transmission system or the like in synchronization pattern detection. Has the effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame synchronization pattern detection device according to the present invention.

FIG. 2 is an explanatory diagram for explaining an example.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining the embodiment of FIG.

FIG. 5 is an explanatory diagram for explaining the embodiment of FIG.

FIG. 6 is an explanatory diagram for explaining a conventional example.

[Explanation of symbols]

 2 ... shift register, 3 ... pattern detection circuit

Claims (2)

[Claims] 1. An input digital signal is input, and a sync pattern is detected by allowing only an error at a bit change point of a sync pattern included in the input digital signal, thereby obtaining the same pattern as the sync pattern and the sync pattern. A frame synchronization pattern detection device comprising a pattern detection circuit that outputs a synchronization pattern detection signal when a pattern having only a change point different from that of the pattern is input. 2. An input digital signal is input, only an error at a bit change point of a sync pattern included in the input digital signal is allowed, and at each change point of the sync pattern, a run length and a change before the change point are changed. A pattern detection circuit that sets a coefficient based on the run length after the point and outputs the degree of error occurrence based on the coefficient corresponding to the error bit, and by comparing the degree of error occurrence with a predetermined threshold value, synchronization is achieved. A frame synchronization pattern detection device, comprising: a threshold circuit that outputs a pattern detection signal.