JPH05259760A - Input signal latch circuit - Google Patents

Abstract

PURPOSE:To reduce switching noise at the time of changeover of signal fetch and latch state in the input signal latch circuit. CONSTITUTION:The circuit consists of input signal fetch transistor differential pairs 7, 8, a transistor(TR) differential pairs 11, 12 to switch a bias current for latch TR differential pairs 9, 10, resistors 13, 14 connecting to the emitter, and a bias current source. A differential gain of the differential pair of emitter resistors 13, 14 is decreased then a bias current is not completely switched at the time of changeover between the input signal fetch state and the latch state, high frequency switching noise generated attended with current changeover is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal holding circuit, and more particularly to an input signal holding circuit used in a discriminating and reproducing circuit for converting an analog signal into a digital signal in a digital optical communication device or the like.

[0002]

2. Description of the Related Art Conventionally, an input signal holding circuit has a constant current as one transistor as described in "Transistor Logic Circuit" (P159, S43, published by Sangyo Tosho Publishing), edited by Minoru Akiyama, edited by the Board of Education for Semiconductor Electronics, USA. It used a current switching type logic that switches from one to the other.

[0003]

Generally, the receiving circuit of a digital optical communication apparatus is composed of an amplifier circuit for amplifying a minute analog signal, an identification reproducing circuit for converting an analog signal into a digital signal, and the like. In order to miniaturize the communication device, the analog signal amplification circuit and the identification reproduction circuit must be placed close to each other, and the high frequency switching noise generated by the identification reproduction circuit spills into the minute analog signal amplification circuit via the power supply circuit etc. However, there is a problem that it adversely affects the analog signal amplifier circuit. Among the identification / reproduction circuits, the input signal holding circuit switches the bias currents of the input signal input transistor differential pair and the holding differential pair at high speed, so that a large amount of high frequency noise is generated. As a method to reduce the influence of noise, separate the power supply circuit,
A method is known in which a capacitor or the like is inserted in the power supply wiring to bypass high frequency noise. However, both have drawbacks such as complicated wiring and an increase in the number of parts. An object of the present invention is to realize a simple circuit that reduces the generation of high frequency noise.

[0004]

The object is to connect a resistor to the emitters of a differential pair for switching the bias current to reduce the differential gain so that a bias current of a certain level or more is always kept on the fetch side. It is realized by flowing to both differential pairs.

[0005]

According to the present invention, the bias current is not completely switched at the time of switching between the input signal acquisition state and the holding state.
The amount of high frequency noise generated is reduced.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an input holding circuit according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG. 2 shows signal voltage waveforms at various points in the circuit shown in FIG.

The differential voltage applied to the input terminal 1 is the first
The current of the transistor differential pair 7 and 8 is changed to change the voltage generated in the load resistors 5 and 6. The voltage causes the output terminal 3 to output a differential voltage via the emitter followers 16 and 17. On the other hand, the second transistor differential pair 9, 1
0 has a collector connected to the load resistors 5 and 6 and a base connected to the output terminal 3 and serves to hold an output voltage. By changing the bias currents flowing through the two differential pairs in the third transistor differential pair 11 and 12, the input signal can be taken in and held.

The conditions when the output differential voltage V3 changes from a positive voltage to a negative voltage are as follows: the minimum input voltage V3min of the digital circuit connected to the output 3 of the circuit, the collector current I11 of the transistors 11 and 12, I12 (k =
I11 / I12), the current value I15 of the current source 15, the load resistances 5 and 6 of the resistance value Rl, and the transistors 7 and 9 are in the same communication state.

[0010]

## EQU1 ## k ≧ (I15 × R1 + V3min) / (I15 × R1-V3min). As an example, V3min = 0.4V, Rl = 20
If 00Ω and I15 = 0.3 mA, the output state can be inverted if k ≧ 5.

On the other hand, the emitter resistance Re for realizing this k is set as a capture holding switching voltage V2.

[0012]

## EQU00002 ## Re.ltoreq. ((V2-0.025.times.log k) / I15) .times. (K + 1) / (k-1). It is empirically known that it is difficult to reduce the voltage V2 to about 0.4 V or less in order to prevent the influence of noise in the circuit and the variation of the circuit. Therefore, by inserting Re of Re ≦ 1800Ω from the equation 2, it is possible to capture and hold the input signal.

[0013]

According to the present invention, it is possible to realize an input signal holding circuit having a simple circuit and less generation of high frequency noise. Also, because this circuit can be configured with only transistors and resistors,
It is also suitable for IC circuits.

[Brief description of drawings]

FIG. 1 is an input signal holding circuit diagram showing an embodiment of the present invention.

FIG. 2 is a voltage waveform diagram of each part of the embodiment shown in FIG.

[Explanation of symbols]

1 ... Signal input terminal, 2 ... Capture holding switching input terminal, 3 ... Output terminal, 4 ... Positive power supply, 5,6 ...
-Load resistance, 7, 8 ... first transistor differential pair,
9, 10 ... Second transistor differential pair, 11, 12
... Third transistor differential pair, 13, 14 ... Emitter resistance, 15 ... Bias current source, 16, 17 ...
..Emitter followers, 18, 19 ... Bias current sources for emitter followers.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiro Hayami 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Information & Communication Division

Claims (1)

[Claims] 1. A pair of transistor differential pairs, a load resistance connected to the differential pair, a third transistor differential pair for determining a bias current flowing through the differential pair, and a bias current source. The differential input voltage is applied to the base of the first differential pair, and the differential output voltage generated in the load resistance is applied to the base of the second differential pair. In a circuit that switches between capturing and holding an input voltage by changing the value of a bias current flowing in a differential pair, a resistor is connected to the emitter of the third differential pair to reduce the differential gain of the differential pair, An input signal holding circuit, characterized in that a current is always supplied to the first and second differential pairs at a constant current or more.