JPH05259348A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05259348A
JPH05259348A JP8957692A JP8957692A JPH05259348A JP H05259348 A JPH05259348 A JP H05259348A JP 8957692 A JP8957692 A JP 8957692A JP 8957692 A JP8957692 A JP 8957692A JP H05259348 A JPH05259348 A JP H05259348A
Authority
JP
Japan
Prior art keywords
base body
outer terminals
semiconductor device
type
external terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8957692A
Other languages
Japanese (ja)
Inventor
Isamu Ozuru
勇 大▲鶴▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP8957692A priority Critical patent/JPH05259348A/en
Publication of JPH05259348A publication Critical patent/JPH05259348A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PURPOSE:To miniaturize a base body with an area to provide outer terminals secured enough by providing outer terminals on at least two faces out of side faces including the top and bottom faces and the ridges of a box-shaped base body. CONSTITUTION:The top face of a base body 1 is provided with gull-wing type outer terminals 3, and its bottom with surface-mounted type pin type outer terminals 4. Since a plurality of points in the bottom, top, and side faces have outer terminals, the base body can be miniaturized as compared with the case where outer terminals are so many as those in a prior art semiconductor device. Further mounting density can be increased by narrowing the occupancy area in high-density board mounting.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
高密度な基板実装を必要とされる半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device which requires high-density board mounting.

【0002】[0002]

【従来の技術】従来の半導体装置は図4,図5に示すよ
うに、ボックス型形状の基体1の内部にICチップ2a
が設けられている。2bは封止用キャップである。
2. Description of the Related Art As shown in FIGS. 4 and 5, a conventional semiconductor device includes an IC chip 2a inside a box-shaped substrate 1.
Is provided. 2b is a cap for sealing.

【0003】そして、ICチップ2aに信号を入出力す
る外部端子4は、基体1の下面領域に集中して設けられ
ていた。
The external terminals 4 for inputting / outputting signals to / from the IC chip 2a are centrally provided in the lower surface region of the base 1.

【0004】[0004]

【発明が解決しようとする課題】従来の半導体装置で
は、外部端子4が基体1の下面に集積して設けられてい
るため、ICチップ2aの多ピン化が促進されて外部端
子4の本数が増加するのに伴い、基体1の下面の面積を
拡大する必要があり、それに従って基体の外形寸法が大
きくなる。このことは、実装基板上で基体が占める面積
が大きくなり、一枚の基板あたりの半導体装置の実装数
が減り、高密度な実装に悪影響を及ぼすという欠点があ
った。
In the conventional semiconductor device, since the external terminals 4 are integrated and provided on the lower surface of the substrate 1, the number of external terminals 4 is increased by promoting the increase in the number of pins of the IC chip 2a. It is necessary to increase the area of the lower surface of the base body 1 as the number increases, and the outer dimensions of the base body increase accordingly. This has a drawback that the area occupied by the base on the mounting substrate increases, the number of semiconductor devices mounted per substrate decreases, and the high-density mounting is adversely affected.

【0005】本発明の目的は、半導体装置の基体の外形
寸法を小さくすることにより、実装密度を高めた半導体
装置を提供することにある。
An object of the present invention is to provide a semiconductor device having a high packaging density by reducing the outer dimensions of the base of the semiconductor device.

【0006】[0006]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、ボックス型形状の基体
に外部端子を有する半導体装置であって、前記基体の上
面,下面,陵線部を含む側面のうち、少なくとも2面の
領域に外部端子を設けたものである。
In order to achieve the above-mentioned object, a semiconductor device according to the present invention is a semiconductor device having a box-shaped base body and external terminals, the top surface, the bottom surface, and the ridge portion of the base body. The external terminals are provided in at least two areas of the side surface including the.

【0007】[0007]

【作用】基体の複数の面(陵線部を含む)に外部端子を
分散させて配置することにより、外部端子を設ける領域
を十分に確保し、基体の小型化を図る。
By disposing the external terminals on a plurality of surfaces (including the ridge line portion) of the base in a dispersed manner, a region for providing the external terminals is sufficiently secured and the base is miniaturized.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。図において、本発明は、ボックス型形状の基体1の
上面,下面,陵線部を含む側面のうち、少なくとも2面
に外部端子を設けたものである。
The present invention will be described below with reference to the drawings. In the drawings, according to the present invention, external terminals are provided on at least two of the upper surface, the lower surface, and the side surface including the ridgeline of the box-shaped base 1.

【0009】図1に示す半導体装置は、基体1の上面に
ガルウイングタイプ外部端子3を設け、しかも基体1の
底面に表面実装型ピンタイプ外部端子4を設けている。
2aはICチップ、2bは封止キャップである。
In the semiconductor device shown in FIG. 1, a gull wing type external terminal 3 is provided on the upper surface of the base body 1, and a surface mount type pin type external terminal 4 is provided on the bottom surface of the base body 1.
2a is an IC chip and 2b is a sealing cap.

【0010】図2の半導体装置は、基体1の上面にJリ
ードタイプ外部端子5を設け、しかも基体1の底面にラ
ンド・グリッド・アレイ(LGA)形外部端子6を設け
ている。
In the semiconductor device of FIG. 2, J lead type external terminals 5 are provided on the upper surface of the base body 1, and further, land grid array (LGA) type external terminals 6 are provided on the bottom surface of the base body 1.

【0011】図3の半導体装置は、基体1の側面にピン
挿入形(DIPタイプ)外部端子7とを設け、しかも基
体1の底面にピン挿入形(PGAタイプ)外部端子8を
設けている。
In the semiconductor device of FIG. 3, a pin insertion type (DIP type) external terminal 7 is provided on the side surface of the base body 1, and a pin insertion type (PGA type) external terminal 8 is provided on the bottom surface of the base body 1.

【0012】[0012]

【発明の効果】以上説明したように本発明は、基体の底
面,上面,側面のうち、複数箇所に外部端子を有するの
で、外部端子数従来の半導体装置と外部端子が同数の場
合に、従来よりも基体を小さくすることができ、高密度
な基板実装において占有面積を狭くして実装密度を高め
ることができるという効果を有する。
As described above, according to the present invention, the external terminals are provided at a plurality of positions on the bottom surface, the upper surface, and the side surfaces of the base body. Therefore, when the number of external terminals is the same as that of the conventional semiconductor device, It is possible to reduce the size of the base body, and it is possible to increase the mounting density by narrowing the occupied area in high-density board mounting.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は、本発明の一実施例を示す斜視図、
(b)は断面図である。
FIG. 1A is a perspective view showing an embodiment of the present invention,
(B) is a sectional view.

【図2】本発明の他の実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the present invention.

【図3】本発明の他の実施例を示す断面図である。FIG. 3 is a sectional view showing another embodiment of the present invention.

【図4】(a)は、従来例を示す斜視図、(b)は断面
図である。
4A is a perspective view showing a conventional example, and FIG. 4B is a sectional view.

【図5】従来例を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

1 基体 2a ICチップ 2b 封止キャップ 3 ガルウイングタイプ外部端子 4 ピンタイプ外部端子 5 Jリードタイプ外部端子 6 ランドタイプ外部端子 7 ピン挿入形(DIPタイプ)外部端子 8 ピン挿入形(PGAタイプ)外部端子 1 Base 2a IC chip 2b Sealing cap 3 Gull wing type external terminal 4 Pin type external terminal 5 J Lead type external terminal 6 Land type external terminal 7 Pin insertion type (DIP type) external terminal 8 pin insertion type (PGA type) external terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ボックス型形状の基体に外部端子を有す
る半導体装置であって、 前記基体の上面,下面,陵線部を含む側面のうち、少な
くとも2面の領域に外部端子を設けたことを特徴とする
半導体装置。
1. A semiconductor device having an external terminal on a box-shaped base, wherein the external terminal is provided on an area of at least two of the upper surface, the lower surface, and the side surface including the ridge. Characteristic semiconductor device.
JP8957692A 1992-03-13 1992-03-13 Semiconductor device Pending JPH05259348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8957692A JPH05259348A (en) 1992-03-13 1992-03-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8957692A JPH05259348A (en) 1992-03-13 1992-03-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05259348A true JPH05259348A (en) 1993-10-08

Family

ID=13974630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8957692A Pending JPH05259348A (en) 1992-03-13 1992-03-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05259348A (en)

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