JPH05258562A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To satisfactorily restore data to a cell without restricting the capability of fRAS by changing the time-setting of active time-out in accordance with normal operation time and self refresh time. CONSTITUTION:Since a self refresh mode signal phiS is H level at the time of self refresh mode, an output from a delay circuit 84 depends on a sense amplifier activating signal phiSA. A time-out signal phito is H level at initial state and falling time, then becomes L level. Thereafter, when the signal phiSA rises, the output of an inverter 80 becomes L level after prescribed delay time. However, the output of a circuit 84 is still H level at this time and becomes L level after prescribed delay time by the circuit 84, and the signal phito becomes H level after this delay time tD. Therefore, the signal phito becomes H level from L level after time tD by the circuit 84 comparing with normal operation time at the time of self refresh mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a self refresh function.

In recent years, electronic devices have been downsized, and the number of battery-operated electronic devices has increased to make them portable. Particularly in the case of small electronic devices, the disk cannot be used because of restrictions on power supply capacity, miniaturization, etc., and the environment for holding data is not blessed. Therefore, the electrical I
C memory is used, but DRAM is one of the IC memories
Unlike SRAM, refresh operation is required to prevent loss of data, and thus consumes much power. However, in the case of battery operation, there is a limit to the power supply capability, so it is required to reduce power consumption as much as possible. This reduction in power consumption must also be considered in the refresh operation. There is a self-refresh mode as a device for that purpose. The self-refresh mode does not access data, but periodically performs only RAS-only refresh in response to a refresh signal from a refresh timer (on-chip refresh timer) on a memory chip to suppress the minimum power consumption required. Is the operation mode.

On the other hand, a timeout is set in the IC memory, and if this timeout is long, the ability of t _RAS may be limited. On the contrary, if the time-out is shortened, the amount of charge in the cell is small, and it is not possible to sufficiently restore the data in the cell in the self-refresh mode. Therefore, it is desired to properly set the timeout in the semiconductor memory device having the self-refresh function.

[0004]

2. Description of the Related Art FIG. 4 shows a timing chart of a conventional semiconductor memory device. In FIG. 4, RAS
When drops, drops the time-out signal (internal RAS) _phi-to, then the voltage V _w of the word line rises, the activation signal phi _SA of the sense amplifier in the cell is increased. When the sense amplifier activation signal φ _SA rises, the bit lines BL, B
The voltages V _BL and V _BL of L are amplified by the sense amplifier, the voltage V _BL rises from the reference voltage V _ref , and the voltage V _BL falls from the reference voltage V _ref . When the voltage V _BL rises and the voltage V _BL falls, the timeout signal φ _to becomes
It rises and then the voltage V _{w on the} word line falls. Here, the time from the fall of RAS to the drop of the word line voltage V _w is t _RAS .

The time-out signal φ _to falls according to RAS and rises according to the sense amplifier activation signal φ _SA . The configuration for this purpose is shown in the main circuit of FIG. There is.

In FIG. 5, RAS is a NOR gate 1
0 is supplied to one input terminal of the NOR gate 10, and the output of the NOR gate 10 is NANDed via an inverter (inversion circuit) 12.
It is supplied to one input terminal of the gate 14. The RAS is directly supplied to the other input terminal of the NAND gate 14, and the output of the NAND gate 14 passes through the inverter 16 and becomes the time-out signal φ _to . A sense amplifier activation signal φ _SA is supplied to the other input terminal of the NOR gate 10 via inverters 18 and 20.

Next, the operation of the main circuit of FIG. 5 will be described with reference to the timing chart of FIG. First, in the initial state, RAS is at "H" level and sense amplifier activation signal φ _SA is at "L" level, so timeout signal φ _to is at "H" level. After that, when RAS falls, that is, goes to "L" level, the timeout signal φ
_{The to} goes down, that is, becomes "L" level after a predetermined delay by the gates 10 and 14 and the inverters 12 and 16. After that, when the sense amplifier activation signal φ _SA rises, that is, when it becomes “H” level, the timeout signal φ _to
Are gates 10 and 14 and inverters 12, 16 and 1
After a predetermined delay of 8,20, it rises or is "H"
Become a level.

As described above, according to the circuit of FIG.
The timeout signal φ _to is changed based on S and the sense amplifier activation signal φ _SA .

[0009]

In the conventional semiconductor memory device, the active time-out is set as long as possible within a range not exceeding t _RAS (see FIG. 4) in the catalog (specification). However, if the time-out period is set to be long, the ability of t _{RAS in} the specifications may be limited.

On the contrary, if the time-out time is shortened,
As shown in FIG. 4, the voltage V _{w of the} word line decreases before the voltages V _BL and V _BL of the bit lines BL and BL completely increase or decrease, respectively. As a result, in the self-refresh mode, the data cannot be sufficiently restored in the cell. Then, since the amount of electric charge in the cell is small, the refresh interval cannot be extended longer than the normal time during the internal automatic refresh, and the power consumption increases.

Therefore, an object of the present invention is to provide a semiconductor memory device which can sufficiently restore data to a cell without limiting the ability of t _RAS .

[0012]

According to the present invention, in a semiconductor memory device having a self-refresh function of automatically refreshing internally, a time-out is set, a means (RAS) for starting the time-out, and the time-out. the means (phi _SA) to terminate, characterized in that it comprises a means (83) for delaying the end of the timeout based on the signal (phi _S) indicating the self-refresh mode.

[0013]

In the present invention, the active timeout time setting is changed between normal operation and self refresh. That is, when the signal (φ _S ) indicating the self-refresh mode is received, the end of the active time-out is delayed compared to the normal operation.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. First, FIG. 3 shows the entire circuit of the semiconductor memory device.

In FIG. 3, reference numeral 30 denotes a memory array and a sense amplifier. A row address decoder 32 is connected to the memory array and the sense amplifier 30 via word lines WL _{1 to} WL _m , and a column line. the column address decoder 34 via the CL ₁ -CL _l is connected. RA ₀ , RA ₁ , RA _{2 to} RA
_n-1 is connected to the row address decoder 32 via row address buffers 36 to 36 and an address selector 38, and CA ₀ and CA _{1 to} CA _n-1 are connected to the column via a column address buffer 40. It is connected to the address decoder 34.

The memory array and sense amplifier 30
DB of₁・ DB₁~ DB_n・ DB _nIs the sensebuff
Is supplied to the output buffer 44 through the output buffer 42.
The buffer 44 is controlled by the output control circuit 46. Out
The output from the force buffer 44 is DQ₁~ DQ_nTo become and
Both are supplied to the data input buffers 48 to 48, and
The outputs from the data input buffers 48 to 48 are write unselected.
Is supplied to the 50. The write amplifier 50 is a write control circuit.
Controlled by 52, the memory array and sense amplifier
Connected to the group 30.

RAS and CAS are supplied to the row control circuit 54 and the column control circuit 56, respectively, and the row address latch clock 58 from the row control circuit 54 is supplied to the row address buffers 36 to 36.
A column address latch clock 60 from the column control circuit 56 is supplied to the column address buffers 40-40. The column control circuit 56 is supplied with the signal 62 to the write amplifier 50.

Reference numeral 64 indicates a self-refresh counter, the count value from the counter 64 is supplied to a self-refresh timer 66, and the timer value from the timer 66 is supplied to a CBR counter 68. CBR
The counter value from the counter 68 is supplied to the address selector 38, and the address selector 38 outputs the CBR.
Either the counter value from the counter 68 or the signals from the row address buffers 36 to 36 is supplied to the row address decoder 32. That is, when the address selector 38 supplies the counter value from the CBR counter 68 to the row address decoder 32, the memory array and sense amplifier 30 performs a self-refresh operation, while the address selector 38 causes the row address buffer 36 to When the signal from 36 is supplied to the row address decoder 32, the memory array and sense amplifier 30 operates normally.

The RAS and CAS are supplied to the CBR judging circuit 70, and the C from the CBR judging circuit 70 is supplied.
The BR judgment signal 72 is supplied to the self-refresh counter 64 and the CBR counter 68. The signal 74 from the self-refresh timer 66 is supplied to the row control circuit 54.

The row control circuit 54 has information regarding active time-out, and the self-refresh counter 64, self-refresh timer 66,
The CBR counter 68 allows the memory array and sense amplifier 30 to perform a self-refresh operation.

Next, FIG. 1 shows a timing chart of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, the same parts as those in the timing chart of FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, in normal operation, the time until the timeout signal φ _to falls from the “H” level to the “L” level and then rises from the “L” level to the “H” level, that is, the time t _NOR is the catalog. (Specification) t
Within the range of _RAS, the time is set so that cell data can be retained at normal refresh intervals. Therefore, t _RAS
There is no limit to your ability.

On the other hand, in the self refresh mode,
Timeout signal φ_toIs from "H" level to "L" level
The time when the temperature drops to
Mu-out signal φ_toGoes from "L" level to "H" level
The time of rising is different from that during normal operation, that is,
Predetermined time t from the case of normal operation_DHas been delayed.
Thus, the timeout signal φ_toFrom "H" level
It goes down to "L" level and then goes from "L" level to "H" level.
The time required to rise to the bell is t during normal operation. _NORThan
Since it is set for a long time, restore the data to the cell.
It can be done enough.

As described above, the time setting of the time-out signal φ _to is changed between the normal operation and the self refresh, and the configuration for this is shown in the main circuit of FIG. In FIG. 2, the same parts as those of the main circuit of FIG. 5 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 2, RAS is a NOR gate 10.
Is supplied to one input end of the NAND gate 14 and one input end of the NAND gate 14, and the fall of the time-out signal φ _to from the inverter 16 is controlled by the RAS. The sense amplifier activation signal φ _SA is NO through the inverter 80.
The signal from the NOR gate 82 is supplied to one input terminal of the R gate 82, and is supplied to the other input terminal of the NOR gate 10 by the sense amplifier activation signal φ _SA .
The rising of the time-out signal φ _to from the inverter 16 is controlled.

Reference numeral 84 represents a delay circuit, which includes one NOR gate 86 and five inverters 88, 90, 92, 94 and 96. Here, the sense amplifier activation signal φ _SA is supplied to the inverter 88, the self-refresh mode signal φ _S is supplied to the inverter 96, and the signal from the NOR gate 86 is
It is adapted to be supplied to the other input end of the NOR gate 82. Note that the self-refresh mode signal φ
_S is at "H" level in the self refresh mode and at "L" level in normal operation.

Next, the operation of the main circuit of FIG. 2 will be described with reference to the timing chart of FIG. First, the normal operation will be described. In this case, since the self-refresh mode signal φ _S is at “L” level, the output from the delay circuit 84 is always at “L” level and NOR.
The gate 82 performs the same operation as an inverter.

In the initial state, RAS is at "H" level and sense amplifier activation signal φ _SA is at "L" level, so timeout signal φ _to is at "H" level. After that, when RAS falls, that is, goes to "L" level,
The time-out signal φ _to goes down, that is, becomes “L” level after a predetermined delay by the gates 10 and 14 and the inverters 12 and 16. After that, when the sense amplifier activation signal φ _SA rises, that is, goes _{to the} “H” level, the timeout signal φ _to rises, that is, ““ after a predetermined delay due _to the gates 10, 14, 82 and the inverters 12, 16, 80. H level.

Next, the self-refresh mode will be described. In this case, self-refresh mode signal φ _S is at “H” level, and therefore the output from delay circuit 84 depends on sense amplifier activation signal φ _SA .

The time-out signal φ _to is at the “H” level in the initial state and at the fall, as in the normal operation, and then falls to the “L” level. After that, when the sense amplifier activation signal φ _SA rises, that is, “H”
At the level, the output of the inverter 80, that is, NOR
One input of the gate 82 becomes "L" level after a predetermined delay by the inverter 80. However, at this time, the output of the delay circuit 84, that is, the other input of the NOR gate 82 is still at the “H” level, and the delay circuit 84
After a predetermined delay by (after delay time t _{D in} FIG. 1),
It goes to "L" level, and after this delay time t _D , the timeout signal φ _to rises to "H" level.

Therefore, in the self-refresh mode, the time-out signal φ _to rises from the “L” level to the “H” level after the delay time t _D by the delay circuit 84 as compared with the normal operation.

[0032]

As described above, according to the present invention,
The time-out time setting is changed between normal operation and self-refresh, that is, the time-out time during self-refresh is set longer than the time-out time during normal operation. Therefore, it is possible to sufficiently restore data to a cell without limiting the ability of t _RAS , and it is possible to reduce power consumption during data retention in a semiconductor memory device having a self-refresh function. ..

[Brief description of drawings]

FIG. 1 is a timing chart of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is an overall circuit diagram of a semiconductor memory device.

FIG. 4 is a timing chart of a conventional semiconductor memory device.

FIG. 5 is a circuit diagram of a main part of a conventional semiconductor memory device.

[Explanation of symbols]

84 ... delay circuit φ _to ... time-out signal φ _SA ... the sense amplifier activation signal φ _S ... self-refresh mode signal of

Claims (1)

[Claims] 1. In a semiconductor memory device having a self-refresh function for automatically refreshing internally and setting a timeout, a means for starting the timeout (RAS) and a means for ending the timeout (φ _SA ). And a means (83) for delaying the end of the timeout based on the signal (φ _S ) indicating the self-refresh mode.